CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: gutteridge Date: Tue Mar 19 01:19:11 UTC 2024 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl.8: fix grammar in a sentence To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/cpuctl/cpuctl.8 diff -u src/usr.sbin/cpuctl/cpuctl.8:1.22 src/usr.sbin/cpuctl/cpuctl.8:1.23 --- src/usr.sbin/cpuctl/cpuctl.8:1.22 Tue Sep 12 20:45:17 2023 +++ src/usr.sbin/cpuctl/cpuctl.8 Tue Mar 19 01:19:11 2024 @@ -1,4 +1,4 @@ -.\" $NetBSD: cpuctl.8,v 1.22 2023/09/12 20:45:17 wiz Exp $ +.\" $NetBSD: cpuctl.8,v 1.23 2024/03/19 01:19:11 gutteridge Exp $ .\" .\" Copyright (c) 2007, 2008, 2012, 2015 The NetBSD Foundation, Inc. .\" All rights reserved. @@ -83,7 +83,7 @@ already exists on the CPU in question ar If .Ar cpu is not specified or \-1, all CPUs are updated. -(AMD CPU updates need to be update all CPUs at once.) +(AMD CPU updates need to update all CPUs at once.) If .Ar cpu is \-2, the current CPUs are updated.
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: gutteridge Date: Tue Mar 19 01:19:11 UTC 2024 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl.8: fix grammar in a sentence To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Jan 18 03:19:27 UTC 2024
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add Meteor Lake and Emerald Rapids.
To generate a diff of this commit:
cvs rdiff -u -r1.141 -r1.142 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.141 src/usr.sbin/cpuctl/arch/i386.c:1.142
--- src/usr.sbin/cpuctl/arch/i386.c:1.141 Wed Sep 13 06:53:23 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Jan 18 03:19:26 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.141 2023/09/13 06:53:23 wiz Exp $ */
+/* $NetBSD: i386.c,v 1.142 2024/01/18 03:19:26 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.141 2023/09/13 06:53:23 wiz Exp $");
+__RCSID("$NetBSD: i386.c,v 1.142 2024/01/18 03:19:26 msaitoh Exp $");
#endif /* not lint */
#include
@@ -361,10 +361,12 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa6] = "10th gen Core (Comet Lake)",
[0xa7] = "11th gen Core (Rocket Lake)",
[0xa8] = "11th gen Core (Rocket Lake)",
+[0xaa] = "Core Ultra 7 (Meteor Lake)",
[0xb7] = "13th gen Core (Raptor Lake)",
[0xba] = "13th gen Core (Raptor Lake)",
[0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)",
[0xbf] = "13th gen Core (Raptor Lake)",
+[0xcf] = "5th gen Xeon Scalable (Emerald Rapids)",
},
"Pentium Pro, II or III", /* Default */
NULL,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Jan 18 03:19:27 UTC 2024 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Add Meteor Lake and Emerald Rapids. To generate a diff of this commit: cvs rdiff -u -r1.141 -r1.142 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src
Committed By: wiz
Date: Wed Sep 13 06:53:23 UTC 2023
Modified Files:
src/usr.sbin/cpuctl: cpuctl.c
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
tabify
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/usr.sbin/cpuctl/cpuctl.c
cvs rdiff -u -r1.140 -r1.141 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/cpuctl.c
diff -u src/usr.sbin/cpuctl/cpuctl.c:1.34 src/usr.sbin/cpuctl/cpuctl.c:1.35
--- src/usr.sbin/cpuctl/cpuctl.c:1.34 Tue Sep 12 20:43:38 2023
+++ src/usr.sbin/cpuctl/cpuctl.c Wed Sep 13 06:53:23 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl.c,v 1.34 2023/09/12 20:43:38 wiz Exp $ */
+/* $NetBSD: cpuctl.c,v 1.35 2023/09/13 06:53:23 wiz Exp $ */
/*-
* Copyright (c) 2007, 2008, 2009, 2012, 2015 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#ifndef lint
#include
-__RCSID("$NetBSD: cpuctl.c,v 1.34 2023/09/12 20:43:38 wiz Exp $");
+__RCSID("$NetBSD: cpuctl.c,v 1.35 2023/09/13 06:53:23 wiz Exp $");
#endif /* not lint */
#include
@@ -247,8 +247,8 @@ cpu_ucode(char **argv)
cpuset_destroy(cpuset);
}
error = ioctl(fd, IOC_CPU_UCODE_APPLY, );
-if (error < 0 && (verbose || errno != EEXIST)) {
-warnx("please also check dmesg(8) output for additional error information");
+ if (error < 0 && (verbose || errno != EEXIST)) {
+ warnx("please also check dmesg(8) output for additional error information");
if (uc.fwname[0])
err(EXIT_FAILURE, "%s", uc.fwname);
else
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.140 src/usr.sbin/cpuctl/arch/i386.c:1.141
--- src/usr.sbin/cpuctl/arch/i386.c:1.140 Tue Sep 12 20:43:38 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Sep 13 06:53:23 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.140 2023/09/12 20:43:38 wiz Exp $ */
+/* $NetBSD: i386.c,v 1.141 2023/09/13 06:53:23 wiz Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.140 2023/09/12 20:43:38 wiz Exp $");
+__RCSID("$NetBSD: i386.c,v 1.141 2023/09/13 06:53:23 wiz Exp $");
#endif /* not lint */
#include
@@ -2584,8 +2584,8 @@ ucodeupdate_check(int fd, struct cpu_uco
switch (loader_version) {
case CPU_UCODE_LOADER_AMD:
-if (uc->cpu_nr != -1) {
-warnx("ucode updates on AMD can only be done on all CPUs at once");
+ if (uc->cpu_nr != -1) {
+ warnx("ucode updates on AMD can only be done on all CPUs at once");
return -1;
}
uc->cpu_nr = CPU_UCODE_ALL_CPUS;
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: wiz Date: Wed Sep 13 06:53:23 UTC 2023 Modified Files: src/usr.sbin/cpuctl: cpuctl.c src/usr.sbin/cpuctl/arch: i386.c Log Message: tabify To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35 src/usr.sbin/cpuctl/cpuctl.c cvs rdiff -u -r1.140 -r1.141 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: wiz Date: Tue Sep 12 20:45:17 UTC 2023 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl(8): note that AMD updates need to be applied on all CPUs at once Note that checking dmesg(8) after problems might be helpful. Sort commands. Bump date. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/cpuctl/cpuctl.8 diff -u src/usr.sbin/cpuctl/cpuctl.8:1.21 src/usr.sbin/cpuctl/cpuctl.8:1.22 --- src/usr.sbin/cpuctl/cpuctl.8:1.21 Mon Mar 6 01:28:54 2023 +++ src/usr.sbin/cpuctl/cpuctl.8 Tue Sep 12 20:45:17 2023 @@ -1,4 +1,4 @@ -.\" $NetBSD: cpuctl.8,v 1.21 2023/03/06 01:28:54 kre Exp $ +.\" $NetBSD: cpuctl.8,v 1.22 2023/09/12 20:45:17 wiz Exp $ .\" .\" Copyright (c) 2007, 2008, 2012, 2015 The NetBSD Foundation, Inc. .\" All rights reserved. @@ -27,7 +27,7 @@ .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE .\" POSSIBILITY OF SUCH DAMAGE. .\" -.Dd May 17, 2019 +.Dd September 12, 2023 .Dt CPUCTL 8 .Os .Sh NAME @@ -51,9 +51,13 @@ Valid commands are: .It identify Ar cpu Op Ar cpu ... Output information on the specified CPU's features and capabilities. Not available on all architectures. +.It intr Ar cpu Op Ar cpu ... +Enable interrupts for the specified CPUs if supported. .It list For each CPU in the system, display the current state and time of the last state change. +.It nointr Ar cpu Op Ar cpu ... +Disable interrupts for the specified CPUs if supported. .It offline Ar cpu Op Ar cpu ... Set the specified CPUs off line. .Pp @@ -79,22 +83,28 @@ already exists on the CPU in question ar If .Ar cpu is not specified or \-1, all CPUs are updated. +(AMD CPU updates need to be update all CPUs at once.) If .Ar cpu is \-2, the current CPUs are updated. The default filename is used if no filename is specified. The +.Ar file +pathname containing the ucode updates are searched relative to the +default firmware path found in +.Xr sysctl 7 +.Pa hw.firmware.path . +The .Cm identify command prints the installed version on the specified CPUs. On success the .Cm identify command shows different ucode versions before and after this command. -The ucode updates are found in the default firmware path found in -sysctl hw.firmware.path. -.It intr Ar cpu Op Ar cpu ... -Enable interrupts for the specified CPUs if supported. -.It nointr Ar cpu Op Ar cpu ... -Disable interrupts for the specified CPUs if supported. +.Pp +Some problems will only be reported in the kernel message buffer, +so check +.Xr dmesg 8 +in case of errors. .El .Pp Valid flags are:
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: wiz Date: Tue Sep 12 20:45:17 UTC 2023 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl(8): note that AMD updates need to be applied on all CPUs at once Note that checking dmesg(8) after problems might be helpful. Sort commands. Bump date. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src
Committed By: wiz
Date: Tue Sep 12 20:43:38 UTC 2023
Modified Files:
src/usr.sbin/cpuctl: cpuctl.c
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
cpuctl: be more verbose about problems and diagnosing them
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/usr.sbin/cpuctl/cpuctl.c
cvs rdiff -u -r1.139 -r1.140 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/cpuctl.c
diff -u src/usr.sbin/cpuctl/cpuctl.c:1.33 src/usr.sbin/cpuctl/cpuctl.c:1.34
--- src/usr.sbin/cpuctl/cpuctl.c:1.33 Mon Mar 6 01:28:54 2023
+++ src/usr.sbin/cpuctl/cpuctl.c Tue Sep 12 20:43:38 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl.c,v 1.33 2023/03/06 01:28:54 kre Exp $ */
+/* $NetBSD: cpuctl.c,v 1.34 2023/09/12 20:43:38 wiz Exp $ */
/*-
* Copyright (c) 2007, 2008, 2009, 2012, 2015 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#ifndef lint
#include
-__RCSID("$NetBSD: cpuctl.c,v 1.33 2023/03/06 01:28:54 kre Exp $");
+__RCSID("$NetBSD: cpuctl.c,v 1.34 2023/09/12 20:43:38 wiz Exp $");
#endif /* not lint */
#include
@@ -247,7 +247,8 @@ cpu_ucode(char **argv)
cpuset_destroy(cpuset);
}
error = ioctl(fd, IOC_CPU_UCODE_APPLY, );
- if (error < 0 && (verbose || errno != EEXIST)) {
+if (error < 0 && (verbose || errno != EEXIST)) {
+warnx("please also check dmesg(8) output for additional error information");
if (uc.fwname[0])
err(EXIT_FAILURE, "%s", uc.fwname);
else
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.139 src/usr.sbin/cpuctl/arch/i386.c:1.140
--- src/usr.sbin/cpuctl/arch/i386.c:1.139 Fri Jul 21 10:26:36 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Tue Sep 12 20:43:38 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.139 2023/07/21 10:26:36 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.140 2023/09/12 20:43:38 wiz Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.139 2023/07/21 10:26:36 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.140 2023/09/12 20:43:38 wiz Exp $");
#endif /* not lint */
#include
@@ -2584,8 +2584,8 @@ ucodeupdate_check(int fd, struct cpu_uco
switch (loader_version) {
case CPU_UCODE_LOADER_AMD:
- if (uc->cpu_nr != -1) {
- /* printf? */
+if (uc->cpu_nr != -1) {
+warnx("ucode updates on AMD can only be done on all CPUs at once");
return -1;
}
uc->cpu_nr = CPU_UCODE_ALL_CPUS;
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: wiz Date: Tue Sep 12 20:43:38 UTC 2023 Modified Files: src/usr.sbin/cpuctl: cpuctl.c src/usr.sbin/cpuctl/arch: i386.c Log Message: cpuctl: be more verbose about problems and diagnosing them To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/usr.sbin/cpuctl/cpuctl.c cvs rdiff -u -r1.139 -r1.140 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Fri Jul 21 10:26:36 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Sort by number. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.138 -r1.139 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.138 src/usr.sbin/cpuctl/arch/i386.c:1.139
--- src/usr.sbin/cpuctl/arch/i386.c:1.138 Thu Jul 6 02:43:44 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Jul 21 10:26:36 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.138 2023/07/06 02:43:44 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.139 2023/07/21 10:26:36 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.138 2023/07/06 02:43:44 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.139 2023/07/21 10:26:36 msaitoh Exp $");
#endif /* not lint */
#include
@@ -361,8 +361,8 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa6] = "10th gen Core (Comet Lake)",
[0xa7] = "11th gen Core (Rocket Lake)",
[0xa8] = "11th gen Core (Rocket Lake)",
-[0xba] = "13th gen Core (Raptor Lake)",
[0xb7] = "13th gen Core (Raptor Lake)",
+[0xba] = "13th gen Core (Raptor Lake)",
[0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)",
[0xbf] = "13th gen Core (Raptor Lake)",
},
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Fri Jul 21 10:26:36 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Sort by number. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.138 -r1.139 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Jul 6 02:43:44 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add Alder Lake-N.
To generate a diff of this commit:
cvs rdiff -u -r1.137 -r1.138 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.137 src/usr.sbin/cpuctl/arch/i386.c:1.138
--- src/usr.sbin/cpuctl/arch/i386.c:1.137 Wed Jul 5 02:54:37 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Jul 6 02:43:44 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.137 2023/07/05 02:54:37 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.138 2023/07/06 02:43:44 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.137 2023/07/05 02:54:37 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.138 2023/07/06 02:43:44 msaitoh Exp $");
#endif /* not lint */
#include
@@ -363,6 +363,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa8] = "11th gen Core (Rocket Lake)",
[0xba] = "13th gen Core (Raptor Lake)",
[0xb7] = "13th gen Core (Raptor Lake)",
+[0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)",
[0xbf] = "13th gen Core (Raptor Lake)",
},
"Pentium Pro, II or III", /* Default */
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Jul 6 02:43:44 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Add Alder Lake-N. To generate a diff of this commit: cvs rdiff -u -r1.137 -r1.138 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Wed Jul 5 02:54:37 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
CPU model 0x5a is not Atom E3500 but Atom Z3500.
To generate a diff of this commit:
cvs rdiff -u -r1.136 -r1.137 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.136 src/usr.sbin/cpuctl/arch/i386.c:1.137
--- src/usr.sbin/cpuctl/arch/i386.c:1.136 Tue Feb 14 15:46:06 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Jul 5 02:54:37 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.136 2023/02/14 15:46:06 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.137 2023/07/05 02:54:37 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.136 2023/02/14 15:46:06 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.137 2023/07/05 02:54:37 msaitoh Exp $");
#endif /* not lint */
#include
@@ -335,7 +335,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
[0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Xeon Phi [357]200 (Knights Landing)",
-[0x5a] = "Atom E3500",
+[0x5a] = "Atom Z3500",
[0x5c] = "Atom (Goldmont)",
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Wed Jul 5 02:54:37 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: CPU model 0x5a is not Atom E3500 but Atom Z3500. To generate a diff of this commit: cvs rdiff -u -r1.136 -r1.137 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: kre Date: Mon Mar 6 01:28:54 UTC 2023 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 cpuctl.c Log Message: Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl() used to implement "cpuctl ucode N", which indicates that the microcode to be loaded already exists in the CPU, and as such, isn't really a very interesting "error". To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/cpuctl.8 cvs rdiff -u -r1.32 -r1.33 src/usr.sbin/cpuctl/cpuctl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src
Committed By: kre
Date: Mon Mar 6 01:28:54 UTC 2023
Modified Files:
src/usr.sbin/cpuctl: cpuctl.8 cpuctl.c
Log Message:
Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()
used to implement "cpuctl ucode N", which indicates that the microcode
to be loaded already exists in the CPU, and as such, isn't really a
very interesting "error".
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/cpuctl.8
cvs rdiff -u -r1.32 -r1.33 src/usr.sbin/cpuctl/cpuctl.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/cpuctl.8
diff -u src/usr.sbin/cpuctl/cpuctl.8:1.20 src/usr.sbin/cpuctl/cpuctl.8:1.21
--- src/usr.sbin/cpuctl/cpuctl.8:1.20 Fri May 17 23:51:35 2019
+++ src/usr.sbin/cpuctl/cpuctl.8 Mon Mar 6 01:28:54 2023
@@ -1,4 +1,4 @@
-.\" $NetBSD: cpuctl.8,v 1.20 2019/05/17 23:51:35 gutteridge Exp $
+.\" $NetBSD: cpuctl.8,v 1.21 2023/03/06 01:28:54 kre Exp $
.\"
.\" Copyright (c) 2007, 2008, 2012, 2015 The NetBSD Foundation, Inc.
.\" All rights reserved.
@@ -72,6 +72,10 @@ Set the specified CPUs on line, making t
.Op Ar file
.Xc
This applies the microcode patch to CPUs.
+Unless
+.Fl v
+was given, errors indicating that the microcode
+already exists on the CPU in question are ignored.
If
.Ar cpu
is not specified or \-1, all CPUs are updated.
Index: src/usr.sbin/cpuctl/cpuctl.c
diff -u src/usr.sbin/cpuctl/cpuctl.c:1.32 src/usr.sbin/cpuctl/cpuctl.c:1.33
--- src/usr.sbin/cpuctl/cpuctl.c:1.32 Tue Feb 1 10:45:02 2022
+++ src/usr.sbin/cpuctl/cpuctl.c Mon Mar 6 01:28:54 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl.c,v 1.32 2022/02/01 10:45:02 mrg Exp $ */
+/* $NetBSD: cpuctl.c,v 1.33 2023/03/06 01:28:54 kre Exp $ */
/*-
* Copyright (c) 2007, 2008, 2009, 2012, 2015 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#ifndef lint
#include
-__RCSID("$NetBSD: cpuctl.c,v 1.32 2022/02/01 10:45:02 mrg Exp $");
+__RCSID("$NetBSD: cpuctl.c,v 1.33 2023/03/06 01:28:54 kre Exp $");
#endif /* not lint */
#include
@@ -247,7 +247,7 @@ cpu_ucode(char **argv)
cpuset_destroy(cpuset);
}
error = ioctl(fd, IOC_CPU_UCODE_APPLY, );
- if (error < 0) {
+ if (error < 0 && (verbose || errno != EEXIST)) {
if (uc.fwname[0])
err(EXIT_FAILURE, "%s", uc.fwname);
else
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: skrll
Date: Fri Feb 3 08:08:33 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
MPIDR is 64bits. Without this AFF3 would always be zero.
Spotted by Cyprien.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.21 src/usr.sbin/cpuctl/arch/aarch64.c:1.22
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.21 Sat Apr 30 14:06:10 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Fri Feb 3 08:08:33 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.21 2022/04/30 14:06:10 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.22 2023/02/03 08:08:33 skrll Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.21 2022/04/30 14:06:10 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.22 2023/02/03 08:08:33 skrll Exp $");
#endif /* no lint */
#include
@@ -1073,7 +1073,7 @@ identify_revidr(const char *cpuname, uin
/* MPIDR_EL1 - Multiprocessor Affinity Register */
static void
-identify_mpidr(const char *cpuname, uint32_t mpidr)
+identify_mpidr(const char *cpuname, uint64_t mpidr)
{
const char *setname = "multiprocessor affinity";
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: skrll Date: Fri Feb 3 08:08:33 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: MPIDR is 64bits. Without this AFF3 would always be zero. Spotted by Cyprien. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Fri Dec 30 13:32:46 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Add Raptor Lake and Sapphire Rapids. To generate a diff of this commit: cvs rdiff -u -r1.134 -r1.135 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Fri Dec 30 13:32:46 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add Raptor Lake and Sapphire Rapids.
To generate a diff of this commit:
cvs rdiff -u -r1.134 -r1.135 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.134 src/usr.sbin/cpuctl/arch/i386.c:1.135
--- src/usr.sbin/cpuctl/arch/i386.c:1.134 Fri Dec 30 12:21:07 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Dec 30 13:32:46 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.134 2022/12/30 12:21:07 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.135 2022/12/30 13:32:46 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.134 2022/12/30 12:21:07 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.135 2022/12/30 13:32:46 msaitoh Exp $");
#endif /* not lint */
#include
@@ -351,7 +351,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x8c] = "11th gen Core (Tiger Lake)",
[0x8d] = "11th gen Core (Tiger Lake)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
-[0x8f] = "future Xeon (Sapphire Rapids)",
+[0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)",
[0x96] = "Atom x6000E (Elkhart Lake)",
[0x97] = "12th gen Core (Alder Lake)",
[0x9a] = "12th gen Core (Alder Lake)",
@@ -361,7 +361,9 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa6] = "10th gen Core (Comet Lake)",
[0xa7] = "11th gen Core (Rocket Lake)",
[0xa8] = "11th gen Core (Rocket Lake)",
-[0xbf] = "12th gen Core (Alder Lake)",
+[0xba] = "13th gen Core (Raptor Lake)",
+[0xb7] = "13th gen Core (Raptor Lake)",
+[0xbf] = "13th gen Core (Raptor Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Fri Dec 30 12:21:07 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
To generate a diff of this commit:
cvs rdiff -u -r1.133 -r1.134 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.133 src/usr.sbin/cpuctl/arch/i386.c:1.134
--- src/usr.sbin/cpuctl/arch/i386.c:1.133 Thu Nov 17 15:21:31 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Dec 30 12:21:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.133 2022/11/17 15:21:31 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.134 2022/12/30 12:21:07 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.133 2022/11/17 15:21:31 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.134 2022/12/30 12:21:07 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2210,13 +2210,25 @@ identifycpu(int fd, const char *cpuname)
if ((ci->ci_max_cpuid >= 7)
&& ((cpu_vendor == CPUVENDOR_INTEL)
|| (cpu_vendor == CPUVENDOR_AMD))) {
+ unsigned int maxsubleaf;
+
x86_cpuid(7, descs);
+ maxsubleaf = descs[0];
aprint_verbose("%s: SEF highest subleaf %08x\n",
- cpuname, descs[0]);
- if (descs[0] >= 1) {
+ cpuname, maxsubleaf);
+ if (maxsubleaf >= 1) {
x86_cpuid2(7, 1, descs);
print_bits(cpuname, "SEF-subleaf1-eax",
CPUID_SEF1_FLAGS_A, descs[0]);
+ print_bits(cpuname, "SEF-subleaf1-ebx",
+ CPUID_SEF1_FLAGS_B, descs[1]);
+ print_bits(cpuname, "SEF-subleaf1-edx",
+ CPUID_SEF1_FLAGS_D, descs[3]);
+ }
+ if (maxsubleaf >= 2) {
+ x86_cpuid2(7, 2, descs);
+ print_bits(cpuname, "SEF-subleaf2-edx",
+ CPUID_SEF2_FLAGS_D, descs[3]);
}
}
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Fri Dec 30 12:21:07 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx. To generate a diff of this commit: cvs rdiff -u -r1.133 -r1.134 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Nov 17 15:21:32 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: s/features 2/features2/ To generate a diff of this commit: cvs rdiff -u -r1.132 -r1.133 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Nov 17 15:21:32 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
s/features 2/features2/
To generate a diff of this commit:
cvs rdiff -u -r1.132 -r1.133 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.132 src/usr.sbin/cpuctl/arch/i386.c:1.133
--- src/usr.sbin/cpuctl/arch/i386.c:1.132 Wed Nov 16 15:02:00 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Nov 17 15:21:31 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.132 2022/11/16 15:02:00 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.133 2022/11/17 15:21:31 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.132 2022/11/16 15:02:00 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.133 2022/11/17 15:21:31 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2234,7 +2234,7 @@ identifycpu(int fd, const char *cpuname)
if (cpu_vendor == CPUVENDOR_AMD) {
if (ci->ci_max_ext_cpuid >= 0x8021) {
x86_cpuid(0x8021, descs);
- print_bits(cpuname, "AMD Extended features 2",
+ print_bits(cpuname, "AMD Extended features2",
CPUID_AMDEXT2_FLAGS, descs[0]);
}
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Wed Nov 16 15:02:00 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
s/Instruction-Based Sampling/IBS/
To generate a diff of this commit:
cvs rdiff -u -r1.131 -r1.132 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.131 src/usr.sbin/cpuctl/arch/i386.c:1.132
--- src/usr.sbin/cpuctl/arch/i386.c:1.131 Wed Nov 16 14:55:50 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Nov 16 15:02:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.131 2022/11/16 14:55:50 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.132 2022/11/16 15:02:00 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.131 2022/11/16 14:55:50 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.132 2022/11/16 15:02:00 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2255,8 +2255,7 @@ identifycpu(int fd, const char *cpuname)
}
if (ci->ci_max_ext_cpuid >= 0x801b) {
x86_cpuid(0x801b, descs);
- print_bits(cpuname,
- "Instruction-Based Sampling features",
+ print_bits(cpuname, "IBS features",
CPUID_IBS_FLAGS, descs[0]);
}
if (ci->ci_max_ext_cpuid >= 0x801f) {
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Wed Nov 16 15:02:00 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: s/Instruction-Based Sampling/IBS/ To generate a diff of this commit: cvs rdiff -u -r1.131 -r1.132 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Wed Nov 16 13:15:26 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Print AMD RAS features and Instruction-Based Sampling features.
To generate a diff of this commit:
cvs rdiff -u -r1.128 -r1.129 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.128 src/usr.sbin/cpuctl/arch/i386.c:1.129
--- src/usr.sbin/cpuctl/arch/i386.c:1.128 Wed Jun 15 16:28:01 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Nov 16 13:15:26 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.128 2022/06/15 16:28:01 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.129 2022/11/16 13:15:26 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.128 2022/06/15 16:28:01 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.129 2022/11/16 13:15:26 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2232,6 +2232,11 @@ identifycpu(int fd, const char *cpuname)
}
if (cpu_vendor == CPUVENDOR_AMD) {
+ if (ci->ci_max_ext_cpuid >= 0x8007) {
+ x86_cpuid(0x8007, descs);
+ print_bits(cpuname, "RAS features",
+ CPUID_RAS_FLAGS, descs[1]);
+ }
if ((ci->ci_max_ext_cpuid >= 0x800a)
&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x800a, descs);
@@ -2242,6 +2247,12 @@ identifycpu(int fd, const char *cpuname)
print_bits(cpuname, "SVM features",
CPUID_AMD_SVM_FLAGS, descs[3]);
}
+ if (ci->ci_max_ext_cpuid >= 0x801b) {
+ x86_cpuid(0x801b, descs);
+ print_bits(cpuname,
+ "Instruction-Based Sampling features",
+ CPUID_IBS_FLAGS, descs[0]);
+ }
if (ci->ci_max_ext_cpuid >= 0x801f) {
x86_cpuid(0x801f, descs);
print_bits(cpuname, "Encrypted Memory features",
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Wed Nov 16 13:15:26 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Print AMD RAS features and Instruction-Based Sampling features. To generate a diff of this commit: cvs rdiff -u -r1.128 -r1.129 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Wed Jun 15 16:28:01 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Modify output of CPUID Fn000a.
old:
cpu0: Perfmon-eax 0x8300805
cpu0: Perfmon-eax 0x8300805
cpu0: Perfmon-edx 0x8604
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff
cpu0: Perfmon: General: avail 0xff
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf
To generate a diff of this commit:
cvs rdiff -u -r1.127 -r1.128 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.127 src/usr.sbin/cpuctl/arch/i386.c:1.128
--- src/usr.sbin/cpuctl/arch/i386.c:1.127 Sat Jan 29 08:20:45 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Jun 15 16:28:01 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.127 2022/01/29 08:20:45 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.128 2022/06/15 16:28:01 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.127 2022/01/29 08:20:45 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.128 2022/06/15 16:28:01 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2249,13 +2249,48 @@ identifycpu(int fd, const char *cpuname)
}
} else if (cpu_vendor == CPUVENDOR_INTEL) {
if (ci->ci_max_cpuid >= 0x0a) {
+ unsigned int pmcver, ncounter, veclen;
+
x86_cpuid(0x0a, descs);
- print_bits(cpuname, "Perfmon-eax",
- CPUID_PERF_FLAGS0, descs[0]);
- print_bits(cpuname, "Perfmon-ebx",
+ pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION);
+ ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC);
+ veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN);
+ aprint_verbose("%s: Perfmon: Ver. %u",
+ cpuname, pmcver);
+ if (((pmcver >= 3) && (pmcver <= 4)) ||
+ ((pmcver >= 5) &&
+(descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0))
+aprint_verbose(" \n");
+ else
+aprint_verbose("\n");
+
+ aprint_verbose("%s: Perfmon: General: "
+ "bitwidth %u, %u counters\n", cpuname,
+ (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC),
+ ncounter);
+ /* Invert logic for the output */
+ descs[1] ^= __BITS(veclen - 1, 0);
+ /*
+ * Mask unrelated bits. An hypervisor reduces the
+ * vector and set bit(s) out of the vector.
+ */
+ descs[1] &= __BITS(veclen - 1, 0);
+ print_bits(cpuname, "Perfmon: General: avail",
CPUID_PERF_FLAGS1, descs[1]);
- print_bits(cpuname, "Perfmon-edx",
- CPUID_PERF_FLAGS3, descs[3]);
+
+ if (pmcver >= 2) {
+ncounter = __SHIFTOUT(descs[3],
+CPUID_PERF_NFFPC);
+aprint_verbose("%s: Perfmon: Fixed: "
+"bitwidth %u, %u counters\n", cpuname,
+(uint32_t)__SHIFTOUT(descs[3],
+ CPUID_PERF_NBWFFPC),
+ncounter);
+if (pmcver <= 4)
+ descs[2] = __BITS(ncounter - 1, 0);
+print_bits(cpuname, "Perfmon: Fixed: avail",
+CPUID_PERF_FLAGS2, descs[2]);
+ }
}
if (ci->ci_max_cpuid >= 0x1a) {
x86_cpuid(0x1a, descs);
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Wed Jun 15 16:28:01 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Modify output of CPUID Fn000a. old: cpu0: Perfmon-eax 0x8300805 cpu0: Perfmon-eax 0x8300805 cpu0: Perfmon-edx 0x8604 new: cpu0: Perfmon: Ver. 5 cpu0: Perfmon: General: bitwidth 48, 8 counters cpu0: Perfmon: General: avail 0xff cpu0: Perfmon: General: avail 0xff cpu0: Perfmon: Fixed: bitwidth 48, 4 counters cpu0: Perfmon: Fixed: avail 0xf To generate a diff of this commit: cvs rdiff -u -r1.127 -r1.128 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: ryo
Date: Sat Apr 30 14:06:10 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM.
sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.20 src/usr.sbin/cpuctl/arch/aarch64.c:1.21
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.20 Thu Jan 6 18:00:58 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Sat Apr 30 14:06:10 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.20 2022/01/06 18:00:58 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.21 2022/04/30 14:06:10 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.20 2022/01/06 18:00:58 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.21 2022/04/30 14:06:10 ryo Exp $");
#endif /* no lint */
#include
@@ -91,6 +91,8 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_THUNDERX81XXRX, "ThunderX CN81XX", "Cavium", "v8-A" },
{ CPU_ID_THUNDERX83XXRX, "ThunderX CN83XX", "Cavium", "v8-A" },
{ CPU_ID_THUNDERX2RX, "ThunderX2", "Marvell", "v8.1-A" },
+ { CPU_ID_APPLE_M1_ICESTORM & CPU_PARTMASK, "M1 Icestorm", "Apple", "Apple Silicon" },
+ { CPU_ID_APPLE_M1_FIRESTORM & CPU_PARTMASK, "M1 Firestorm", "Apple", "Apple Silicon" },
};
const struct impltab implids[] = {
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: ryo Date: Sat Apr 30 14:06:10 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM. sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69 To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src
Committed By: mrg
Date: Tue Feb 1 10:45:02 UTC 2022
Modified Files:
src/usr.sbin/cpuctl: cpuctl.c
Log Message:
allow "cpuN" as well as "N" to specific a CPU.
update usage to include a change i made from 2015 to allow multiple
CPUs to be operated on at the same time for most commands.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/usr.sbin/cpuctl/cpuctl.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/cpuctl.c
diff -u src/usr.sbin/cpuctl/cpuctl.c:1.31 src/usr.sbin/cpuctl/cpuctl.c:1.32
--- src/usr.sbin/cpuctl/cpuctl.c:1.31 Tue Apr 21 02:56:37 2020
+++ src/usr.sbin/cpuctl/cpuctl.c Tue Feb 1 10:45:02 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl.c,v 1.31 2020/04/21 02:56:37 msaitoh Exp $ */
+/* $NetBSD: cpuctl.c,v 1.32 2022/02/01 10:45:02 mrg Exp $ */
/*-
* Copyright (c) 2007, 2008, 2009, 2012, 2015 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#ifndef lint
#include
-__RCSID("$NetBSD: cpuctl.c,v 1.31 2020/04/21 02:56:37 msaitoh Exp $");
+__RCSID("$NetBSD: cpuctl.c,v 1.32 2022/02/01 10:45:02 mrg Exp $");
#endif /* not lint */
#include
@@ -132,12 +132,12 @@ usage(void)
{
const char *progname = getprogname();
- fprintf(stderr, "usage: %s identify cpuno\n", progname);
+ fprintf(stderr, "usage: %s identify cpuno [cpuno ..]\n", progname);
fprintf(stderr, " %s list\n", progname);
- fprintf(stderr, " %s offline cpuno\n", progname);
- fprintf(stderr, " %s online cpuno\n", progname);
- fprintf(stderr, " %s intr cpuno\n", progname);
- fprintf(stderr, " %s nointr cpuno\n", progname);
+ fprintf(stderr, " %s offline cpuno [cpuno ..]\n", progname);
+ fprintf(stderr, " %s online cpuno [cpuno ..]\n", progname);
+ fprintf(stderr, " %s intr cpuno [cpuno ..]\n", progname);
+ fprintf(stderr, " %s nointr cpuno [cpuno ..]\n", progname);
fprintf(stderr, " %s ucode [cpuno] [file]\n", progname);
exit(EXIT_FAILURE);
/* NOTREACHED */
@@ -296,6 +296,9 @@ getcpuid(char *arg)
u_int id;
long np;
+ if (strncmp(arg, "cpu", 3) == 0)
+ arg += 3;
+
id = (u_int)strtoul(arg, , 0);
if (*argp != '\0')
usage();
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: mrg Date: Tue Feb 1 10:45:02 UTC 2022 Modified Files: src/usr.sbin/cpuctl: cpuctl.c Log Message: allow "cpuN" as well as "N" to specific a CPU. update usage to include a change i made from 2015 to allow multiple CPUs to be operated on at the same time for most commands. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/usr.sbin/cpuctl/cpuctl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Sat Jan 29 08:20:45 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Decode Intel Hybrid Information Enumeration (CPUID Fn_001a).
To generate a diff of this commit:
cvs rdiff -u -r1.126 -r1.127 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.126 src/usr.sbin/cpuctl/arch/i386.c:1.127
--- src/usr.sbin/cpuctl/arch/i386.c:1.126 Thu Jan 27 09:53:43 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Sat Jan 29 08:20:45 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.126 2022/01/27 09:53:43 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.127 2022/01/29 08:20:45 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.126 2022/01/27 09:53:43 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.127 2022/01/29 08:20:45 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2257,6 +2257,18 @@ identifycpu(int fd, const char *cpuname)
print_bits(cpuname, "Perfmon-edx",
CPUID_PERF_FLAGS3, descs[3]);
}
+ if (ci->ci_max_cpuid >= 0x1a) {
+ x86_cpuid(0x1a, descs);
+ if (descs[0] != 0) {
+aprint_verbose("%s: Hybrid: Core type %02x, "
+"Native Model ID %07x\n",
+cpuname,
+(uint8_t)__SHIFTOUT(descs[0],
+ CPUID_HYBRID_CORETYPE),
+(uint32_t)__SHIFTOUT(descs[0],
+ CPUID_HYBRID_NATIVEID));
+ }
+ }
}
#ifdef INTEL_ONDEMAND_CLOCKMOD
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Sat Jan 29 08:20:45 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Decode Intel Hybrid Information Enumeration (CPUID Fn_001a). To generate a diff of this commit: cvs rdiff -u -r1.126 -r1.127 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Jan 27 09:53:43 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Remove debug code and simplify. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.125 -r1.126 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.125 src/usr.sbin/cpuctl/arch/i386.c:1.126
--- src/usr.sbin/cpuctl/arch/i386.c:1.125 Thu Jan 13 16:02:44 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Jan 27 09:53:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.125 2022/01/13 16:02:44 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.126 2022/01/27 09:53:43 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.125 2022/01/13 16:02:44 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.126 2022/01/27 09:53:43 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2248,32 +2248,14 @@ identifycpu(int fd, const char *cpuname)
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
}
} else if (cpu_vendor == CPUVENDOR_INTEL) {
- int32_t bi_index;
-
- for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) {
- x86_cpuid(bi_index, descs);
- switch (bi_index) {
- case 0x0a:
-print_bits(cpuname, "Perfmon-eax",
-CPUID_PERF_FLAGS0, descs[0]);
-print_bits(cpuname, "Perfmon-ebx",
-CPUID_PERF_FLAGS1, descs[1]);
-print_bits(cpuname, "Perfmon-edx",
-CPUID_PERF_FLAGS3, descs[3]);
-break;
- default:
-#if 0
-aprint_verbose("%s: basic %08x-eax %08x\n",
-cpuname, bi_index, descs[0]);
-aprint_verbose("%s: basic %08x-ebx %08x\n",
-cpuname, bi_index, descs[1]);
-aprint_verbose("%s: basic %08x-ecx %08x\n",
-cpuname, bi_index, descs[2]);
-aprint_verbose("%s: basic %08x-edx %08x\n",
-cpuname, bi_index, descs[3]);
-#endif
-break;
- }
+ if (ci->ci_max_cpuid >= 0x0a) {
+ x86_cpuid(0x0a, descs);
+ print_bits(cpuname, "Perfmon-eax",
+ CPUID_PERF_FLAGS0, descs[0]);
+ print_bits(cpuname, "Perfmon-ebx",
+ CPUID_PERF_FLAGS1, descs[1]);
+ print_bits(cpuname, "Perfmon-edx",
+ CPUID_PERF_FLAGS3, descs[3]);
}
}
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Jan 27 09:53:43 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Remove debug code and simplify. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.125 -r1.126 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Jan 13 16:02:44 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
To generate a diff of this commit:
cvs rdiff -u -r1.124 -r1.125 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.124 src/usr.sbin/cpuctl/arch/i386.c:1.125
--- src/usr.sbin/cpuctl/arch/i386.c:1.124 Thu Dec 9 14:23:06 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Jan 13 16:02:44 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.124 2021/12/09 14:23:06 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.125 2022/01/13 16:02:44 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.124 2021/12/09 14:23:06 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.125 2022/01/13 16:02:44 msaitoh Exp $");
#endif /* not lint */
#include
@@ -351,11 +351,17 @@ const struct cpu_cpuid_nameclass i386_cp
[0x8c] = "11th gen Core (Tiger Lake)",
[0x8d] = "11th gen Core (Tiger Lake)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x8f] = "future Xeon (Sapphire Rapids)",
[0x96] = "Atom x6000E (Elkhart Lake)",
+[0x97] = "12th gen Core (Alder Lake)",
+[0x9a] = "12th gen Core (Alder Lake)",
[0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)",
[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
[0xa5] = "10th gen Core (Comet Lake)",
[0xa6] = "10th gen Core (Comet Lake)",
+[0xa7] = "11th gen Core (Rocket Lake)",
+[0xa8] = "11th gen Core (Rocket Lake)",
+[0xbf] = "12th gen Core (Alder Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Jan 13 16:02:44 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM. To generate a diff of this commit: cvs rdiff -u -r1.124 -r1.125 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: ryo Date: Thu Jan 6 18:00:58 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: display the raw value of each field when -v specified To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: ryo
Date: Thu Jan 6 18:00:58 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
display the raw value of each field when -v specified
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.19 src/usr.sbin/cpuctl/arch/aarch64.c:1.20
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.19 Thu Jan 6 17:59:15 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 6 18:00:58 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.19 2022/01/06 17:59:15 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.20 2022/01/06 18:00:58 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.19 2022/01/06 17:59:15 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.20 2022/01/06 18:00:58 ryo Exp $");
#endif /* no lint */
#include
@@ -1008,6 +1008,9 @@ print_fieldinfo(const char *cpuname, con
printf("%s: %s: %s: ",
cpuname, setname, fieldinfo[i].name);
+ if (verbose)
+ printf("0x%"PRIx64": ", v);
+
if (info == NULL) {
if (flags & FIELDINFO_FLAGS_4LOG2)
v = 4 * (1 << v);
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: ryo
Date: Thu Jan 6 17:59:15 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
fix typo
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.18 src/usr.sbin/cpuctl/arch/aarch64.c:1.19
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.18 Thu Jan 6 09:01:16 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 6 17:59:15 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.18 2022/01/06 09:01:16 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.19 2022/01/06 17:59:15 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.18 2022/01/06 09:01:16 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.19 2022/01/06 17:59:15 ryo Exp $");
#endif /* no lint */
#include
@@ -384,7 +384,7 @@ struct fieldinfo id_aa64isar1_fieldinfo[
},
{
FIELDINFO(4, 4, "APA") {
- [0] = "No Archtected Address Authentication algorithm",
+ [0] = "No Architected Address Authentication algorithm",
[1] = "QARMA with PAC",
[2] = "QARMA with EnhancedPAC",
[3] = "QARMA with EnhancedPAC2",
@@ -423,7 +423,7 @@ struct fieldinfo id_aa64isar1_fieldinfo[
},
{
FIELDINFO(24, 4, "GPA") {
- [0] = "No Archtected Generic Authentication algorithm",
+ [0] = "No Architected Generic Authentication algorithm",
[1] = "QARMA with PACGA"
}
},
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: ryo Date: Thu Jan 6 17:59:15 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: fix typo To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: ryo
Date: Thu Jan 6 09:01:16 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
Added more field definitions for ARMv8.x system registers
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.17 src/usr.sbin/cpuctl/arch/aarch64.c:1.18
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.17 Thu Jan 6 08:46:43 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 6 09:01:16 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.18 2022/01/06 09:01:16 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.18 2022/01/06 09:01:16 ryo Exp $");
#endif /* no lint */
#include
@@ -244,15 +244,31 @@ struct fieldinfo id_aa64pfr1_fieldinfo[]
},
{
FIELDINFO(8, 4, "MTE") {
- [0] = "Tagged Memory Extension not implemented",
- [1] = "Tagged Memory Extension implemented, EL0 only",
- [2] = "Tagged Memory Extension implemented"
+ [0] = "Memory Tagging Extension not implemented",
+ [1] = "Instruction-only Memory Taggined Extension"
+ " implemented",
+ [2] = "Full Memory Tagging Extension implemented",
+ [3] = "Memory Tagging Extension implemented"
+ " with Tag Check Fault handling"
}
},
{
FIELDINFO(12, 4, "RAS_frac") {
[0] = "Regular RAS",
- [1] = "RAS plus registers",
+ [1] = "RAS plus registers"
+ }
+ },
+ {
+ FIELDINFO(16, 4, "MPAM_frac") {
+ [0] = "MPAM not implemented, or v1.0",
+ [1] = "MPAM v0.1 or v1.1"
+ }
+ },
+ {
+ FIELDINFO(32, 4, "CSV2_frac") {
+ [0] = "not disclosed",
+ [1] = "SCXTNUM_ELx registers not supported",
+ [2] = "SCXTNUM_ELx registers supported"
}
},
{ .bitwidth = 0 } /* end of table */
@@ -276,7 +292,9 @@ struct fieldinfo id_aa64isar0_fieldinfo[
{
FIELDINFO(12, 4, "SHA2") {
[0] = "No SHA2",
- [1] = "SHA256H/SHA256H2/SHA256SU0/SHA256U1"
+ [1] = "SHA256H/SHA256H2/SHA256SU0/SHA256SU1",
+ [2] = "SHA256H/SHA256H2/SHA256SU0/SHA256SU1"
+ "/SHA512H/SHA512H2/SHA512SU0/SHA512SU1"
}
},
{
@@ -355,6 +373,121 @@ struct fieldinfo id_aa64isar0_fieldinfo[
{ .bitwidth = 0 } /* end of table */
};
+/* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
+struct fieldinfo id_aa64isar1_fieldinfo[] = {
+ {
+ FIELDINFO(0, 4, "DPB") {
+ [0] = "No DC CVAP",
+ [1] = "DC CVAP",
+ [2] = "DC CVAP/DC CVADP"
+ }
+ },
+ {
+ FIELDINFO(4, 4, "APA") {
+ [0] = "No Archtected Address Authentication algorithm",
+ [1] = "QARMA with PAC",
+ [2] = "QARMA with EnhancedPAC",
+ [3] = "QARMA with EnhancedPAC2",
+ [4] = "QARMA with EnhancedPAC/PAC2",
+ [5] = "QARMA with EnhancedPAC/PAC2/FPACCombined"
+ }
+ },
+ {
+ FIELDINFO(8, 4, "API") {
+ [0] = "No Address Authentication algorithm",
+ [1] = "Address Authentication algorithm implemented",
+ [2] = "EnhancedPAC",
+ [3] = "EnhancedPAC2",
+ [4] = "EnhancedPAC2/FPAC",
+ [5] = "EnhancedPAC2/FPAC/FPACCombined"
+ }
+ },
+ {
+ FIELDINFO(12, 4, "JSCVT") {
+ [0] = "No FJCVTZS",
+ [1] = "FJCVTZS"
+ }
+ },
+ {
+ FIELDINFO(16, 4, "FCMA") {
+ [0] = "No FCMA",
+ [1] = "FCMLA/FCADD"
+ }
+ },
+ {
+ FIELDINFO(20, 4, "LRCPC") {
+ [0] = "no LRCPC",
+ [1] = "LDAPR",
+ [2] = "LDAPR/LDAPUR/STLUR"
+ }
+ },
+ {
+ FIELDINFO(24, 4, "GPA") {
+ [0] = "No Archtected Generic Authentication algorithm",
+ [1] = "QARMA with PACGA"
+ }
+ },
+ {
+ FIELDINFO(28, 4, "GPI") {
+ [0] = "No Generic Authentication algorithm",
+ [1] = "Generic Authentication algorithm implemented"
+ }
+ },
+ {
+ FIELDINFO(32, 4, "FRINTTS") {
+ [0] = "No FRINTTS",
+ [1] = "FRINT32Z/FRINT32X/FRINT64Z/FRINT64X"
+ }
+ },
+ {
+ FIELDINFO(36, 4, "SB") {
+ [0] = "No SB",
+ [1] = "SB"
+ }
+ },
+ {
+ FIELDINFO(40, 4, "SPECRES") {
+ [0] = "No SPECRES",
+ [1] = "CFP RCTX/DVP RCTX/CPP RCTX"
+ }
+ },
+ {
+ FIELDINFO(44, 4, "BF16") {
+ [0] = "No BFloat16",
+ [1] = "BFCVT/BFCVTN/BFCVTN2/BFDOT"
+ "/BFMLALB/BFMLALT/BFMMLA"
+ }
+ },
+ {
+ FIELDINFO(48, 4, "DGH") {
+ [0] = "Data Gathering Hint not implemented",
+ [1] = "Data Gathering Hint implemented"
+ }
+ },
+ {
+ FIELDINFO(52, 4, "I8MM") {
+ [0] = "No Int8 matrix",
+ [1] = "SMMLA/SUDOT/UMMLA/USMMLA/USDOT"
+ }
+ },
+ {
+ FIELDINFO(56, 4, "XS") {
+ [0] = "No XS/nXS qualifier",
+ [1] = "XS attribute, TLBI and DSB"
+ " with nXS qualifier supported"
+ }
+ },
+ {
+ FIELDINFO(60, 4, "LS64") {
+ [0] = "No LS64",
+ [1] = "LD64B/ST64B",
+ [2] = "LD64B/ST64B/ST64BV",
+ [3] = "LD64B/ST64B/ST64BV/ST64BV0/ACCDATA_EL1",
+ }
+ },
+ { .bitwidth = 0 } /* end of
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: ryo Date: Thu Jan 6 09:01:16 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: Added more field definitions for ARMv8.x system registers To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: ryo
Date: Thu Jan 6 08:46:43 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch: aarch64.c
Log Message:
macroify. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/usr.sbin/cpuctl/arch/aarch64.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/aarch64.c
diff -u src/usr.sbin/cpuctl/arch/aarch64.c:1.16 src/usr.sbin/cpuctl/arch/aarch64.c:1.17
--- src/usr.sbin/cpuctl/arch/aarch64.c:1.16 Wed Jan 5 19:53:32 2022
+++ src/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 6 08:46:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.16 2022/01/05 19:53:32 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.16 2022/01/05 19:53:32 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $");
#endif /* no lint */
#include
@@ -111,119 +111,114 @@ const struct impltab implids[] = {
{ CPU_ID_INTEL, "Intel Corporation" }
};
+#define FIELDNAME(_bitpos, _bitwidth, _name) \
+ .bitpos = _bitpos, \
+ .bitwidth = _bitwidth, \
+ .name = _name
+
+#define FIELDINFO(_bitpos, _bitwidth, _name) \
+ FIELDNAME(_bitpos, _bitwidth, _name), \
+ .info = (const char *[1 << _bitwidth])
+
+
/* ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 */
struct fieldinfo id_aa64pfr0_fieldinfo[] = {
{
- .bitpos = 0, .bitwidth = 4, .name = "EL0",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(0, 4, "EL0") {
[0] = "No EL0",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 4, .bitwidth = 4, .name = "EL1",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(4, 4, "EL1") {
[0] = "No EL1",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 8, .bitwidth = 4, .name = "EL2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(8, 4, "EL2") {
[0] = "No EL2",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 12, .bitwidth = 4, .name = "EL3",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(12, 4, "EL3") {
[0] = "No EL3",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 16, .bitwidth = 4, .name = "FP",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(16, 4, "FP") {
[0] = "Floating Point",
[1] = "Floating Point including half-precision support",
[15] = "No Floating Point"
}
},
{
- .bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(20, 4, "AdvSIMD") {
[0] = "Advanced SIMD",
[1] = "Advanced SIMD including half-precision support",
[15] = "No Advanced SIMD"
}
},
{
- .bitpos = 24, .bitwidth = 4, .name = "GIC",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(24, 4, "GIC") {
[0] = "GIC CPU interface sysregs not implemented",
[1] = "GIC CPU interface sysregs v3.0/4.0 supported",
[3] = "GIC CPU interface sysregs v4.1 supported"
}
},
{
- .bitpos = 28, .bitwidth = 4, .name = "RAS",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(28, 4, "RAS") {
[0] = "Reliability/Availability/Serviceability not supported",
[1] = "Reliability/Availability/Serviceability supported",
[2] = "Reliability/Availability/Serviceability ARMv8.4 supported",
},
},
{
- .bitpos = 32, .bitwidth = 4, .name = "SVE",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(32, 4, "SVE") {
[0] = "Scalable Vector Extensions not implemented",
[1] = "Scalable Vector Extensions implemented",
},
},
{
- .bitpos = 36, .bitwidth = 4, .name = "SEL2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(36, 4, "SEL2") {
[0] = "Secure EL2 not implemented",
[1] = "Secure EL2 implemented",
},
},
{
- .bitpos = 40, .bitwidth = 4, .name = "MPAM",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(40, 4, "MPAM") {
[0] = "Memory Partitioning and Monitoring not implemented",
[1] = "Memory Partitioning and Monitoring implemented",
},
},
{
- .bitpos = 44, .bitwidth = 4, .name = "AMU",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(44, 4, "AMU") {
[0] = "Activity Monitors Extension not implemented",
[1] = "Activity Monitors Extension v1 ARMv8.4",
[2] = "Activity Monitors Extension v1 ARMv8.6",
},
},
{
- .bitpos = 48, .bitwidth = 4, .name = "DIT",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(48, 4, "DIT") {
[0] = "No Data-Independent Timing guarantees",
[1] = "Data-Independent Timing guaranteed by PSTATE.DIT",
},
},
{
- .bitpos = 56, .bitwidth = 4, .name = "CSV2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(56, 4, "CSV2") {
[0] = "Branch prediction might be Spectred",
[1] = "Branch prediction maybe not
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: ryo Date: Thu Jan 6 08:46:43 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch: aarch64.c Log Message: macroify. NFC. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/usr.sbin/cpuctl/arch/aarch64.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Thu Dec 9 14:23:06 UTC 2021
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Print 1GB TLB entry at the same leve's line.
Example:
before:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries
cpu0: L1 1GB page DTLB: 4 1GB entries 4-way
after:
cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 4K/2M: 1024 entries
To generate a diff of this commit:
cvs rdiff -u -r1.123 -r1.124 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.123 src/usr.sbin/cpuctl/arch/i386.c:1.124
--- src/usr.sbin/cpuctl/arch/i386.c:1.123 Wed Oct 27 04:15:42 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Thu Dec 9 14:23:06 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.123 2021/10/27 04:15:42 mrg Exp $ */
+/* $NetBSD: i386.c,v 1.124 2021/12/09 14:23:06 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.123 2021/10/27 04:15:42 mrg Exp $");
+__RCSID("$NetBSD: i386.c,v 1.124 2021/12/09 14:23:06 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2420,11 +2420,13 @@ x86_print_cache_and_tlb_info(struct cpu_
sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL);
sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep);
+ sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep);
if (sep != NULL)
aprint_verbose("\n");
sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL);
sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep);
+ sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep);
if (sep != NULL)
aprint_verbose("\n");
@@ -2438,11 +2440,13 @@ x86_print_cache_and_tlb_info(struct cpu_
sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep);
if (sep != NULL)
aprint_verbose("\n");
sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep);
if (sep != NULL)
aprint_verbose("\n");
@@ -2451,22 +2455,6 @@ x86_print_cache_and_tlb_info(struct cpu_
sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep);
if (sep != NULL)
aprint_verbose("\n");
-
- sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:", NULL);
- if (sep != NULL)
- aprint_verbose("\n");
-
- sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:", NULL);
- if (sep != NULL)
- aprint_verbose("\n");
-
- sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:", NULL);
- if (sep != NULL)
- aprint_verbose("\n");
-
- sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:", NULL);
- if (sep != NULL)
- aprint_verbose("\n");
}
static void
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Thu Dec 9 14:23:06 UTC 2021 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Print 1GB TLB entry at the same leve's line. Example: before: cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries cpu0: DTLB: 64 4KB entries 4-way cpu0: L2 STLB: 4K/2M: 1024 entries cpu0: L1 1GB page DTLB: 4 1GB entries 4-way after: cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way cpu0: L2 STLB: 4K/2M: 1024 entries To generate a diff of this commit: cvs rdiff -u -r1.123 -r1.124 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Sun Dec 5 04:25:33 UTC 2021
Modified Files:
src/usr.sbin/cpuctl/arch: arm.c
Log Message:
auxilary -> auxiliary
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/arm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/arm.c
diff -u src/usr.sbin/cpuctl/arch/arm.c:1.4 src/usr.sbin/cpuctl/arch/arm.c:1.5
--- src/usr.sbin/cpuctl/arch/arm.c:1.4 Sat Jan 16 15:35:28 2021
+++ src/usr.sbin/cpuctl/arch/arm.c Sun Dec 5 04:25:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: arm.c,v 1.4 2021/01/16 15:35:28 jmcneill Exp $ */
+/* $NetBSD: arm.c,v 1.5 2021/12/05 04:25:33 msaitoh Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: arm.c,v 1.4 2021/01/16 15:35:28 jmcneill Exp $");
+__RCSID("$NetBSD: arm.c,v 1.5 2021/12/05 04:25:33 msaitoh Exp $");
#endif /* not lint */
#include
@@ -77,7 +77,7 @@ static const char * const id_mmfr_fieldn
"Outermost-Shareablity",
"Shareability-Levels",
"TCM-Support",
- "Auxilary-Registers",
+ "Auxiliary-Registers",
"FCSE-Support",
"Innermost-Shareability"
}, {
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Sun Dec 5 04:25:33 UTC 2021 Modified Files: src/usr.sbin/cpuctl/arch: arm.c Log Message: auxilary -> auxiliary To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/cpuctl/arch/arm.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Mon Sep 27 17:05:58 UTC 2021
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Improve variable sized TLB's output.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
XXX This is temporary solution.
To generate a diff of this commit:
cvs rdiff -u -r1.120 -r1.121 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.120 src/usr.sbin/cpuctl/arch/i386.c:1.121
--- src/usr.sbin/cpuctl/arch/i386.c:1.120 Mon Sep 27 16:52:15 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Sep 27 17:05:58 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.120 2021/09/27 16:52:15 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.121 2021/09/27 17:05:58 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.120 2021/09/27 16:52:15 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.121 2021/09/27 17:05:58 msaitoh Exp $");
#endif /* not lint */
#include
@@ -1145,24 +1145,35 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
else if (type == CPUID_DATP_TCTYPE_D)
caitype = CAI_L2_DTLB;
else if (type == CPUID_DATP_TCTYPE_U) {
-switch (pgsize) {
-case CPUID_DATP_PGSIZE_4KB:
+if (pgsize == CPUID_DATP_PGSIZE_4KB)
caitype = CAI_L2_STLB;
- break;
-case CPUID_DATP_PGSIZE_4KB
-| CPUID_DATP_PGSIZE_2MB:
+else if (pgsize == (CPUID_DATP_PGSIZE_4KB
+ | CPUID_DATP_PGSIZE_2MB))
caitype = CAI_L2_STLB2;
- break;
-case CPUID_DATP_PGSIZE_2MB
-| CPUID_DATP_PGSIZE_4MB:
+else if (pgsize == (CPUID_DATP_PGSIZE_2MB
+ | CPUID_DATP_PGSIZE_4MB))
caitype = CAI_L2_STLB3;
- break;
-default:
- aprint_error_dev(ci->ci_dev,
- "error: unknown L2 STLB size (%d)\n",
+else if ((pgsize & CPUID_DATP_PGSIZE_1GB)
+!= 0) {
+ /* FIXME: 1GB max TLB */
+ caitype = CAI_L2_STLB3;
+ linesize = 1024 * 1024 * 1024;
+} else if ((pgsize & CPUID_DATP_PGSIZE_4MB)
+!= 0) {
+ /* FIXME: 4MB max TLB */
+ caitype = CAI_L2_STLB3;
+ linesize = 4 * 1024 * 1024;
+} else if ((pgsize & CPUID_DATP_PGSIZE_2MB)
+!= 0) {
+ /* FIXME: 2MB max TLB */
+ caitype = CAI_L2_STLB2;
+ linesize = 2 * 1024 * 1024;
+} else {
+ aprint_error_dev(ci->ci_dev, "error: "
+ "unknown L2 STLB size (%d)\n",
pgsize);
- caitype = CAI_DTLB;
- break;
+ caitype = CAI_L2_STLB;
+ linesize = 4 * 1024;
}
} else
caitype = -1;
@@ -1194,15 +1205,19 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
case CPUID_DATP_PGSIZE_1GB:
linesize = 1024 * 1024 * 1024;
break;
- case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB:
- aprint_error_dev(ci->ci_dev,
- "WARINING: Currently 2M/4M info can't print correctly\n");
- linesize = 4 * 1024 * 1024;
- break;
default:
- aprint_error_dev(ci->ci_dev,
- "error: Unknown size combination\n");
- linesize = 4 * 1024;
+ if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0)
+linesize = 1024 * 1024 * 1024; /* MAX 1G */
+ else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0)
+linesize = 4 * 1024 * 1024; /* MAX 4M */
+ else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0)
+linesize = 2 * 1024 * 1024; /* MAX 2M */
+ else
+linesize = 4 * 1024; /* XXX default to 4K */
+ aprint_error_dev(ci->ci_dev, "WARNING: Currently "
+ "this info can't print correctly "
+ "(level = %d, pgsize = %d)\n",
+ level, pgsize);
break;
}
ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Mon Sep 27 17:05:58 UTC 2021 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Improve variable sized TLB's output. - Fix a bug that STLB is printed as DTLB. - If a TLB is variable sized, print the max size instead of error message. XXX This is temporary solution. To generate a diff of this commit: cvs rdiff -u -r1.120 -r1.121 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Mon Sep 27 16:47:15 UTC 2021
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Fix a bug that some TLB related lines were not printed.
To generate a diff of this commit:
cvs rdiff -u -r1.118 -r1.119 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.118 src/usr.sbin/cpuctl/arch/i386.c:1.119
--- src/usr.sbin/cpuctl/arch/i386.c:1.118 Mon Sep 27 16:22:58 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Sep 27 16:47:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.118 2021/09/27 16:22:58 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.118 2021/09/27 16:22:58 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2421,7 +2421,7 @@ print_tlb_config(struct cpu_info *ci, in
aprint_verbose_dev(ci->ci_dev, "");
else
aprint_verbose("%s", sep);
- if (name != NULL)
+ if ((name != NULL) && (sep == NULL))
aprint_verbose("%s ", name);
if (cai->cai_string != NULL) {
@@ -2477,61 +2477,48 @@ x86_print_cache_and_tlb_info(struct cpu_
if (sep != NULL)
aprint_verbose("\n");
}
- if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL);
- sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL);
- sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
- sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL);
- sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL);
- sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
- sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
- if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:",
- NULL);
- if (sep != NULL)
- aprint_verbose("\n");
- }
+
+ sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL);
+ sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL);
+ sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL);
+ sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep);
+ sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
+
+ sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:", NULL);
+ if (sep != NULL)
+ aprint_verbose("\n");
}
static void
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Mon Sep 27 16:47:15 UTC 2021 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Fix a bug that some TLB related lines were not printed. To generate a diff of this commit: cvs rdiff -u -r1.118 -r1.119 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Mon Sep 27 16:22:58 UTC 2021 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Add ':' for readability. To generate a diff of this commit: cvs rdiff -u -r1.117 -r1.118 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Mon Sep 27 16:22:58 UTC 2021
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add ':' for readability.
To generate a diff of this commit:
cvs rdiff -u -r1.117 -r1.118 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.117 src/usr.sbin/cpuctl/arch/i386.c:1.118
--- src/usr.sbin/cpuctl/arch/i386.c:1.117 Mon Jul 12 12:56:52 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Sep 27 16:22:58 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.117 2021/07/12 12:56:52 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.118 2021/09/27 16:22:58 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.117 2021/07/12 12:56:52 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.118 2021/09/27 16:22:58 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2456,18 +2456,18 @@ x86_print_cache_and_tlb_info(struct cpu_
if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 ||
ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL);
- sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep);
+ sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL);
+ sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL);
+ sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
- sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
+ sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL);
if (sep != NULL)
aprint_verbose("\n");
}
@@ -2478,56 +2478,56 @@ x86_print_cache_and_tlb_info(struct cpu_
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL);
+ sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL);
sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL);
+ sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL);
sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL);
+ sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL);
+ sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL);
+ sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL);
sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB",
+ sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:",
NULL);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB",
+ sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:",
NULL);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB",
+ sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:",
NULL);
if (sep != NULL)
aprint_verbose("\n");
}
if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
- sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB",
+ sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:",
NULL);
if (sep != NULL)
aprint_verbose("\n");
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Sun Nov 17 15:32:00 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
0x7d and 0x7e are for 10th generation Core (Ice Lake).
To generate a diff of this commit:
cvs rdiff -u -r1.107 -r1.108 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.107 src/usr.sbin/cpuctl/arch/i386.c:1.108
--- src/usr.sbin/cpuctl/arch/i386.c:1.107 Thu Oct 3 15:21:44 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Sun Nov 17 15:32:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.107 2019/10/03 15:21:44 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.108 2019/11/17 15:32:00 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.107 2019/10/03 15:21:44 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.108 2019/11/17 15:32:00 msaitoh Exp $");
#endif /* not lint */
#include
@@ -386,8 +386,8 @@ const struct cpu_cpuid_nameclass i386_cp
[0x6a] = "Future Xeon (Ice Lake)",
[0x6c] = "Future Xeon (Ice Lake)",
[0x7a] = "Atom (Goldmont Plus)",
-[0x7d] = "Future Core (Ice Lake)",
-[0x7e] = "Future Core (Ice Lake)",
+[0x7d] = "10th gen Core (Ice Lake)",
+[0x7e] = "10th gen Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Sun Nov 17 15:32:00 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: 0x7d and 0x7e are for 10th generation Core (Ice Lake). To generate a diff of this commit: cvs rdiff -u -r1.107 -r1.108 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Fri Aug 30 13:12:25 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Decode AMD's CPUID Fn8000_0008 %ebx. To generate a diff of this commit: cvs rdiff -u -r1.104 -r1.105 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Fri Aug 30 13:12:25 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Decode AMD's CPUID Fn8000_0008 %ebx.
To generate a diff of this commit:
cvs rdiff -u -r1.104 -r1.105 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.104 src/usr.sbin/cpuctl/arch/i386.c:1.105
--- src/usr.sbin/cpuctl/arch/i386.c:1.104 Fri Jul 26 10:03:40 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Fri Aug 30 13:12:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.105 2019/08/30 13:12:24 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.105 2019/08/30 13:12:24 msaitoh Exp $");
#endif /* not lint */
#include
@@ -2292,10 +2292,16 @@ identifycpu(int fd, const char *cpuname)
ci->ci_max_ext_cpuid = descs[0];
else
ci->ci_max_ext_cpuid = 0;
- if (descs[0] >= 0x8007)
+ if (ci->ci_max_ext_cpuid >= 0x8007)
powernow_probe(ci);
- if ((descs[0] >= 0x800a)
+ if (ci->ci_max_ext_cpuid >= 0x8008) {
+ x86_cpuid(0x8008, descs);
+ print_bits(cpuname, "AMD Extended features",
+ CPUID_CAPEX_FLAGS, descs[1]);
+ }
+
+ if ((ci->ci_max_ext_cpuid >= 0x800a)
&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x800a, descs);
aprint_verbose("%s: SVM Rev. %d\n", cpuname,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Wed May 29 03:24:23 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
White space fix. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.102 -r1.103 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.102 src/usr.sbin/cpuctl/arch/i386.c:1.103
--- src/usr.sbin/cpuctl/arch/i386.c:1.102 Tue May 28 07:51:58 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Wed May 29 03:24:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.102 2019/05/28 07:51:58 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.103 2019/05/29 03:24:23 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.102 2019/05/28 07:51:58 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.103 2019/05/29 03:24:23 msaitoh Exp $");
#endif /* not lint */
#include
@@ -168,7 +168,7 @@ static const char * const i386_intel_bra
"Pentium III", /* Intel (R) Pentium (R) III processor */
"", /* 0x05: Reserved */
"Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
- "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
+ "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
"Celeron", /* Intel (R) Celeron (TM) processor */
@@ -321,10 +321,10 @@ const struct cpu_cpuid_nameclass i386_cp
[0x06] = "Celeron (Mendocino)",
[0x07] = "Pentium III (Katmai)",
[0x08] = "Pentium III (Coppermine)",
-[0x09] = "Pentium M (Banias)",
+[0x09] = "Pentium M (Banias)",
[0x0a] = "Pentium III Xeon (Cascades)",
[0x0b] = "Pentium III (Tualatin)",
-[0x0d] = "Pentium M (Dothan)",
+[0x0d] = "Pentium M (Dothan)",
[0x0e] = "Pentium Core Duo, Core solo",
[0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, "
"Core 2 Quad 6xxx, "
@@ -729,7 +729,7 @@ static void
cyrix6x86_cpu_setup(struct cpu_info *ci)
{
- /*
+ /*
* Do not disable the TSC on the Geode GX, it's reported to
* work fine.
*/
@@ -979,7 +979,7 @@ amd_family6_probe(struct cpu_info *ci)
if (*cpu_brand_string == '\0')
return;
-
+
for (i = 1; i < __arraycount(amd_brand); i++)
if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) {
ci->ci_brand_id = i;
@@ -1230,10 +1230,10 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
}
}
-static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
+static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
AMD_L2CACHE_INFO;
-static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
+static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
AMD_L3CACHE_INFO;
static void
@@ -2112,8 +2112,8 @@ identifycpu(int fd, const char *cpuname)
if (cpu_vendor == CPUVENDOR_AMD) {
if (ci->ci_family == 6 && ci->ci_model >= 6) {
if (ci->ci_brand_id == 1)
- /*
- * It's Duron. We override the
+ /*
+ * It's Duron. We override the
* name, since it might have
* been misidentified as Athlon.
*/
@@ -2131,7 +2131,7 @@ identifycpu(int fd, const char *cpuname)
name = tmp;
}
}
-
+
if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6)
vendorname = "VIA";
}
@@ -2256,7 +2256,7 @@ identifycpu(int fd, const char *cpuname)
|| (cpu_vendor == CPUVENDOR_AMD))) {
uint16_t lmin, lmax;
x86_cpuid(5, descs);
-
+
print_bits(cpuname, "MONITOR/MWAIT extensions",
CPUID_MON_FLAGS, descs[2]);
lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE);
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Wed May 29 03:24:23 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: White space fix. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Tue May 28 07:51:58 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Update from the latest Intel SDM: - Add Cascade Lake, Copper Lake - Add Future Xeon (Cannon Lake) - Add 06_7DH for another Ice Lake - Add Coffee Lake based Xeon E To generate a diff of this commit: cvs rdiff -u -r1.101 -r1.102 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Tue May 28 07:51:58 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Update from the latest Intel SDM:
- Add Cascade Lake, Copper Lake
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake
- Add Coffee Lake based Xeon E
To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.101 src/usr.sbin/cpuctl/arch/i386.c:1.102
--- src/usr.sbin/cpuctl/arch/i386.c:1.101 Tue May 28 07:44:14 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Tue May 28 07:51:58 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.101 2019/05/28 07:44:14 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.102 2019/05/28 07:51:58 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.101 2019/05/28 07:44:14 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.102 2019/05/28 07:51:58 msaitoh Exp $");
#endif /* not lint */
#include
@@ -373,7 +373,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x4d] = "Atom C2000",
[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
-[0x55] = "Xeon Scalable (Skylake)",
+[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
[0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Xeon Phi [357]200 (Knights Landing)",
[0x5a] = "Atom E3500",
@@ -381,13 +381,16 @@ const struct cpu_cpuid_nameclass i386_cp
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x5f] = "Atom (Goldmont, Denverton)",
-[0x66] = "Future Core (Cannon Lake)",
+[0x66] = "8th gen Core i3 (Cannon Lake)",
+[0x6a] = "Future Xeon (Ice Lake)",
+[0x6c] = "Future Xeon (Ice Lake)",
[0x7a] = "Atom (Goldmont Plus)",
+[0x7d] = "Future Core (Ice Lake)",
[0x7e] = "Future Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
-[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
-[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
+[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: msaitoh Date: Tue May 28 07:44:14 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Revert previous (accidentally committed). To generate a diff of this commit: cvs rdiff -u -r1.100 -r1.101 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: msaitoh
Date: Tue May 28 07:44:14 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Revert previous (accidentally committed).
To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.100 src/usr.sbin/cpuctl/arch/i386.c:1.101
--- src/usr.sbin/cpuctl/arch/i386.c:1.100 Tue May 28 07:41:50 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Tue May 28 07:44:14 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.100 2019/05/28 07:41:50 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.101 2019/05/28 07:44:14 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.100 2019/05/28 07:41:50 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.101 2019/05/28 07:44:14 msaitoh Exp $");
#endif /* not lint */
#include
@@ -373,7 +373,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x4d] = "Atom C2000",
[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
-[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
+[0x55] = "Xeon Scalable (Skylake)",
[0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Xeon Phi [357]200 (Knights Landing)",
[0x5a] = "Atom E3500",
@@ -381,16 +381,13 @@ const struct cpu_cpuid_nameclass i386_cp
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x5f] = "Atom (Goldmont, Denverton)",
-[0x66] = "8th gen Core i3 (Cannon Lake)",
-[0x6a] = "Future Xeon (Ice Lake)",
-[0x6c] = "Future Xeon (Ice Lake)",
+[0x66] = "Future Core (Cannon Lake)",
[0x7a] = "Atom (Goldmont Plus)",
-[0x7d] = "Future Core (Ice Lake)",
[0x7e] = "Future Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
-[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
-[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
+[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: mlelstv
Date: Tue May 21 05:29:21 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: cpuctl_i386.h i386-asm.S i386.c x86_64-asm.S
Log Message:
All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/cpuctl_i386.h
cvs rdiff -u -r1.6 -r1.7 src/usr.sbin/cpuctl/arch/i386-asm.S \
src/usr.sbin/cpuctl/arch/x86_64-asm.S
cvs rdiff -u -r1.98 -r1.99 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/cpuctl_i386.h
diff -u src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.3 src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.4
--- src/usr.sbin/cpuctl/arch/cpuctl_i386.h:1.3 Fri May 10 16:42:57 2019
+++ src/usr.sbin/cpuctl/arch/cpuctl_i386.h Tue May 21 05:29:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl_i386.h,v 1.3 2019/05/10 16:42:57 mlelstv Exp $ */
+/* $NetBSD: cpuctl_i386.h,v 1.4 2019/05/21 05:29:21 mlelstv Exp $ */
/* Interfaces to code in i386-asm.S */
@@ -7,4 +7,3 @@
void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
uint32_t x86_identify(void);
uint32_t x86_xgetbv(void);
-uint64_t rdmsr(u_int);
Index: src/usr.sbin/cpuctl/arch/i386-asm.S
diff -u src/usr.sbin/cpuctl/arch/i386-asm.S:1.6 src/usr.sbin/cpuctl/arch/i386-asm.S:1.7
--- src/usr.sbin/cpuctl/arch/i386-asm.S:1.6 Sat May 11 12:24:42 2019
+++ src/usr.sbin/cpuctl/arch/i386-asm.S Tue May 21 05:29:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386-asm.S,v 1.6 2019/05/11 12:24:42 mlelstv Exp $ */
+/* $NetBSD: i386-asm.S,v 1.7 2019/05/21 05:29:21 mlelstv Exp $ */
/*-
* Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc.
@@ -164,11 +164,3 @@ is486dlc:
movl $CPU_486DLC,%eax
ret
-ENTRY(rdmsr)
- movl 4(%esp), %ecx
- pushl %edi
- movl $OPTERON_MSR_PASSCODE, %edi
- rdmsr
- popl %edi
- ret
-END(rdmsr)
Index: src/usr.sbin/cpuctl/arch/x86_64-asm.S
diff -u src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.6 src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.7
--- src/usr.sbin/cpuctl/arch/x86_64-asm.S:1.6 Fri May 10 16:42:57 2019
+++ src/usr.sbin/cpuctl/arch/x86_64-asm.S Tue May 21 05:29:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: x86_64-asm.S,v 1.6 2019/05/10 16:42:57 mlelstv Exp $ */
+/* $NetBSD: x86_64-asm.S,v 1.7 2019/05/21 05:29:21 mlelstv Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -55,11 +55,3 @@ ENTRY(x86_identify)
movl $-1,%eax
ret
-ENTRY(rdmsr)
- movq %rdi, %rcx
- xorq %rax, %rax
- movl $OPTERON_MSR_PASSCODE, %edi
- rdmsr
- shlq $32, %rdx
- orq %rdx, %rax
- ret
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.98 src/usr.sbin/cpuctl/arch/i386.c:1.99
--- src/usr.sbin/cpuctl/arch/i386.c:1.98 Sat May 11 17:21:07 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Tue May 21 05:29:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.98 2019/05/11 17:21:07 kre Exp $ */
+/* $NetBSD: i386.c,v 1.99 2019/05/21 05:29:21 mlelstv Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.98 2019/05/11 17:21:07 kre Exp $");
+__RCSID("$NetBSD: i386.c,v 1.99 2019/05/21 05:29:21 mlelstv Exp $");
#endif /* not lint */
#include
@@ -1959,6 +1959,7 @@ identifycpu_cpuids_amd(struct cpu_info *
if (core_bits == 0)
core_bits = ilog2(core_max - 1) + 1;
+#if 0 /* MSRs need kernel mode */
if (cpu_family < 0x11) {
const uint64_t reg = rdmsr(MSR_NB_CFG);
if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) {
@@ -1968,6 +1969,7 @@ identifycpu_cpuids_amd(struct cpu_info *
(apic_id >> 5) | (node_id << 2);
}
}
+#endif
if (cpu_family == 0x17) {
x86_cpuid(0x801e, descs);
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: mlelstv Date: Tue May 21 05:29:21 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: cpuctl_i386.h i386-asm.S i386.c x86_64-asm.S Log Message: All MSRs can only be read at privilege level 0. The exact APIC ID cannot be determined on some AMD CPUs. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/usr.sbin/cpuctl/arch/cpuctl_i386.h cvs rdiff -u -r1.6 -r1.7 src/usr.sbin/cpuctl/arch/i386-asm.S \ src/usr.sbin/cpuctl/arch/x86_64-asm.S cvs rdiff -u -r1.98 -r1.99 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: gutteridge Date: Fri May 17 23:51:35 UTC 2019 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl.8: minor fixes To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/cpuctl/cpuctl.8 diff -u src/usr.sbin/cpuctl/cpuctl.8:1.19 src/usr.sbin/cpuctl/cpuctl.8:1.20 --- src/usr.sbin/cpuctl/cpuctl.8:1.19 Mon Apr 15 22:37:13 2019 +++ src/usr.sbin/cpuctl/cpuctl.8 Fri May 17 23:51:35 2019 @@ -1,4 +1,4 @@ -.\" $NetBSD: cpuctl.8,v 1.19 2019/04/15 22:37:13 gutteridge Exp $ +.\" $NetBSD: cpuctl.8,v 1.20 2019/05/17 23:51:35 gutteridge Exp $ .\" .\" Copyright (c) 2007, 2008, 2012, 2015 The NetBSD Foundation, Inc. .\" All rights reserved. @@ -27,7 +27,7 @@ .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE .\" POSSIBILITY OF SUCH DAMAGE. .\" -.Dd April 15, 2019 +.Dd May 17, 2019 .Dt CPUCTL 8 .Os .Sh NAME @@ -47,7 +47,7 @@ The first argument, .Ar command , specifies the action to take. Valid commands are: -.Bl -tag -width offline +.Bl -tag -width identify .It identify Ar cpu Op Ar cpu ... Output information on the specified CPU's features and capabilities. Not available on all architectures. @@ -57,7 +57,7 @@ state change. .It offline Ar cpu Op Ar cpu ... Set the specified CPUs off line. .Pp -Unbound LWPs (lightweight processes) will not be executed on the CPUs +Unbound LWPs (lightweight processes) will not be executed on a CPU while it is off line. Bound LWPs will continue to be executed on the CPUs, and device interrupts routed to the CPUs will continue to be handled. @@ -66,7 +66,7 @@ away from individual CPUs. .Pp At least one CPU in the system must remain on line. .It online Ar cpu Op Ar cpu ... -Set the specified CPUs on line, making it available to run unbound LWPs. +Set the specified CPUs on line, making them available to run unbound LWPs. .It ucode Xo .Op Ar cpu .Op Ar file @@ -84,7 +84,7 @@ The command prints the installed version on the specified CPUs. On success the .Cm identify -command show different ucode versions before and after this command. +command shows different ucode versions before and after this command. The ucode updates are found in the default firmware path found in sysctl hw.firmware.path. .It intr Ar cpu Op Ar cpu ...
CVS commit: src/usr.sbin/cpuctl
Module Name:src Committed By: gutteridge Date: Fri May 17 23:51:35 UTC 2019 Modified Files: src/usr.sbin/cpuctl: cpuctl.8 Log Message: cpuctl.8: minor fixes To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/usr.sbin/cpuctl/cpuctl.8 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: kre Date: Sat May 11 17:21:07 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: Undo previous. Not needed (and file included isn't installed anyway. To generate a diff of this commit: cvs rdiff -u -r1.97 -r1.98 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: kre
Date: Sat May 11 17:21:07 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Undo previous. Not needed (and file included isn't installed anyway.
To generate a diff of this commit:
cvs rdiff -u -r1.97 -r1.98 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.97 src/usr.sbin/cpuctl/arch/i386.c:1.98
--- src/usr.sbin/cpuctl/arch/i386.c:1.97 Sat May 11 12:59:50 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Sat May 11 17:21:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $ */
+/* $NetBSD: i386.c,v 1.98 2019/05/11 17:21:07 kre Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $");
+__RCSID("$NetBSD: i386.c,v 1.98 2019/05/11 17:21:07 kre Exp $");
#endif /* not lint */
#include
@@ -81,7 +81,6 @@ __RCSID("$NetBSD: i386.c,v 1.97 2019/05/
#include
#include
-#include
#include
#include
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: christos
Date: Sat May 11 12:59:50 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
need cpufunc.h for rdmsr
To generate a diff of this commit:
cvs rdiff -u -r1.96 -r1.97 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.96 src/usr.sbin/cpuctl/arch/i386.c:1.97
--- src/usr.sbin/cpuctl/arch/i386.c:1.96 Fri May 10 12:42:57 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Sat May 11 08:59:50 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.96 2019/05/10 16:42:57 mlelstv Exp $ */
+/* $NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.96 2019/05/10 16:42:57 mlelstv Exp $");
+__RCSID("$NetBSD: i386.c,v 1.97 2019/05/11 12:59:50 christos Exp $");
#endif /* not lint */
#include
@@ -81,6 +81,7 @@ __RCSID("$NetBSD: i386.c,v 1.96 2019/05/
#include
#include
+#include
#include
#include
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: christos Date: Sat May 11 12:59:50 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: need cpufunc.h for rdmsr To generate a diff of this commit: cvs rdiff -u -r1.96 -r1.97 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: mlelstv Date: Sat May 11 12:24:42 UTC 2019 Modified Files: src/usr.sbin/cpuctl/arch: i386-asm.S Log Message: Fix copy error, the function is named rdmsr(). Found by kre@ To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/usr.sbin/cpuctl/arch/i386-asm.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl
Module Name:src
Committed By: maxv
Date: Sat May 11 11:59:22 UTC 2019
Modified Files:
src/usr.sbin/cpuctl: cpuctl.c
Log Message:
Check the return value of cpuset_set(), to prevent future surprises.
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/usr.sbin/cpuctl/cpuctl.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/cpuctl.c
diff -u src/usr.sbin/cpuctl/cpuctl.c:1.29 src/usr.sbin/cpuctl/cpuctl.c:1.30
--- src/usr.sbin/cpuctl/cpuctl.c:1.29 Tue Jan 16 08:23:18 2018
+++ src/usr.sbin/cpuctl/cpuctl.c Sat May 11 11:59:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuctl.c,v 1.29 2018/01/16 08:23:18 mrg Exp $ */
+/* $NetBSD: cpuctl.c,v 1.30 2019/05/11 11:59:21 maxv Exp $ */
/*-
* Copyright (c) 2007, 2008, 2009, 2012, 2015 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#ifndef lint
#include
-__RCSID("$NetBSD: cpuctl.c,v 1.29 2018/01/16 08:23:18 mrg Exp $");
+__RCSID("$NetBSD: cpuctl.c,v 1.30 2019/05/11 11:59:21 maxv Exp $");
#endif /* not lint */
#include
@@ -239,7 +239,8 @@ cpu_ucode(char **argv)
if (cpuset == NULL)
err(EXIT_FAILURE, "cpuset_create");
cpuset_zero(cpuset);
- cpuset_set(id, cpuset);
+ if (cpuset_set(id, cpuset) < 0)
+ err(EXIT_FAILURE, "cpuset_set");
if (_sched_setaffinity(0, 0, cpuset_size(cpuset), cpuset) < 0) {
err(EXIT_FAILURE, "_sched_setaffinity");
}
@@ -271,7 +272,8 @@ cpu_identify(char **argv)
if (cpuset == NULL)
err(EXIT_FAILURE, "cpuset_create");
cpuset_zero(cpuset);
- cpuset_set(id, cpuset);
+ if (cpuset_set(id, cpuset) < 0)
+err(EXIT_FAILURE, "cpuset_set");
if (_sched_setaffinity(0, 0, cpuset_size(cpuset), cpuset) < 0) {
if (errno == EPERM) {
printf("Cannot bind to target CPU. Output "
Re: CVS commit: src/usr.sbin/cpuctl/arch
On Nov 7, 6:18pm, SAITOH Masanobu wrote: } } Module Name: src } Committed By: msaitoh } Date: Thu Nov 7 18:18:59 UTC 2013 } } Modified Files: } src/usr.sbin/cpuctl/arch: i386.c } } Log Message: } Update some processor names. } } Modified files: } } Index: src/usr.sbin/cpuctl/arch/i386.c } diff -u src/usr.sbin/cpuctl/arch/i386.c:1.47 src/usr.sbin/cpuctl/arch/i386.c:1.48 } --- src/usr.sbin/cpuctl/arch/i386.c:1.47 Wed Oct 30 08:42:16 2013 } +++ src/usr.sbin/cpuctl/arch/i386.c Thu Nov 7 18:18:59 2013 } @@ -1,4 +1,4 @@ } -/* $NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $*/ } +/* $NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $*/ } } /*- } * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. } @@ -57,7 +57,7 @@ } } #include sys/cdefs.h } #ifndef lint } -__RCSID($NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $); } +__RCSID($NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $); } #endif /* not lint */ } } #include sys/types.h } @@ -342,18 +342,19 @@ const struct cpu_cpuid_nameclass i386_cp } [0x2a] = Xeon E3-12xx, 2nd gen i7, i5, }i3 2xxx, } [0x2c] = Xeon 36xx 56xx, i7, i5 and i3, } - [0x2d] = Xeon E5 Sandy bridy family, } + [0x2d] = Xeon E5 Sandy Bridy family, Shouldn't that be Sandy Bridge? } + Core i7-39xx Extreme, } [0x2e] = Xeon 75xx 65xx, } [0x2f] = Xeon E7 family, } [0x35] = Atom Family, } [0x36] = Atom S1000, } [0x37] = Atom C2000, E3000, } [0x3a] = Xeon E3-1200v2 and 3rd gen core, } - Ivy bridge, } + Ivy Bridge, } [0x3c] = 4th gen Core, Xeon E3-12xx v3 }(Haswell), } [0x3d] = Next gen Core, } - [0x3e] = Next gen Xeon E5/E7, Ivy bridge, } + [0x3e] = Xeon E5/E7, Ivy Bridge-EP, } [0x3f] = Future gen Xeon, } [0x45] = 4th gen Core, Xeon E3-12xx v3 }(Haswell), } }-- End of excerpt from SAITOH Masanobu
Re: CVS commit: src/usr.sbin/cpuctl/arch
(2013/11/08 3:45), John Nemeth wrote: On Nov 7, 6:18pm, SAITOH Masanobu wrote: } } Module Name:src } Committed By: msaitoh } Date: Thu Nov 7 18:18:59 UTC 2013 } } Modified Files: } src/usr.sbin/cpuctl/arch: i386.c } } Log Message: } Update some processor names. } } Modified files: } } Index: src/usr.sbin/cpuctl/arch/i386.c } diff -u src/usr.sbin/cpuctl/arch/i386.c:1.47 src/usr.sbin/cpuctl/arch/i386.c:1.48 } --- src/usr.sbin/cpuctl/arch/i386.c:1.47Wed Oct 30 08:42:16 2013 } +++ src/usr.sbin/cpuctl/arch/i386.c Thu Nov 7 18:18:59 2013 } @@ -1,4 +1,4 @@ } -/* $NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $*/ } +/* $NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $*/ } } /*- } * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. } @@ -57,7 +57,7 @@ } } #include sys/cdefs.h } #ifndef lint } -__RCSID($NetBSD: i386.c,v 1.47 2013/10/30 08:42:16 mrg Exp $); } +__RCSID($NetBSD: i386.c,v 1.48 2013/11/07 18:18:59 msaitoh Exp $); } #endif /* not lint */ } } #include sys/types.h } @@ -342,18 +342,19 @@ const struct cpu_cpuid_nameclass i386_cp } [0x2a] = Xeon E3-12xx, 2nd gen i7, i5, } i3 2xxx, } [0x2c] = Xeon 36xx 56xx, i7, i5 and i3, } - [0x2d] = Xeon E5 Sandy bridy family, } + [0x2d] = Xeon E5 Sandy Bridy family, Shouldn't that be Sandy Bridge? Fixed. Thanks! } +Core i7-39xx Extreme, } [0x2e] = Xeon 75xx 65xx, } [0x2f] = Xeon E7 family, } [0x35] = Atom Family, } [0x36] = Atom S1000, } [0x37] = Atom C2000, E3000, } [0x3a] = Xeon E3-1200v2 and 3rd gen core, } -Ivy bridge, } +Ivy Bridge, } [0x3c] = 4th gen Core, Xeon E3-12xx v3 } (Haswell), } [0x3d] = Next gen Core, } - [0x3e] = Next gen Xeon E5/E7, Ivy bridge, } + [0x3e] = Xeon E5/E7, Ivy Bridge-EP, } [0x3f] = Future gen Xeon, } [0x45] = 4th gen Core, Xeon E3-12xx v3 } (Haswell), } }-- End of excerpt from SAITOH Masanobu -- --- SAITOH Masanobu (msai...@execsw.org msai...@netbsd.org)
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: cegger Date: Tue Feb 23 08:46:33 UTC 2010 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: check for svm feature flags if cpuid function 0x800a is available. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/cpuctl/arch
Module Name:src Committed By: mrg Date: Tue Feb 16 00:13:14 UTC 2010 Modified Files: src/usr.sbin/cpuctl/arch: i386.c Log Message: don't call most/all Core2's (Merom). To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
