CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:23:31 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Define PRIxPTE


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.9 src/sys/arch/aarch64/include/pte.h:1.10
--- src/sys/arch/aarch64/include/pte.h:1.9	Wed Sep 11 18:19:35 2019
+++ src/sys/arch/aarch64/include/pte.h	Wed Sep 11 18:23:31 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.9 2019/09/11 18:19:35 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.10 2019/09/11 18:23:31 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,13 @@
 
 #ifndef _LOCORE
 typedef uint64_t pd_entry_t;	/* L0(512G) / L1(1G) / L2(2M) table entry */
+
+#ifndef __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
 typedef uint64_t pt_entry_t;	/* L3(4k) table entry */
+#define PRIxPTE PRIx64
+#endif /* __BSD_PTENTRY_T__ */
+
 #endif /* _LOCORE */
 
 /*



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:23:31 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Define PRIxPTE


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:19:35 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h pte.h

Log Message:
Move the TCR and TTBR defines into armreg.h where they below.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.26 src/sys/arch/aarch64/include/armreg.h:1.27
--- src/sys/arch/aarch64/include/armreg.h:1.26	Mon Aug 12 23:31:48 2019
+++ src/sys/arch/aarch64/include/armreg.h	Wed Sep 11 18:19:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.26 2019/08/12 23:31:48 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.27 2019/09/11 18:19:35 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -646,7 +646,60 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
 AARCH64REG_READ_INLINE(tcr_el1)		// Translation Control Register
 AARCH64REG_WRITE_INLINE(tcr_el1)
 
-#define TCR_PAGE_SIZE1(tcr)	(1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8))
+
+/* TCR_EL1 - Translation Control Register */
+#define TCR_TBI1		__BIT(38)		/* ignore Top Byte TTBR1_EL1 */
+#define TCR_TBI0		__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
+#define TCR_AS64K		__BIT(36)		/* Use 64K ASIDs */
+#define TCR_IPS			__BITS(34,32)		/* Intermediate PhysAdr Size */
+#define  TCR_IPS_4PB		__SHIFTIN(6,TCR_IPS)	/* 52 bits (  4 PB) */
+#define  TCR_IPS_256TB		__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
+#define  TCR_IPS_16TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
+#define  TCR_IPS_4TB		__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
+#define  TCR_IPS_1TB		__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
+#define  TCR_IPS_64GB		__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
+#define  TCR_IPS_4GB		__SHIFTIN(0,TCR_IPS)	/* 32 bits   (4 GB) */
+#define TCR_TG1			__BITS(31,30)		/* TTBR1 Page Granule Size */
+#define  TCR_TG1_16KB		__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
+#define  TCR_TG1_4KB		__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
+#define  TCR_TG1_64KB		__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
+#define TCR_SH1			__BITS(29,28)
+#define  TCR_SH1_NONE		__SHIFTIN(0,TCR_SH1)
+#define  TCR_SH1_OUTER		__SHIFTIN(2,TCR_SH1)
+#define  TCR_SH1_INNER		__SHIFTIN(3,TCR_SH1)
+#define TCR_ORGN1		__BITS(27,26)		/* TTBR1 Outer cacheability */
+#define  TCR_ORGN1_NC		__SHIFTIN(0,TCR_ORGN1)	/* Non Cacheable */
+#define  TCR_ORGN1_WB_WA	__SHIFTIN(1,TCR_ORGN1)	/* WriteBack WriteAllocate */
+#define  TCR_ORGN1_WT		__SHIFTIN(2,TCR_ORGN1)	/* WriteThrough */
+#define  TCR_ORGN1_WB		__SHIFTIN(3,TCR_ORGN1)	/* WriteBack */
+#define TCR_IRGN1		__BITS(25,24)		/* TTBR1 Inner cacheability */
+#define  TCR_IRGN1_NC		__SHIFTIN(0,TCR_IRGN1)	/* Non Cacheable */
+#define  TCR_IRGN1_WB_WA	__SHIFTIN(1,TCR_IRGN1)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN1_WT		__SHIFTIN(2,TCR_IRGN1)	/* WriteThrough */
+#define  TCR_IRGN1_WB		__SHIFTIN(3,TCR_IRGN1)	/* WriteBack */
+#define TCR_EPD1		__BIT(23)		/* Walk Disable for TTBR1_EL1 */
+#define TCR_A1			__BIT(22)		/* ASID is in TTBR1_EL1 */
+#define TCR_T1SZ		__BITS(21,16)		/* Size offset for TTBR1_EL1 */
+#define TCR_TG0			__BITS(15,14)		/* TTBR0 Page Granule Size */
+#define  TCR_TG0_4KB		__SHIFTIN(0,TCR_TG0)	/* 4KB page size */
+#define  TCR_TG0_64KB		__SHIFTIN(1,TCR_TG0)	/* 64KB page size */
+#define  TCR_TG0_16KB		__SHIFTIN(2,TCR_TG0)	/* 16KB page size */
+#define TCR_SH0			__BITS(13,12)
+#define  TCR_SH0_NONE		__SHIFTIN(0,TCR_SH0)
+#define  TCR_SH0_OUTER		__SHIFTIN(2,TCR_SH0)
+#define  TCR_SH0_INNER		__SHIFTIN(3,TCR_SH0)
+#define TCR_ORGN0		__BITS(11,10)		/* TTBR0 Outer cacheability */
+#define  TCR_ORGN0_NC		__SHIFTIN(0,TCR_ORGN0)	/* Non Cacheable */
+#define  TCR_ORGN0_WB_WA	__SHIFTIN(1,TCR_ORGN0)	/* WriteBack WriteAllocate */
+#define  TCR_ORGN0_WT		__SHIFTIN(2,TCR_ORGN0)	/* WriteThrough */
+#define  TCR_ORGN0_WB		__SHIFTIN(3,TCR_ORGN0)	/* WriteBack */
+#define TCR_IRGN0		__BITS(9,8)		/* TTBR0 Inner cacheability */
+#define  TCR_IRGN0_NC		__SHIFTIN(0,TCR_IRGN0)	/* Non Cacheable */
+#define  TCR_IRGN0_WB_WA	__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN0_WT		__SHIFTIN(2,TCR_IRGN0)	/* WriteThrough */
+#define  TCR_IRGN0_WB		__SHIFTIN(3,TCR_IRGN0)	/* WriteBack */
+#define TCR_EPD0		__BIT(7)		/* Walk Disable for TTBR0 */
+#define TCR_T0SZ		__BITS(5,0)		/* Size offset for TTBR0_EL1 */
 
 AARCH64REG_READ_INLINE(tpidr_el1)	// Thread ID Register (EL1)
 AARCH64REG_WRITE_INLINE(tpidr_el1)
@@ -659,6 +712,9 @@ AARCH64REG_WRITE_INLINE(ttbr0_el1)
 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
 AARCH64REG_WRITE_INLINE(ttbr1_el1)
 
+#define TTBR_ASID		__BITS(63,48)
+#define TTBR_BADDR		__BITS(47,0)
+
 AARCH64REG_READ_INLINE(vbar_el1)	// Vector Base Address Register
 AARCH64REG_WRITE_INLINE(vbar_el1)
 

Index: 

CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Sep 11 18:19:35 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h pte.h

Log Message:
Move the TCR and TTBR defines into armreg.h where they below.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Sep 11 11:43:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
- Fix TCR_TG0 field definitions to match Armv8 ARM
- Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB
- Whitespace fixes


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-11 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Sep 11 11:43:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
- Fix TCR_TG0 field definitions to match Armv8 ARM
- Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB
- Whitespace fixes


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.7 src/sys/arch/aarch64/include/pte.h:1.8
--- src/sys/arch/aarch64/include/pte.h:1.7	Thu Aug 15 09:07:34 2019
+++ src/sys/arch/aarch64/include/pte.h	Wed Sep 11 11:43:15 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.8 2019/09/11 11:43:15 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -134,8 +134,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define TCR_TBI0		__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
 #define TCR_AS64K		__BIT(36)		/* Use 64K ASIDs */
 #define TCR_IPS			__BITS(34,32)		/* Intermediate PhysAdr Size */
+#define  TCR_IPS_4PB		__SHIFTIN(6,TCR_IPS)	/* 52 bits (  4 PB) */
 #define  TCR_IPS_256TB		__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
-#define  TCR_IPS_64TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
+#define  TCR_IPS_16TB		__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
 #define  TCR_IPS_4TB		__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
 #define  TCR_IPS_1TB		__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
 #define  TCR_IPS_64GB		__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
@@ -162,9 +163,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define TCR_A1			__BIT(22)		/* ASID is in TTBR1_EL1 */
 #define TCR_T1SZ		__BITS(21,16)		/* Size offset for TTBR1_EL1 */
 #define TCR_TG0			__BITS(15,14)		/* TTBR0 Page Granule Size */
-#define  TCR_TG0_16KB		__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
-#define  TCR_TG0_4KB		__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
-#define  TCR_TG0_64KB		__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
+#define  TCR_TG0_4KB		__SHIFTIN(0,TCR_TG0)	/* 4KB page size */
+#define  TCR_TG0_64KB		__SHIFTIN(1,TCR_TG0)	/* 64KB page size */
+#define  TCR_TG0_16KB		__SHIFTIN(2,TCR_TG0)	/* 16KB page size */
 #define TCR_SH0			__BITS(13,12)
 #define  TCR_SH0_NONE		__SHIFTIN(0,TCR_SH0)
 #define  TCR_SH0_OUTER		__SHIFTIN(2,TCR_SH0)
@@ -176,7 +177,7 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define  TCR_ORGN0_WB		__SHIFTIN(3,TCR_ORGN0)	/* WriteBack */
 #define TCR_IRGN0		__BITS(9,8)		/* TTBR0 Inner cacheability */
 #define  TCR_IRGN0_NC		__SHIFTIN(0,TCR_IRGN0)	/* Non Cacheable */
-#define  TCR_IRGN0_WB_WA		__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
+#define  TCR_IRGN0_WB_WA	__SHIFTIN(1,TCR_IRGN0)	/* WriteBack WriteAllocate */
 #define  TCR_IRGN0_WT		__SHIFTIN(2,TCR_IRGN0)	/* WriteThrough */
 #define  TCR_IRGN0_WB		__SHIFTIN(3,TCR_IRGN0)	/* WriteBack */
 #define TCR_EPD0		__BIT(7)		/* Walk Disable for TTBR0 */



CVS commit: src/sys/arch/aarch64/include

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:10:24 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
add checking status of MMU and devmap to make _platform_early_putchar() 
available at all times.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-09-07 Thread Ryo Shimizu
Module Name:src
Committed By:   ryo
Date:   Sat Sep  7 11:10:24 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: cpufunc.h

Log Message:
add checking status of MMU and devmap to make _platform_early_putchar() 
available at all times.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/cpufunc.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/cpufunc.h
diff -u src/sys/arch/aarch64/include/cpufunc.h:1.5 src/sys/arch/aarch64/include/cpufunc.h:1.6
--- src/sys/arch/aarch64/include/cpufunc.h:1.5	Fri Dec 21 08:01:01 2018
+++ src/sys/arch/aarch64/include/cpufunc.h	Sat Sep  7 11:10:24 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.h,v 1.5 2018/12/21 08:01:01 ryo Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.6 2019/09/07 11:10:24 ryo Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -148,8 +148,17 @@ cpu_clusterid(void)
 static inline bool
 cpu_earlydevice_va_p(void)
 {
+	extern vaddr_t virtual_devmap_addr;	/* in pmap.c */
 
-	return false;
+	/* This function may be called before enabling MMU, or mapping KVA */
+	if ((reg_sctlr_el1_read() & SCTLR_M) == 0)
+		return false;
+
+	/* device mapping will be availabled after pmap_devmap_bootstrap() */
+	if (virtual_devmap_addr == 0)
+		return false;
+
+	return true;
 }
 
 #endif /* _KERNEL */



CVS commit: src/sys/arch/aarch64/include

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 09:07:34 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Indent the field value defines.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.6 src/sys/arch/aarch64/include/pte.h:1.7
--- src/sys/arch/aarch64/include/pte.h:1.6	Tue Aug 13 08:27:42 2019
+++ src/sys/arch/aarch64/include/pte.h	Thu Aug 15 09:07:34 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.7 2019/08/15 09:07:34 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -44,17 +44,17 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
  */
 #define LX_TBL_NSTABLE		__BIT(63)	/* inherited next level */
 #define LX_TBL_APTABLE		__BITS(62,61)	/* inherited next level */
-#define LX_TBL_APTABLE_NOEFFECT		__SHIFTIN(0,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_EL0_NOACCESS	__SHIFTIN(1,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO		__SHIFTIN(2,LX_TBL_APTABLE)
-#define LX_TBL_APTABLE_RO_EL0_NOREAD	__SHIFTIN(3,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_NOEFFECT	__SHIFTIN(0,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_EL0_NOACCESS	__SHIFTIN(1,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_RO		__SHIFTIN(2,LX_TBL_APTABLE)
+#define  LX_TBL_APTABLE_RO_EL0_NOREAD	__SHIFTIN(3,LX_TBL_APTABLE)
 #define LX_TBL_UXNTABLE		__BIT(60)	/* inherited next level */
 #define LX_TBL_PXNTABLE		__BIT(59)	/* inherited next level */
 #define LX_BLKPAG_OS		__BITS(58, 55)
-# define LX_BLKPAG_OS_0		__SHIFTIN(1,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_1		__SHIFTIN(2,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_2		__SHIFTIN(4,LX_BLKPAG_OS)
-# define LX_BLKPAG_OS_3		__SHIFTIN(8,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_0		__SHIFTIN(1,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_1		__SHIFTIN(2,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_2		__SHIFTIN(4,LX_BLKPAG_OS)
+#define  LX_BLKPAG_OS_3		__SHIFTIN(8,LX_BLKPAG_OS)
 #define LX_BLKPAG_UXN		__BIT(54)	/* Unprivileged Execute Never */
 #define LX_BLKPAG_PXN		__BIT(53)	/* Privileged Execute Never */
 #define LX_BLKPAG_CONTIG	__BIT(52)	/* Hint of TLB cache */
@@ -64,12 +64,12 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define LX_BLKPAG_NG		__BIT(11)	/* Not Global */
 #define LX_BLKPAG_AF		__BIT(10)	/* Access Flag */
 #define LX_BLKPAG_SH		__BITS(9,8)	/* Shareability */
-#define LX_BLKPAG_SH_NS		__SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
-#define LX_BLKPAG_SH_OS		__SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
-#define LX_BLKPAG_SH_IS		__SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
+#define  LX_BLKPAG_SH_NS	__SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
+#define  LX_BLKPAG_SH_OS	__SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */
+#define  LX_BLKPAG_SH_IS	__SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */
 #define LX_BLKPAG_AP		__BIT(7)
-#define LX_BLKPAG_AP_RW		__SHIFTIN(0,LX_BLKPAG_AP) /* RW */
-#define LX_BLKPAG_AP_RO		__SHIFTIN(1,LX_BLKPAG_AP) /* RO */
+#define  LX_BLKPAG_AP_RW	__SHIFTIN(0,LX_BLKPAG_AP) /* RW */
+#define  LX_BLKPAG_AP_RO	__SHIFTIN(1,LX_BLKPAG_AP) /* RO */
 #define LX_BLKPAG_APUSER	__BIT(6)
 #define LX_BLKPAG_NS		__BIT(5)
 #define LX_BLKPAG_ATTR_INDX	__BITS(4,2)	/* refer MAIR_EL1 attr */
@@ -78,9 +78,9 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define  LX_BLKPAG_ATTR_INDX_2	__SHIFTIN(2,LX_BLKPAG_ATTR_INDX)
 #define  LX_BLKPAG_ATTR_INDX_3	__SHIFTIN(3,LX_BLKPAG_ATTR_INDX)
 #define LX_TYPE			__BIT(1)
-#define LX_TYPE_BLK		__SHIFTIN(0, LX_TYPE)
-#define LX_TYPE_TBL		__SHIFTIN(1, LX_TYPE)
-#define L3_TYPE_PAG		__SHIFTIN(1, LX_TYPE)
+#define  LX_TYPE_BLK		__SHIFTIN(0, LX_TYPE)
+#define  LX_TYPE_TBL		__SHIFTIN(1, LX_TYPE)
+#define  L3_TYPE_PAG		__SHIFTIN(1, LX_TYPE)
 #define LX_VALID		__BIT(0)
 
 #define L1_BLK_OA		__BITS(47, 30)	/* 1GB */
@@ -130,57 +130,57 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 
 
 /* TCR_EL1 - Translation Control Register */
-#define TCR_TBI1	__BIT(38)		/* ignore Top Byte TTBR1_EL1 */
-#define TCR_TBI0	__BIT(37)		/* ignore Top Byte TTBR0_EL1 */
-#define TCR_AS64K	__BIT(36)		/* Use 64K ASIDs */
-#define TCR_IPS		__BITS(34,32)		/* Intermediate PhysAdr Size */
-#define TCR_IPS_256TB	__SHIFTIN(5,TCR_IPS)	/* 48 bits (256 TB) */
-#define TCR_IPS_64TB	__SHIFTIN(4,TCR_IPS)	/* 44 bits  (16 TB) */
-#define TCR_IPS_4TB	__SHIFTIN(3,TCR_IPS)	/* 42 bits  ( 4 TB) */
-#define TCR_IPS_1TB	__SHIFTIN(2,TCR_IPS)	/* 40 bits  ( 1 TB) */
-#define TCR_IPS_64GB	__SHIFTIN(1,TCR_IPS)	/* 36 bits  (64 GB) */
-#define TCR_IPS_4GB	__SHIFTIN(0,TCR_IPS)	/* 32 bits   (4 GB) */
-#define TCR_TG1		__BITS(31,30)		/* TTBR1 Page Granule Size */
-#define TCR_TG1_16KB	__SHIFTIN(1,TCR_TG1)	/* 16KB page size */
-#define TCR_TG1_4KB	__SHIFTIN(2,TCR_TG1)	/* 4KB page size */
-#define TCR_TG1_64KB	__SHIFTIN(3,TCR_TG1)	/* 64KB page size */
-#define TCR_SH1		

CVS commit: src/sys/arch/aarch64/include

2019-08-15 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Thu Aug 15 09:07:34 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Indent the field value defines.  NFCI.


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-13 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Aug 13 08:27:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Add DBM


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-13 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Aug 13 08:27:42 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: pte.h

Log Message:
Add DBM


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.5 src/sys/arch/aarch64/include/pte.h:1.6
--- src/sys/arch/aarch64/include/pte.h:1.5	Thu Oct  4 09:09:29 2018
+++ src/sys/arch/aarch64/include/pte.h	Tue Aug 13 08:27:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.5 2018/10/04 09:09:29 ryo Exp $ */
+/* $NetBSD: pte.h,v 1.6 2019/08/13 08:27:42 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -58,6 +58,7 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define LX_BLKPAG_UXN		__BIT(54)	/* Unprivileged Execute Never */
 #define LX_BLKPAG_PXN		__BIT(53)	/* Privileged Execute Never */
 #define LX_BLKPAG_CONTIG	__BIT(52)	/* Hint of TLB cache */
+#define LX_BLKPAG_DBM		__BIT(51)	/* Dirty Bit Modifier (V8.1) */
 #define LX_TBL_PA		__BITS(47, 12)
 #define LX_BLKPAG_OA		__BITS(47, 12)
 #define LX_BLKPAG_NG		__BIT(11)	/* Not Global */



CVS commit: src/sys/arch/aarch64/include

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:46:07 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: bus_funcs.h

Log Message:
Really provide bus_funcs.h


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:46:07 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: bus_funcs.h

Log Message:
Really provide bus_funcs.h


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/include/bus_funcs.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/bus_funcs.h
diff -u src/sys/arch/aarch64/include/bus_funcs.h:1.2 src/sys/arch/aarch64/include/bus_funcs.h:1.3
--- src/sys/arch/aarch64/include/bus_funcs.h:1.2	Sun Apr  1 04:35:03 2018
+++ src/sys/arch/aarch64/include/bus_funcs.h	Sat Aug 10 16:46:07 2019
@@ -1,3 +1,3 @@
-/*	$NetBSD: bus_funcs.h,v 1.2 2018/04/01 04:35:03 ryo Exp $	*/
+/*	$NetBSD: bus_funcs.h,v 1.3 2019/08/10 16:46:07 skrll Exp $	*/
 
-#include 
+#include 



CVS commit: src/sys/arch/aarch64/include

2019-08-05 Thread Joerg Sonnenberger
Module Name:src
Committed By:   joerg
Date:   Mon Aug  5 16:24:48 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: asm.h

Log Message:
Don't define register replacements when targetting 32bit ARM.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-08-05 Thread Joerg Sonnenberger
Module Name:src
Committed By:   joerg
Date:   Mon Aug  5 16:24:48 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: asm.h

Log Message:
Don't define register replacements when targetting 32bit ARM.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/include/asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/asm.h
diff -u src/sys/arch/aarch64/include/asm.h:1.3 src/sys/arch/aarch64/include/asm.h:1.4
--- src/sys/arch/aarch64/include/asm.h:1.3	Tue Jul 17 18:08:37 2018
+++ src/sys/arch/aarch64/include/asm.h	Mon Aug  5 16:24:48 2019
@@ -1,11 +1,13 @@
-/* $NetBSD: asm.h,v 1.3 2018/07/17 18:08:37 christos Exp $ */
+/* $NetBSD: asm.h,v 1.4 2019/08/05 16:24:48 joerg Exp $ */
 
 #ifndef _AARCH64_ASM_H_
 #define _AARCH64_ASM_H_
 
 #include 
 
+#ifdef __aarch64__
 #define	fp	x29
 #define	lr	x30
+#endif
 
 #endif /* !_AARCH64_ASM_H_ */



CVS commit: src/sys/arch/aarch64/include

2019-07-16 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jul 16 16:18:56 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: machdep.h

Log Message:
Add vaddr_t initarm(void *);

Missed in previous commit.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/aarch64/include

2019-07-16 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jul 16 16:18:56 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: machdep.h

Log Message:
Add vaddr_t initarm(void *);

Missed in previous commit.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/machdep.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/machdep.h
diff -u src/sys/arch/aarch64/include/machdep.h:1.7 src/sys/arch/aarch64/include/machdep.h:1.8
--- src/sys/arch/aarch64/include/machdep.h:1.7	Sat Apr  6 03:06:24 2019
+++ src/sys/arch/aarch64/include/machdep.h	Tue Jul 16 16:18:56 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.h,v 1.7 2019/04/06 03:06:24 thorpej Exp $	*/
+/*	$NetBSD: machdep.h,v 1.8 2019/07/16 16:18:56 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu 
@@ -70,6 +70,12 @@ extern char *booted_kernel;
 extern u_int arm_cpu_max;
 #endif
 
+/*
+ * note that we use void * as all the platforms have different ideas on what
+ * the structure is
+ */
+vaddr_t initarm(void *);
+
 vaddr_t initarm_common(vaddr_t, vsize_t, const struct boot_physmem *, size_t);
 void cpu_kernel_vm_init(paddr_t, psize_t);
 void uartputc(int);



CVS commit: src/sys/arch/aarch64/include

2019-06-16 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Jun 16 15:16:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h

Log Message:
Provide icc_pmr_read


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/armreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.24 src/sys/arch/aarch64/include/armreg.h:1.25
--- src/sys/arch/aarch64/include/armreg.h:1.24	Wed Mar 20 07:16:07 2019
+++ src/sys/arch/aarch64/include/armreg.h	Sun Jun 16 15:16:15 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.24 2019/03/20 07:16:07 ryo Exp $ */
+/* $NetBSD: armreg.h,v 1.25 2019/06/16 15:16:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -1056,6 +1056,7 @@ AARCH64REG_READ_INLINE2(icc_iar1_el1, s3
 
 #define	icc_sre_read		reg_icc_sre_el1_read
 #define	icc_sre_write		reg_icc_sre_el1_write
+#define	icc_pmr_read		reg_icc_pmr_el1_read
 #define	icc_pmr_write		reg_icc_pmr_el1_write
 #define	icc_bpr0_write		reg_icc_bpr0_el1_write
 #define	icc_bpr1_write		reg_icc_bpr1_el1_write



CVS commit: src/sys/arch/aarch64/include

2019-06-16 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sun Jun 16 15:16:15 UTC 2019

Modified Files:
src/sys/arch/aarch64/include: armreg.h

Log Message:
Provide icc_pmr_read


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/include/armreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



re: CVS commit: src/sys/arch/aarch64/include

2018-11-21 Thread matthew green
"Jaromir Dolecek" writes:
> Module Name:  src
> Committed By: jdolecek
> Date: Tue Nov 20 20:53:50 UTC 2018
> 
> Modified Files:
>   src/sys/arch/aarch64/include: pmap.h
> 
> Log Message:
> Implement PMAP_DIRECT / pmap_direct_process() in support of experimental
> UBC optimizations (compile-tested only for now)
> 
> PR kern/53124

can we please not commit *untested* pmap changes.  espcially
when this port is actively maintained and you could very
easily ask someone to test this specific change.

compile testing kernel changes is really bad.  compile testing
memory management code is pretty much forbidden.


.mrg.


Re: CVS commit: src/sys/arch/aarch64/include

2018-07-17 Thread Christos Zoulas
In article <2018071711.5b119f...@cvs.netbsd.org>,
Joerg Sonnenberger  wrote:
>-=-=-=-=-=-
>
>Module Name:   src
>Committed By:  joerg
>Date:  Tue Jul 17 11:55:55 UTC 2018
>
>Modified Files:
>   src/sys/arch/aarch64/include: types.h
>
>Log Message:
>Be consistent and explicitly size register32_t too.

The reason I did not do that (I don't disagree with the change though)
is that in reg.h they are declared as unsigned int, not __uint32_t.

christos