CVS commit: src/sys/arch/arm/cortex

2019-09-05 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Thu Sep 5 13:33:11 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: - Use pic_do_pending_ints in intr handler - Sprinkle isb - Fix PMR bits detection on eMAG, from OpenBSD To generate a diff of this

CVS commit: src/sys/arch/arm/cortex

2019-09-05 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Thu Sep 5 13:33:11 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: - Use pic_do_pending_ints in intr handler - Sprinkle isb - Fix PMR bits detection on eMAG, from OpenBSD To generate a diff of this

CVS commit: src/sys/arch/arm/cortex

2019-08-14 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Wed Aug 14 09:20:00 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9ptmr.c Log Message: Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks

CVS commit: src/sys/arch/arm/cortex

2019-08-14 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Wed Aug 14 09:20:00 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9ptmr.c Log Message: Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks

CVS commit: src/sys/arch/arm/cortex

2019-08-10 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Sat Aug 10 16:50:24 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: spaces to tab To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c Please note that diffs are not

CVS commit: src/sys/arch/arm/cortex

2019-08-10 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Sat Aug 10 16:50:24 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: spaces to tab To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c Please note that diffs are not

CVS commit: src/sys/arch/arm/cortex

2019-07-30 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Tue Jul 30 06:57:02 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: Fix loop to calculate prescaler divisor. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c

CVS commit: src/sys/arch/arm/cortex

2019-07-30 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Tue Jul 30 06:57:02 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: Fix loop to calculate prescaler divisor. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c

CVS commit: src/sys/arch/arm/cortex

2019-07-27 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Sat Jul 27 07:02:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h Log Message: Rename a register define to make it more obvious it's watchdog only To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2

CVS commit: src/sys/arch/arm/cortex

2019-07-27 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Sat Jul 27 07:02:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h Log Message: Rename a register define to make it more obvious it's watchdog only To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 17:33:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Cleanup ThunderX quirk and print cache / shareability details for ITT tables To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 17:33:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Cleanup ThunderX quirk and print cache / shareability details for ITT tables To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 11:11:38 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Fix size of LPI pending table allocation and enable caching of LPI conf and pending tables where possible. To generate a diff

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 11:11:38 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Fix size of LPI pending table allocation and enable caching of LPI conf and pending tables where possible. To generate a diff

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 10:10:20 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Enable caching of ITS tables when possible To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 30 10:10:20 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Enable caching of ITS tables when possible To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20

CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Jun 29 16:48:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Restore original size calculation for MAPD and don't disable MSI/MSIX on devices before making changes To generate a diff of this

CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Jun 29 16:48:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Restore original size calculation for MAPD and don't disable MSI/MSIX on devices before making changes To generate a diff of this

CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Jun 29 13:30:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Rename lpi pic to gicv3-its when an ITS is found To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18

CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Jun 29 13:30:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Rename lpi pic to gicv3-its when an ITS is found To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18

CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:10:42 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.h Log Message: Remove unused field To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h Please note that

CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:10:42 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.h Log Message: Remove unused field To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h Please note that

CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:00:10 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Change how we detect secure vs non-secure access. Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented, then do the

CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:00:10 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Change how we detect secure vs non-secure access. Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented, then do the

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:19:51 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct EventID to MOVI and INV commands To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:19:51 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct EventID to MOVI and INV commands To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:04:52 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Remove unused variable (build fix) To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:04:52 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Remove unused variable (build fix) To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:03:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Ensure that the "size" parameter of MAPD matches the size of the ITT being mapped and subtract the LPI base from EventID. Fixes

CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:03:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Ensure that the "size" parameter of MAPD matches the size of the ITT being mapped and subtract the LPI base from EventID. Fixes

CVS commit: src/sys/arch/arm/cortex

2019-06-17 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Mon Jun 17 10:15:08 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Improve priority handling for cases where access is secure, from OpenBSD. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/arm/cortex

2019-06-17 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Mon Jun 17 10:15:08 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Improve priority handling for cases where access is secure, from OpenBSD. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Mon Jun 17 00:49:55 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Mon Jun 17 00:49:55 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 19:19:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct event ID with MOVI commands To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 19:19:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct event ID with MOVI commands To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 11:05:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 11:05:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 10:57:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Disable counter before updating cval/tval To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Jun 16 10:57:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Disable counter before updating cval/tval To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 21:02:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Allow set_affinity calls before PEs are brought online. We store the desired target PE if set_affinity is called early

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 21:02:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Allow set_affinity calls before PEs are brought online. We store the desired target PE if set_affinity is called early

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread matthew green
Module Name:src Committed By: mrg Date: Wed Jun 12 11:35:18 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: revert rev 1.4: >Adjust priority mappings, NFCI it has some unintended change that makes nvme hangy. ok @jmcneill. To generate a diff of

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread matthew green
Module Name:src Committed By: mrg Date: Wed Jun 12 11:35:18 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: revert rev 1.4: >Adjust priority mappings, NFCI it has some unintended change that makes nvme hangy. ok @jmcneill. To generate a diff of

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:27:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Revert "Route all interrupts to the primary PE by default" To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:27:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Revert "Route all interrupts to the primary PE by default" To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:03:28 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Route all interrupts to the primary PE by default To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:03:28 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Route all interrupts to the primary PE by default To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:02:17 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Adjust priority mappings, NFCI To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c Please

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:02:17 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Adjust priority mappings, NFCI To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c Please

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:00:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Fail gracefully if gicv3_its_set_affinity is called before a cpu is brought online. To generate a diff of this commit:

CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:00:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Fail gracefully if gicv3_its_set_affinity is called before a cpu is brought online. To generate a diff of this commit:

CVS commit: src/sys/arch/arm/cortex

2019-06-11 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Tue Jun 11 12:48:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c Please note that diffs

CVS commit: src/sys/arch/arm/cortex

2019-06-11 Thread Nick Hudson
Module Name:src Committed By: skrll Date: Tue Jun 11 12:48:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c Please note that diffs