CVS commit: src/sys/arch/arm/cortex

2019-09-05 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Thu Sep  5 13:33:11 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
- Use pic_do_pending_ints in intr handler
- Sprinkle isb
- Fix PMR bits detection on eMAG, from OpenBSD


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-09-05 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Thu Sep  5 13:33:11 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
- Use pic_do_pending_ints in intr handler
- Sprinkle isb
- Fix PMR bits detection on eMAG, from OpenBSD


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.20 src/sys/arch/arm/cortex/gicv3.c:1.21
--- src/sys/arch/arm/cortex/gicv3.c:1.20	Sun Jun 30 11:11:38 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Thu Sep  5 13:33:11 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $");
 
 #include 
 #include 
@@ -213,6 +213,7 @@ gicv3_set_priority(struct pic_softc *pic
 	struct gicv3_softc * const sc = PICTOSOFTC(pic);
 
 	icc_pmr_write(IPL_TO_PMR(sc, ipl));
+	arm_isb();
 }
 
 static void
@@ -437,14 +438,17 @@ gicv3_ipi_send(struct pic_softc *pic, co
 			if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
 if (targets != 0) {
 	icc_sgi1r_write(intid | aff | targets);
+	arm_isb();
 	targets = 0;
 }
 aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff);
 			}
 			targets |= (ci->ci_gic_sgir & ICC_SGIR_EL1_TargetList);
 		}
-		if (targets != 0)
+		if (targets != 0) {
 			icc_sgi1r_write(intid | aff | targets);
+			arm_isb();
+		}
 	}
 }
 
@@ -715,6 +719,7 @@ gicv3_irq_handler(void *frame)
 
 	for (;;) {
 		const uint32_t iar = icc_iar1_read();
+		arm_dsb();
 		const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID);
 		if (irq == ICC_IAR_INTID_SPURIOUS)
 			break;
@@ -726,26 +731,39 @@ gicv3_irq_handler(void *frame)
 		struct intrsource * const is = pic->pic_sources[irq - pic->pic_irqbase];
 		KASSERT(is != NULL);
 
+		const bool early_eoi = irq < GIC_LPI_BASE && is->is_type == IST_EDGE;
+
 		const int ipl = is->is_ipl;
-		if (ci->ci_cpl < ipl)
-			pic_set_priority(ci, ipl);
+		if (__predict_false(ipl < ci->ci_cpl)) {
+			pic_do_pending_ints(I32_bit, ipl, frame);
+		} else {
+			gicv3_set_priority(pic, ipl);
+			ci->ci_cpl = ipl;
+		}
+
+		if (early_eoi) {
+			icc_eoi1r_write(iar);
+			arm_isb();
+		}
 
 		cpsie(I32_bit);
 		pic_dispatch(is, frame);
 		cpsid(I32_bit);
 
-		icc_eoi1r_write(iar);
+		if (!early_eoi) {
+			icc_eoi1r_write(iar);
+			arm_isb();
+		}
 	}
 
-	if (ci->ci_cpl != oldipl)
-		pic_set_priority(ci, oldipl);
+	pic_do_pending_ints(I32_bit, oldipl, frame);
 }
 
 static int
 gicv3_detect_pmr_bits(struct gicv3_softc *sc)
 {
 	const uint32_t opmr = icc_pmr_read();
-	icc_pmr_write(0xff);
+	icc_pmr_write(0xbf);
 	const uint32_t npmr = icc_pmr_read();
 	icc_pmr_write(opmr);
 



CVS commit: src/sys/arch/arm/cortex

2019-08-14 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Aug 14 09:20:00 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c

Log Message:
Various fixes / changes

- don't use prescaler
- improve AB_DEBUG output
- fix a9ptmr_delay to work with a decrementing counter!

Thanks to jmcneill@ for proving I'm an idiot


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9ptmr.c
diff -u src/sys/arch/arm/cortex/a9ptmr.c:1.1 src/sys/arch/arm/cortex/a9ptmr.c:1.2
--- src/sys/arch/arm/cortex/a9ptmr.c:1.1	Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr.c	Wed Aug 14 09:20:00 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $	*/
+/*	$NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $");
 
 #include 
 #include 
@@ -144,6 +144,7 @@ a9ptmr_attach(device_t parent, device_t 
 	sc->sc_ctl = a9ptmr_read(sc, TMR_CTL);
 
 	sc->sc_prescaler = 1;
+#if 0
 	/*
 	 * Let's hope the timer frequency isn't prime.
 	 */
@@ -154,14 +155,17 @@ a9ptmr_attach(device_t parent, device_t 
 		}
 	}
 	sc->sc_freq /= sc->sc_prescaler;
+#endif
 
-	aprint_debug_dev(sc->sc_dev, ": freq %d prescaler %d", sc->sc_freq,
+	aprint_debug(": freq %d prescaler %d", sc->sc_freq,
 	sc->sc_prescaler);
 	sc->sc_ctl = TMR_CTL_INT_ENABLE | TMR_CTL_AUTO_RELOAD | TMR_CTL_ENABLE;
 	sc->sc_ctl |= __SHIFTIN(sc->sc_prescaler - 1, TMR_CTL_PRESCALER);
 
 	sc->sc_load = (sc->sc_freq / hz) - 1;
 
+	aprint_debug(": load %d ", sc->sc_load);
+
 	a9ptmr_init_cpu_clock(curcpu());
 
 	aprint_naive("\n");
@@ -188,7 +192,6 @@ a9ptmr_delay(unsigned int n)
 	curcpu()->ci_data.cpu_cc_freq / 2;
 	KASSERT(freq != 0);
 
-
 	const uint64_t counts_per_usec = freq / 100;
 	uint32_t delta, usecs, last, curr;
 
@@ -200,11 +203,11 @@ a9ptmr_delay(unsigned int n)
 	while (n > usecs) {
 		curr = a9ptmr_read(sc, TMR_CTR);
 
-		/* Check to see if the timer has wrapped around. */
-		if (curr < last)
-			delta += curr + (sc->sc_load - last);
+		/* Check to see if the timer has reloaded. */
+		if (curr > last)
+			delta += (sc->sc_load - curr) + last;
 		else
-			delta += curr - last;
+			delta += last - curr;
 
 		last = curr;
 



CVS commit: src/sys/arch/arm/cortex

2019-08-14 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Wed Aug 14 09:20:00 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c

Log Message:
Various fixes / changes

- don't use prescaler
- improve AB_DEBUG output
- fix a9ptmr_delay to work with a decrementing counter!

Thanks to jmcneill@ for proving I'm an idiot


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:50:24 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9wdt.c

Log Message:
spaces to tab


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.8 src/sys/arch/arm/cortex/a9wdt.c:1.9
--- src/sys/arch/arm/cortex/a9wdt.c:1.8	Tue Jul 30 06:57:02 2019
+++ src/sys/arch/arm/cortex/a9wdt.c	Sat Aug 10 16:50:23 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $	*/
+/*	$NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $");
 
 #include 
 #include 
@@ -183,7 +183,7 @@ a9wdt_setmode(struct sysmon_wdog *smw)
 static void
 a9wdt_attach(device_t parent, device_t self, void *aux)
 {
-struct a9wdt_softc * const sc = device_private(self);
+	struct a9wdt_softc * const sc = device_private(self);
 	struct mpcore_attach_args * const mpcaa = aux;
 	prop_dictionary_t dict = device_properties(self);
 	const char *cpu_type;



CVS commit: src/sys/arch/arm/cortex

2019-08-10 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Aug 10 16:50:24 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9wdt.c

Log Message:
spaces to tab


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-07-30 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jul 30 06:57:02 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9wdt.c

Log Message:
Fix loop to calculate prescaler divisor.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-07-30 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jul 30 06:57:02 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9wdt.c

Log Message:
Fix loop to calculate prescaler divisor.


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.7 src/sys/arch/arm/cortex/a9wdt.c:1.8
--- src/sys/arch/arm/cortex/a9wdt.c:1.7	Fri Dec 29 11:07:03 2017
+++ src/sys/arch/arm/cortex/a9wdt.c	Tue Jul 30 06:57:02 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $	*/
+/*	$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $");
 
 #include 
 #include 
@@ -214,7 +214,7 @@ a9wdt_attach(device_t parent, device_t s
 		/*
 		 * Let's hope the timer frequency isn't prime.
 		 */
-		for (size_t div = 256; div >= 2; div++) {
+		for (size_t div = 256; div >= 2; div--) {
 			if (sc->sc_freq % div == 0) {
 sc->sc_wdog_prescaler = div;
 break;



CVS commit: src/sys/arch/arm/cortex

2019-07-27 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Jul 27 07:02:09 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h

Log Message:
Rename a register define to make it more obvious it's watchdog only


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9tmr_reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9tmr_reg.h
diff -u src/sys/arch/arm/cortex/a9tmr_reg.h:1.1 src/sys/arch/arm/cortex/a9tmr_reg.h:1.2
--- src/sys/arch/arm/cortex/a9tmr_reg.h:1.1	Sat Sep  1 00:03:14 2012
+++ src/sys/arch/arm/cortex/a9tmr_reg.h	Sat Jul 27 07:02:09 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9tmr_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $	*/
+/*	$NetBSD: a9tmr_reg.h,v 1.2 2019/07/27 07:02:09 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -57,7 +57,7 @@
 #define	TMR_CTR			0x0004	// Timer Counter Register
 #define	TMR_CTL			0x0008	// Timer Control Register
 #define	TMR_INT			0x000C	// Timer Interrupt Status
-#define	TMR_RST			0x0010  // Timer Reset Status (WDOG only)
+#define	TMR_WDOGRST		0x0010  // Timer Reset Status (WDOG only)
 #define	TMR_WDOGDIS		0x0014  // [WO] Timer Disable (WDOG only)
 
 #define	TMR_CTL_PRESCALER	__BITS(15,8)



CVS commit: src/sys/arch/arm/cortex

2019-07-27 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Sat Jul 27 07:02:09 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h

Log Message:
Rename a register define to make it more obvious it's watchdog only


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9tmr_reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 17:33:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Cleanup ThunderX quirk and print cache / shareability details for ITT tables


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.20 src/sys/arch/arm/cortex/gicv3_its.c:1.21
--- src/sys/arch/arm/cortex/gicv3_its.c:1.20	Sun Jun 30 10:10:19 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 30 17:33:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $");
 
 #include 
 #include 
@@ -61,7 +61,29 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
  */
 #define GITS_IIDR_PID_CAVIUM_THUNDERX	0xa1
 #define GITS_IIDR_IMP_CAVIUM		0x34c
-
+#define	GITS_IIDR_CAVIUM_ERRATA_MASK	(GITS_IIDR_Implementor|GITS_IIDR_ProductID|GITS_IIDR_Variant)
+#define	GITS_IIDR_CAVIUM_ERRATA_VALUE			\
+		(__SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) |		\
+		 __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) |	\
+		 __SHIFTIN(0, GITS_IIDR_Variant))
+
+static const char * gits_cache_type[] = {
+	[GITS_Cache_DEVICE_nGnRnE]	= "Device-nGnRnE",
+	[GITS_Cache_NORMAL_NC]		= "Non-cacheable",
+	[GITS_Cache_NORMAL_RA_WT]	= "Cacheable RA WT",
+	[GITS_Cache_NORMAL_RA_WB]	= "Cacheable RA WB",
+	[GITS_Cache_NORMAL_WA_WT]	= "Cacheable WA WT",
+	[GITS_Cache_NORMAL_WA_WB]	= "Cacheable WA WB",
+	[GITS_Cache_NORMAL_RA_WA_WT]	= "Cacheable RA WA WT",
+	[GITS_Cache_NORMAL_RA_WA_WB]	= "Cacheable RA WA WB",
+};
+
+static const char * gits_share_type[] = {
+	[GITS_Shareability_NS]		= "Non-shareable",
+	[GITS_Shareability_IS]		= "Inner shareable",
+	[GITS_Shareability_OS]		= "Outer shareable",
+	[3]= "(Reserved)",
+};
 
 static inline uint32_t
 gits_read_4(struct gicv3_its *its, bus_size_t reg)
@@ -617,34 +639,36 @@ gicv3_its_command_init(struct gicv3_soft
 }
 
 static void
-gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its)
+gicv3_its_table_params(struct gicv3_softc *sc, struct gicv3_its *its,
+u_int *devbits, u_int *innercache, u_int *share)
 {
-	u_int table_size, page_size, table_align;
-	uint64_t baser;
-	int tab;
 
 	const uint64_t typer = gits_read_8(its, GITS_TYPER);
+	const uint32_t iidr = gits_read_4(its, GITS_IIDR);
 
-	/* devbits and innercache defaults */
-	u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
-	u_int innercache = GITS_Cache_NORMAL_WA_WB;
-	u_int share = GITS_Shareability_IS;
-
-	uint32_t iidr = gits_read_4(its, GITS_IIDR);
-	const uint32_t ctx =
-	   __SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) |
-	   __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) |
-	   __SHIFTIN(0, GITS_IIDR_Variant);
-	const uint32_t mask =
-	GITS_IIDR_Implementor |
-	GITS_IIDR_ProductID |
-	GITS_IIDR_Variant;
-
-	if ((iidr & mask) == ctx) {
-		devbits = 20;		/* 8Mb */
-		innercache = GITS_Cache_DEVICE_nGnRnE;
+	/* Default values */
+	*devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+	*innercache = GITS_Cache_NORMAL_WA_WB;
+	*share = GITS_Shareability_IS;
+
+	/* Cavium ThunderX errata */
+	if ((iidr & GITS_IIDR_CAVIUM_ERRATA_MASK) == GITS_IIDR_CAVIUM_ERRATA_VALUE) {
+		*devbits = 20;		/* 8Mb */
+		*innercache = GITS_Cache_DEVICE_nGnRnE;
 		aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n");
 	}
+}
+
+static void
+gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its)
+{
+	u_int table_size, page_size, table_align;
+	u_int devbits, innercache, share;
+	const char *table_type;
+	uint64_t baser;
+	int tab;
+
+	gicv3_its_table_params(sc, its, , , );
 
 	for (tab = 0; tab < 8; tab++) {
 		baser = gits_read_8(its, GITS_BASERn(tab));
@@ -673,12 +697,14 @@ gicv3_its_table_init(struct gicv3_softc 
 			 * Table size scales with the width of the DeviceID.
 			 */
 			table_size = roundup(entry_size * (1 << devbits), page_size);
+			table_type = "Devices";
 			break;
 		case GITS_Type_InterruptCollections:
 			/*
 			 * Allocate space for one interrupt collection per CPU.
 			 */
 			table_size = roundup(entry_size * MAXCPUS, page_size);
+			table_type = "Collections";
 			break;
 		default:
 			table_size = 0;
@@ -688,7 +714,6 @@ gicv3_its_table_init(struct gicv3_softc 
 		if (table_size == 0)
 			continue;
 
-		aprint_normal_dev(sc->sc_dev, "ITS TT%u type %#x size %#x\n", tab, (u_int)__SHIFTOUT(baser, GITS_BASER_Type), table_size);
 		

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 17:33:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Cleanup ThunderX quirk and print cache / shareability details for ITT tables


To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 11:11:38 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h

Log Message:
Fix size of LPI pending table allocation and enable caching of LPI conf
and pending tables where possible.


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.19 src/sys/arch/arm/cortex/gicv3.c:1.20
--- src/sys/arch/arm/cortex/gicv3.c:1.19	Wed Jun 26 23:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Sun Jun 30 11:11:38 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $");
 
 #include 
 #include 
@@ -41,6 +41,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 
@@ -516,10 +518,13 @@ gicv3_lpi_unblock_irqs(struct pic_softc 
 
 	while ((bit = ffs(mask)) != 0) {
 		sc->sc_lpiconf.base[irqbase + bit - 1] |= GIC_LPICONF_Enable;
+		if (sc->sc_lpiconf_flush)
+			cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
 		mask &= ~__BIT(bit - 1);
 	}
 
-	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, irqbase, 32, BUS_DMASYNC_PREWRITE);
+	if (!sc->sc_lpiconf_flush)
+		__asm __volatile ("dsb ishst");
 }
 
 static void
@@ -530,10 +535,13 @@ gicv3_lpi_block_irqs(struct pic_softc *p
 
 	while ((bit = ffs(mask)) != 0) {
 		sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable;
+		if (sc->sc_lpiconf_flush)
+			cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
 		mask &= ~__BIT(bit - 1);
 	}
 
-	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, irqbase, 32, BUS_DMASYNC_PREWRITE);
+	if (!sc->sc_lpiconf_flush)
+		__asm __volatile ("dsb ishst");
 }
 
 static void
@@ -543,7 +551,10 @@ gicv3_lpi_establish_irq(struct pic_softc
 
 	sc->sc_lpiconf.base[is->is_irq] = IPL_TO_LPIPRIO(sc, is->is_ipl) | GIC_LPICONF_Res1;
 
-	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
+	if (sc->sc_lpiconf_flush)
+		cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[is->is_irq], 1);
+	else
+		__asm __volatile ("dsb ishst");
 }
 
 static void
@@ -551,6 +562,7 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
 {
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 	struct gicv3_lpi_callback *cb;
+	uint64_t propbase, pendbase;
 	uint32_t ctlr;
 
 	/* If physical LPIs are not supported on this redistributor, just return. */
@@ -568,18 +580,36 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
 	arm_dsb();
 
 	/* Setup the LPI configuration table */
-	const uint64_t propbase = sc->sc_lpiconf.segs[0].ds_addr |
+	propbase = sc->sc_lpiconf.segs[0].ds_addr |
 	__SHIFTIN(ffs(pic->pic_maxsources) - 1, GICR_PROPBASER_IDbits) |
-	__SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability) |
-	__SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache);
+	__SHIFTIN(GICR_Shareability_IS, GICR_PROPBASER_Shareability) |
+	__SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PROPBASER_InnerCache);
 	gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase);
+	propbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PROPBASER);
+	if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) != GICR_Shareability_IS) {
+		if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) == GICR_Shareability_NS) {
+			propbase &= ~GICR_PROPBASER_Shareability;
+			propbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability);
+			propbase &= ~GICR_PROPBASER_InnerCache;
+			propbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache);
+			gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase);
+		}
+		sc->sc_lpiconf_flush = true;
+	}
 
 	/* Setup the LPI pending table */
-	const uint64_t pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr |
-	__SHIFTIN(GICR_Shareability_NS, GICR_PENDBASER_Shareability) |
-	__SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PENDBASER_InnerCache) |
-	GICR_PENDBASER_PTZ;
+	pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr |
+	__SHIFTIN(GICR_Shareability_IS, GICR_PENDBASER_Shareability) |
+	__SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PENDBASER_InnerCache);
 	gicr_write_8(sc, ci->ci_gic_redist, GICR_PENDBASER, pendbase);
+	pendbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PENDBASER);
+	if (__SHIFTOUT(pendbase, GICR_PENDBASER_Shareability) == GICR_Shareability_NS) {
+		pendbase &= ~GICR_PENDBASER_Shareability;
+		pendbase |= __SHIFTIN(GICR_Shareability_NS, 

CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 11:11:38 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h

Log Message:
Fix size of LPI pending table allocation and enable caching of LPI conf
and pending tables where possible.


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 10:10:20 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Enable caching of ITS tables when possible


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.19 src/sys/arch/arm/cortex/gicv3_its.c:1.20
--- src/sys/arch/arm/cortex/gicv3_its.c:1.19	Sat Jun 29 16:48:07 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 30 10:10:19 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $");
 
 #include 
 #include 
@@ -627,7 +627,8 @@ gicv3_its_table_init(struct gicv3_softc 
 
 	/* devbits and innercache defaults */
 	u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
-	u_int innercache = GITS_Cache_NORMAL_NC;
+	u_int innercache = GITS_Cache_NORMAL_WA_WB;
+	u_int share = GITS_Shareability_IS;
 
 	uint32_t iidr = gits_read_4(its, GITS_IIDR);
 	const uint32_t ctx =
@@ -697,10 +698,18 @@ gicv3_its_table_init(struct gicv3_softc 
 		baser &= ~GITS_BASER_InnerCache;
 		baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache);
 		baser &= ~GITS_BASER_Shareability;
-		baser |= __SHIFTIN(GITS_Shareability_NS, GITS_BASER_Shareability);
+		baser |= __SHIFTIN(share, GITS_BASER_Shareability);
 		baser |= GITS_BASER_Valid;
 
 		gits_write_8(its, GITS_BASERn(tab), baser);
+
+		baser = gits_read_8(its, GITS_BASERn(tab));
+		if (__SHIFTOUT(baser, GITS_BASER_Shareability) == GITS_Shareability_NS) {
+			baser &= ~GITS_BASER_InnerCache;
+			baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache);
+
+			gits_write_8(its, GITS_BASERn(tab), baser);
+		}
 	}
 }
 



CVS commit: src/sys/arch/arm/cortex

2019-06-30 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 30 10:10:20 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Enable caching of ITS tables when possible


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sat Jun 29 16:48:07 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Restore original size calculation for MAPD and don't disable MSI/MSIX on 
devices before making changes


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.18 src/sys/arch/arm/cortex/gicv3_its.c:1.19
--- src/sys/arch/arm/cortex/gicv3_its.c:1.18	Sat Jun 29 13:30:59 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sat Jun 29 16:48:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $");
 
 #include 
 #include 
@@ -329,8 +329,8 @@ gicv3_its_device_map(struct gicv3_its *i
 	/*
 	 * Map the device to the ITT
 	 */
-	const u_int size = ilog2(vectors) - 1;
-	gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, size, true);
+	const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
+	gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
 	gits_wait(its);
 
 	return 0;
@@ -349,10 +349,6 @@ gicv3_its_msi_enable(struct gicv3_its *i
 		panic("gicv3_its_msi_enable: device is not MSI-capable");
 
 	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
-	ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
-	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
-
-	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
 	ctl &= ~PCI_MSI_CTL_MME_MASK;
 	ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
 	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
@@ -406,10 +402,6 @@ gicv3_its_msix_enable(struct gicv3_its *
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL))
 		panic("gicv3_its_msix_enable: device is not MSI-X-capable");
 
-	ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
-	ctl &= ~PCI_MSIX_CTL_ENABLE;
-	pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
-
 	const uint64_t addr = its->its_base + GITS_TRANSLATER;
 	const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);



CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sat Jun 29 16:48:07 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Restore original size calculation for MAPD and don't disable MSI/MSIX on 
devices before making changes


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sat Jun 29 13:30:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Rename lpi pic to gicv3-its when an ITS is found


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-29 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sat Jun 29 13:30:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Rename lpi pic to gicv3-its when an ITS is found


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.17 src/sys/arch/arm/cortex/gicv3_its.c:1.18
--- src/sys/arch/arm/cortex/gicv3_its.c:1.17	Sun Jun 23 16:19:51 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sat Jun 29 13:30:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $");
 
 #include 
 #include 
@@ -821,6 +821,7 @@ gicv3_its_init(struct gicv3_softc *sc, b
 	its->its_dmat = sc->sc_dmat;
 	its->its_base = its_base;
 	its->its_pic = >sc_lpi;
+	snprintf(its->its_pic->pic_name, sizeof(its->its_pic->pic_name), "gicv3-its");
 	KASSERT(its->its_pic->pic_maxsources > 0);
 	its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP);
 	its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP);



CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 26 23:10:42 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.h

Log Message:
Remove unused field


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 26 23:10:42 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.h

Log Message:
Remove unused field


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.5 src/sys/arch/arm/cortex/gicv3.h:1.6
--- src/sys/arch/arm/cortex/gicv3.h:1.5	Mon Jun 17 10:15:08 2019
+++ src/sys/arch/arm/cortex/gicv3.h	Wed Jun 26 23:10:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.5 2019/06/17 10:15:08 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.6 2019/06/26 23:10:42 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -60,9 +60,6 @@ struct gicv3_softc {
 	bus_space_handle_t	*sc_bsh_r;	/* GICR */
 	u_int			sc_bsh_r_count;
 
-	u_int			sc_flags;
-#define	GICV3_F_SECURE		0x01
-
 	u_int			sc_priority_shift;
 	u_int			sc_pmr_shift;
 



CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 26 23:00:10 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Change how we detect secure vs non-secure access.

Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented,
then do the same with a GICD_IPRIORITYR priority value field.

If the values differ, assume we have a shifted view of IPRIORITYR.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-26 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 26 23:00:10 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Change how we detect secure vs non-secure access.

Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented,
then do the same with a GICD_IPRIORITYR priority value field.

If the values differ, assume we have a shifted view of IPRIORITYR.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.18 src/sys/arch/arm/cortex/gicv3.c:1.19
--- src/sys/arch/arm/cortex/gicv3.c:1.18	Mon Jun 17 10:15:08 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Wed Jun 26 23:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $");
 
 #include 
 #include 
@@ -249,9 +249,7 @@ gicv3_dist_enable(struct gicv3_softc *sc
 		;
 
 	/* Enable Affinity routing and G1NS interrupts */
-	gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
-	if (ISSET(sc->sc_flags, GICV3_F_SECURE))
-		gicd_ctrl = (gicd_ctrl & ~GICD_CTRL_EnableGrp1A) << 1;
+	gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_ARE_NS;
 	gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
 }
 
@@ -713,6 +711,28 @@ gicv3_irq_handler(void *frame)
 		pic_set_priority(ci, oldipl);
 }
 
+static int
+gicv3_detect_pmr_bits(struct gicv3_softc *sc)
+{
+	const uint32_t opmr = icc_pmr_read();
+	icc_pmr_write(0xff);
+	const uint32_t npmr = icc_pmr_read();
+	icc_pmr_write(opmr);
+
+	return NBBY - (ffs(npmr) - 1);
+}
+
+static int
+gicv3_detect_ipriority_bits(struct gicv3_softc *sc)
+{
+	const uint32_t oipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
+	gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr | 0xff);
+	const uint32_t nipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
+	gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr);
+
+	return NBBY - (ffs(nipriorityr & 0xff) - 1);
+}
+
 int
 gicv3_init(struct gicv3_softc *sc)
 {
@@ -728,27 +748,21 @@ gicv3_init(struct gicv3_softc *sc)
 		sc->sc_irouter[n] = UINT64_MAX;
 
 	sc->sc_priority_shift = 4;
-	const uint32_t oldnsacr = gicd_read_4(sc, GICD_NSACRn(2));
-	gicd_write_4(sc, GICD_NSACRn(2), oldnsacr ^ 0x);
-	if (gicd_read_4(sc, GICD_NSACRn(2)) != oldnsacr) {
-		gicd_write_4(sc, GICD_NSACRn(2), oldnsacr);
-		sc->sc_priority_shift--;
-		SET(sc->sc_flags, GICV3_F_SECURE);
-	}
-	aprint_verbose_dev(sc->sc_dev, "access is %ssecure\n",
-	ISSET(sc->sc_flags, GICV3_F_SECURE) ? "" : "in");
-
 	sc->sc_pmr_shift = 4;
+
 	if ((gicd_ctrl & GICD_CTRL_DS) == 0) {
-		const uint32_t icc_ctlr = icc_ctlr_read();
-		const u_int nbits = __SHIFTOUT(icc_ctlr, ICC_CTLR_EL1_PRIbits) + 1;
-		const u_int oldpmr = icc_pmr_read();
-		icc_pmr_write(0xff);
-		const u_int pmr = icc_pmr_read();
-		icc_pmr_write(oldpmr);
-		if (nbits == 8 - (ffs(pmr) - 1))
-			sc->sc_pmr_shift--;
+		const int pmr_bits = gicv3_detect_pmr_bits(sc);
+		const int ipriority_bits = gicv3_detect_ipriority_bits(sc);
+
+		if (ipriority_bits != pmr_bits)
+			--sc->sc_priority_shift;
+
+		aprint_verbose_dev(sc->sc_dev, "%d pmr bits, %d ipriority bits\n",
+		pmr_bits, ipriority_bits);
+	} else {
+		aprint_verbose_dev(sc->sc_dev, "security disabled\n");
 	}
+
 	aprint_verbose_dev(sc->sc_dev, "priority shift %d, pmr shift %d\n",
 	sc->sc_priority_shift, sc->sc_pmr_shift);
 



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:19:51 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Pass correct EventID to MOVI and INV commands


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:19:51 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Pass correct EventID to MOVI and INV commands


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.16 src/sys/arch/arm/cortex/gicv3_its.c:1.17
--- src/sys/arch/arm/cortex/gicv3_its.c:1.16	Sun Jun 23 16:04:52 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 23 16:19:51 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $");
 
 #include 
 #include 
@@ -579,7 +579,7 @@ gicv3_its_msi_intr_establish(struct arm_
 	pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
 	KASSERT(pa != NULL);
 	const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-	gits_command_inv(its, devid, lpi);
+	gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase);
 
 	return intrh;
 }
@@ -757,7 +757,7 @@ gicv3_its_cpu_init(void *priv, struct cp
 		KASSERT(pa != NULL);
 
 		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-		gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
+		gits_command_movi(its, devid, irq, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 
@@ -796,7 +796,7 @@ gicv3_its_set_affinity(void *priv, size_
 
 	if (its->its_cpuonline[cpu_index(ci)] == true) {
 		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-		gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
+		gits_command_movi(its, devid, irq, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:04:52 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Remove unused variable (build fix)


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.15 src/sys/arch/arm/cortex/gicv3_its.c:1.16
--- src/sys/arch/arm/cortex/gicv3_its.c:1.15	Sun Jun 23 16:03:30 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 23 16:04:52 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $");
 
 #include 
 #include 
@@ -312,7 +312,6 @@ gicv3_its_device_map(struct gicv3_its *i
 		vectors++;
 
 	const uint64_t typer = gits_read_8(its, GITS_TYPER);
-	const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
 	const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1;
 	const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN);
 



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:04:52 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Remove unused variable (build fix)


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:03:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Ensure that the "size" parameter of MAPD matches the size of the ITT being
mapped and subtract the LPI base from EventID. Fixes multi-vector MSI/MSI-X
on RK3399.


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-23 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 23 16:03:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Ensure that the "size" parameter of MAPD matches the size of the ITT being
mapped and subtract the LPI base from EventID. Fixes multi-vector MSI/MSI-X
on RK3399.


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.14 src/sys/arch/arm/cortex/gicv3_its.c:1.15
--- src/sys/arch/arm/cortex/gicv3_its.c:1.14	Sun Jun 16 19:19:30 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 23 16:03:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $");
 
 #include 
 #include 
@@ -148,16 +148,17 @@ gits_command_mapd(struct gicv3_its *its,
 }
 
 static inline void
-gits_command_mapi(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint16_t icid)
+gits_command_mapti(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint32_t pintid, uint16_t icid)
 {
 	struct gicv3_its_command cmd;
 
 	/*
-	 * Map the event defined by EventID and DeviceID into an ITT entry with ICID and pINTID = EventID
+	 * Map the event defined by EventID and DeviceID to its associated ITE, defined by ICID and pINTID
+	 * in the ITT associated with DeviceID.
 	 */
 	memset(, 0, sizeof(cmd));
-	cmd.dw[0] = GITS_CMD_MAPI | ((uint64_t)deviceid << 32);
-	cmd.dw[1] = eventid;
+	cmd.dw[0] = GITS_CMD_MAPTI | ((uint64_t)deviceid << 32);
+	cmd.dw[1] = eventid | ((uint64_t)pintid << 32);
 	cmd.dw[2] = icid;
 
 	gits_command(its, );
@@ -329,7 +330,8 @@ gicv3_its_device_map(struct gicv3_its *i
 	/*
 	 * Map the device to the ITT
 	 */
-	gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
+	const u_int size = ilog2(vectors) - 1;
+	gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, size, true);
 	gits_wait(its);
 
 	return 0;
@@ -363,11 +365,13 @@ gicv3_its_msi_enable(struct gicv3_its *i
 		addr & 0x);
 		pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI,
 		(addr >> 32) & 0x);
-		pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, lpi);
+		pci_conf_write(pc, tag, off + PCI_MSI_MDATA64,
+		lpi - its->its_pic->pic_irqbase);
 	} else {
 		pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
 		addr & 0x);
-		pci_conf_write(pc, tag, off + PCI_MSI_MDATA, lpi);
+		pci_conf_write(pc, tag, off + PCI_MSI_MDATA,
+		lpi - its->its_pic->pic_irqbase);
 	}
 	ctl |= PCI_MSI_CTL_MSI_ENABLE;
 	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
@@ -411,7 +415,7 @@ gicv3_its_msix_enable(struct gicv3_its *
 	const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
-	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi);
+	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase);
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
 
 	ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
@@ -477,7 +481,7 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
 		/*
 		 * Map event
 		 */
-		gits_command_mapi(its, devid, lpi, cpu_index(ci));
+		gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 	gits_wait(its);
@@ -546,7 +550,7 @@ gicv3_its_msix_alloc(struct arm_pci_msi 
 		/*
 		 * Map event
 		 */
-		gits_command_mapi(its, devid, lpi, cpu_index(ci));
+		gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 	gits_wait(its);



CVS commit: src/sys/arch/arm/cortex

2019-06-17 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Jun 17 10:15:08 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h

Log Message:
Improve priority handling for cases where access is secure, from OpenBSD.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-17 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Jun 17 10:15:08 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h

Log Message:
Improve priority handling for cases where access is secure, from OpenBSD.


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.17 src/sys/arch/arm/cortex/gicv3.c:1.18
--- src/sys/arch/arm/cortex/gicv3.c:1.17	Wed Jun 12 11:35:17 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Mon Jun 17 10:15:08 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $ */
+/* $NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $");
 
 #include 
 #include 
@@ -52,7 +52,9 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
 #define	LPITOSOFTC(lpi) \
 	((void *)((uintptr_t)(lpi) - offsetof(struct gicv3_softc, sc_lpi)))
 
-#define	IPL_TO_PRIORITY(ipl)	((IPL_HIGH - (ipl)) << 4)
+#define	IPL_TO_PRIORITY(sc, ipl)	(((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
+#define	IPL_TO_PMR(sc, ipl)		(((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define	IPL_TO_LPIPRIO(sc, ipl)		(((0xff - (ipl)) << 4) & 0xff)
 
 static struct gicv3_softc *gicv3_softc;
 
@@ -155,7 +157,7 @@ gicv3_establish_irq(struct pic_softc *pi
 	uint64_t irouter;
 	u_int n;
 
-	const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+	const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
 	const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
 	const u_int icfg_shift = (is->is_irq & 0xf) * 2;
 
@@ -206,7 +208,9 @@ gicv3_establish_irq(struct pic_softc *pi
 static void
 gicv3_set_priority(struct pic_softc *pic, int ipl)
 {
-	icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
+	struct gicv3_softc * const sc = PICTOSOFTC(pic);
+
+	icc_pmr_write(IPL_TO_PMR(sc, ipl));
 }
 
 static void
@@ -246,6 +250,8 @@ gicv3_dist_enable(struct gicv3_softc *sc
 
 	/* Enable Affinity routing and G1NS interrupts */
 	gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
+	if (ISSET(sc->sc_flags, GICV3_F_SECURE))
+		gicd_ctrl = (gicd_ctrl & ~GICD_CTRL_EnableGrp1A) << 1;
 	gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
 }
 
@@ -271,7 +277,7 @@ gicv3_redist_enable(struct gicv3_softc *
 			if (is == NULL)
 priority |= 0xff << byte_shift;
 			else {
-const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
 priority |= ipriority_val << byte_shift;
 			}
 		}
@@ -303,19 +309,11 @@ gicv3_cpu_identity(void)
 {
 	u_int aff3, aff2, aff1, aff0;
 
-#ifdef __aarch64__
-	const register_t mpidr = reg_mpidr_el1_read();
+	const register_t mpidr = cpu_mpidr_aff_read();
 	aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
 	aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
 	aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3);
-#else
-	const register_t mpidr = armreg_mpidr_read();
-	aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
-	aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
-	aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
-	aff3 = 0;
-#endif
 
 	return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) |
 	   __SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) |
@@ -545,7 +543,7 @@ gicv3_lpi_establish_irq(struct pic_softc
 {
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 
-	sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
+	sc->sc_lpiconf.base[is->is_irq] = IPL_TO_LPIPRIO(sc, is->is_ipl) | GIC_LPICONF_Res1;
 
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
 }
@@ -719,6 +717,7 @@ int
 gicv3_init(struct gicv3_softc *sc)
 {
 	const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
+	const uint32_t gicd_ctrl = gicd_read_4(sc, GICD_CTRL);
 	int n;
 
 	KASSERT(CPU_IS_PRIMARY(curcpu()));
@@ -728,6 +727,31 @@ gicv3_init(struct gicv3_softc *sc)
 	for (n = 0; n < MAXCPUS; n++)
 		sc->sc_irouter[n] = UINT64_MAX;
 
+	sc->sc_priority_shift = 4;
+	const uint32_t oldnsacr = gicd_read_4(sc, GICD_NSACRn(2));
+	gicd_write_4(sc, GICD_NSACRn(2), oldnsacr ^ 0x);
+	if (gicd_read_4(sc, GICD_NSACRn(2)) != oldnsacr) {
+		gicd_write_4(sc, GICD_NSACRn(2), oldnsacr);
+		sc->sc_priority_shift--;
+		SET(sc->sc_flags, GICV3_F_SECURE);
+	}
+	aprint_verbose_dev(sc->sc_dev, "access is %ssecure\n",
+	ISSET(sc->sc_flags, GICV3_F_SECURE) ? "" : "in");
+
+	sc->sc_pmr_shift = 4;
+	if ((gicd_ctrl & GICD_CTRL_DS) == 0) {
+		const uint32_t icc_ctlr = icc_ctlr_read();
+		const u_int nbits = __SHIFTOUT(icc_ctlr, ICC_CTLR_EL1_PRIbits) + 1;
+		

CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Jun 17 00:49:55 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c

Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gic_v2m.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.5 src/sys/arch/arm/cortex/gic_v2m.c:1.6
--- src/sys/arch/arm/cortex/gic_v2m.c:1.5	Fri Dec  7 17:56:41 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c	Mon Jun 17 00:49:55 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,10 +32,11 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $");
 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -90,7 +91,7 @@ gic_v2m_msi_available_spi(struct gic_v2m
 }
 
 static void
-gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi)
+gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi, int count)
 {
 	const struct pci_attach_args *pa = frame->frame_pa[spi];
 	pci_chipset_tag_t pc = pa->pa_pc;
@@ -101,6 +102,15 @@ gic_v2m_msi_enable(struct gic_v2m_frame 
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSI, , NULL))
 		panic("gic_v2m_msi_enable: device is not MSI-capable");
 
+	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+	ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
+	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
+	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+	ctl &= ~PCI_MSI_CTL_MME_MASK;
+	ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
+	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
 	const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
 	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
 	if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -148,6 +158,10 @@ gic_v2m_msix_enable(struct gic_v2m_frame
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL))
 		panic("gic_v2m_msix_enable: device is not MSI-X-capable");
 
+	ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+	ctl &= ~PCI_MSIX_CTL_ENABLE;
+	pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+
 	const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
 	const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
@@ -210,10 +224,10 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
 		__SHIFTIN(spi, ARM_PCI_INTR_IRQ) |
 		__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
 		__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
-
-		gic_v2m_msi_enable(frame, spi);
 	}
 
+	gic_v2m_msi_enable(frame, spi_base, *count);
+
 	return vectors;
 }
 



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Mon Jun 17 00:49:55 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c

Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gic_v2m.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 19:19:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Pass correct event ID with MOVI commands


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 19:19:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
Pass correct event ID with MOVI commands


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.13 src/sys/arch/arm/cortex/gicv3_its.c:1.14
--- src/sys/arch/arm/cortex/gicv3_its.c:1.13	Sun Jun 16 11:05:58 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 16 19:19:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $");
 
 #include 
 #include 
@@ -754,7 +754,7 @@ gicv3_its_cpu_init(void *priv, struct cp
 		KASSERT(pa != NULL);
 
 		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-		gits_command_movi(its, devid, devid, cpu_index(ci));
+		gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 
@@ -793,7 +793,7 @@ gicv3_its_set_affinity(void *priv, size_
 
 	if (its->its_cpuonline[cpu_index(ci)] == true) {
 		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-		gits_command_movi(its, devid, devid, cpu_index(ci));
+		gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	}
 



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 11:05:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.12 src/sys/arch/arm/cortex/gicv3_its.c:1.13
--- src/sys/arch/arm/cortex/gicv3_its.c:1.12	Wed Jun 12 21:02:07 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Sun Jun 16 11:05:58 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $");
 
 #include 
 #include 
@@ -336,7 +336,7 @@ gicv3_its_device_map(struct gicv3_its *i
 }
 
 static void
-gicv3_its_msi_enable(struct gicv3_its *its, int lpi)
+gicv3_its_msi_enable(struct gicv3_its *its, int lpi, int count)
 {
 	const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
 	pci_chipset_tag_t pc = pa->pa_pc;
@@ -347,6 +347,15 @@ gicv3_its_msi_enable(struct gicv3_its *i
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSI, , NULL))
 		panic("gicv3_its_msi_enable: device is not MSI-capable");
 
+	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+	ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
+	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
+	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+	ctl &= ~PCI_MSI_CTL_MME_MASK;
+	ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
+	pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
 	const uint64_t addr = its->its_base + GITS_TRANSLATER;
 	ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
 	if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -394,6 +403,10 @@ gicv3_its_msix_enable(struct gicv3_its *
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL))
 		panic("gicv3_its_msix_enable: device is not MSI-X-capable");
 
+	ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+	ctl &= ~PCI_MSIX_CTL_ENABLE;
+	pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+
 	const uint64_t addr = its->its_base + GITS_TRANSLATER;
 	const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
 	bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
@@ -453,7 +466,8 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
 		__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
 		__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
 
-		gicv3_its_msi_enable(its, lpi);
+		if (n == 0)
+			gicv3_its_msi_enable(its, lpi, *count);
 
 		/*
 		 * Record target PE



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 11:05:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c

Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3_its.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 10:57:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gtmr.c

Log Message:
Disable counter before updating cval/tval


To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.39 src/sys/arch/arm/cortex/gtmr.c:1.40
--- src/sys/arch/arm/cortex/gtmr.c:1.39	Wed Jan 30 02:01:58 2019
+++ src/sys/arch/arm/cortex/gtmr.c	Sun Jun 16 10:57:59 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $	*/
+/*	$NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $");
 
 #include 
 #include 
@@ -268,6 +268,9 @@ gtmr_intr(void *arg)
 	if ((ctl & CNTCTL_ISTATUS) == 0)
 		return 0;
 
+	arm_isb();
+	gtmr_cntv_ctl_write(0);
+
 	const uint64_t now = gtmr_read_cntvct(sc);
 	uint64_t delta = now - ci->ci_lastintr;
 
@@ -299,12 +302,16 @@ gtmr_intr(void *arg)
 		delta = 0;
 	}
 
+	arm_isb();
 	if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
 		gtmr_cntv_cval_write(now + sc->sc_autoinc - delta);
 	} else {
 		gtmr_cntv_tval_write(sc->sc_autoinc - delta);
 	}
 
+	arm_isb();
+	gtmr_cntv_ctl_write(CNTCTL_ENABLE);
+
 	ci->ci_lastintr = now;
 
 #ifdef DIAGNOSTIC



CVS commit: src/sys/arch/arm/cortex

2019-06-16 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Sun Jun 16 10:57:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gtmr.c

Log Message:
Disable counter before updating cval/tval


To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 21:02:07 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h

Log Message:
Allow set_affinity calls before PEs are brought online. We store the
desired target PE if set_affinity is called early and restore the routes
when the PE comes alive.


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3_its.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.11 src/sys/arch/arm/cortex/gicv3_its.c:1.12
--- src/sys/arch/arm/cortex/gicv3_its.c:1.11	Wed Jun 12 10:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c	Wed Jun 12 21:02:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $");
 
 #include 
 #include 
@@ -260,11 +260,14 @@ static int
 gicv3_its_msi_alloc_lpi(struct gicv3_its *its,
 const struct pci_attach_args *pa)
 {
+	struct pci_attach_args *new_pa;
 	int n;
 
 	for (n = 0; n < its->its_pic->pic_maxsources; n++) {
 		if (its->its_pa[n] == NULL) {
-			its->its_pa[n] = pa;
+			new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+			memcpy(new_pa, pa, sizeof(*new_pa));
+			its->its_pa[n] = new_pa;
 			return n + its->its_pic->pic_irqbase;
 		}
 	}
@@ -275,8 +278,13 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its
 static void
 gicv3_its_msi_free_lpi(struct gicv3_its *its, int lpi)
 {
+	struct pci_attach_args *pa;
+
 	KASSERT(lpi >= its->its_pic->pic_irqbase);
+
+	pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
 	its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL;
+	kmem_free(pa, sizeof(*pa));
 }
 
 static uint32_t
@@ -702,7 +710,9 @@ gicv3_its_cpu_init(void *priv, struct cp
 {
 	struct gicv3_its * const its = priv;
 	struct gicv3_softc * const sc = its->its_gic;
+	const struct pci_attach_args *pa;
 	uint64_t rdbase;
+	size_t irq;
 
 	const uint64_t typer = bus_space_read_8(sc->sc_bst, its->its_bsh, GITS_TYPER);
 	if (typer & GITS_TYPER_PTA) {
@@ -720,6 +730,20 @@ gicv3_its_cpu_init(void *priv, struct cp
 	gits_command_invall(its, cpu_index(ci));
 	gits_wait(its);
 
+	/*
+	 * Update routing for LPIs targetting this CPU
+	 */
+	for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) {
+		if (its->its_targets[irq] != ci)
+			continue;
+		pa = its->its_pa[irq];
+		KASSERT(pa != NULL);
+
+		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
+		gits_command_movi(its, devid, devid, cpu_index(ci));
+		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+	}
+
 	its->its_cpuonline[cpu_index(ci)] = true;
 }
 
@@ -751,15 +775,14 @@ gicv3_its_set_affinity(void *priv, size_
 		return EINVAL;
 
 	ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
-	if (its->its_cpuonline[cpu_index(ci)] == false)
-		return ENXIO;
-
-	const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
-	gits_command_movi(its, devid, devid, cpu_index(ci));
-	gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
-
 	its->its_targets[irq] = ci;
 
+	if (its->its_cpuonline[cpu_index(ci)] == true) {
+		const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
+		gits_command_movi(its, devid, devid, cpu_index(ci));
+		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+	}
+
 	return 0;
 }
 

Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.5 src/sys/arch/arm/cortex/gicv3_its.h:1.6
--- src/sys/arch/arm/cortex/gicv3_its.h:1.5	Wed Jun 12 10:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3_its.h	Wed Jun 12 21:02:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.5 2019/06/12 10:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.6 2019/06/12 21:02:07 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -59,7 +59,7 @@ struct gicv3_its {
 	struct gicv3_lpi_callback its_cb;
 
 	struct pic_softc	*its_pic;
-	const struct pci_attach_args **its_pa;
+	struct pci_attach_args	**its_pa;
 	struct cpu_info		**its_targets;
 
 	LIST_HEAD(, gicv3_its_device) its_devices;



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 21:02:07 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h

Log Message:
Allow set_affinity calls before PEs are brought online. We store the
desired target PE if set_affinity is called early and restore the routes
when the PE comes alive.


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3_its.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread matthew green
Module Name:src
Committed By:   mrg
Date:   Wed Jun 12 11:35:18 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
revert rev 1.4:
>Adjust priority mappings, NFCI

it has some unintended change that makes nvme hangy.  ok @jmcneill.


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread matthew green
Module Name:src
Committed By:   mrg
Date:   Wed Jun 12 11:35:18 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
revert rev 1.4:
>Adjust priority mappings, NFCI

it has some unintended change that makes nvme hangy.  ok @jmcneill.


To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.16 src/sys/arch/arm/cortex/gicv3.c:1.17
--- src/sys/arch/arm/cortex/gicv3.c:1.16	Wed Jun 12 10:27:59 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Wed Jun 12 11:35:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $");
 
 #include 
 #include 
@@ -155,7 +155,7 @@ gicv3_establish_irq(struct pic_softc *pi
 	uint64_t irouter;
 	u_int n;
 
-	const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
+	const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
 	const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
 	const u_int icfg_shift = (is->is_irq & 0xf) * 2;
 
@@ -206,7 +206,7 @@ gicv3_establish_irq(struct pic_softc *pi
 static void
 gicv3_set_priority(struct pic_softc *pic, int ipl)
 {
-	icc_pmr_write(IPL_TO_PRIORITY(ipl));
+	icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
 }
 
 static void
@@ -271,7 +271,7 @@ gicv3_redist_enable(struct gicv3_softc *
 			if (is == NULL)
 priority |= 0xff << byte_shift;
 			else {
-const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
+const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
 priority |= ipriority_val << byte_shift;
 			}
 		}
@@ -545,7 +545,7 @@ gicv3_lpi_establish_irq(struct pic_softc
 {
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 
-	sc->sc_lpiconf.base[is->is_irq] = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1) | GIC_LPICONF_Res1;
+	sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
 
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
 }



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:27:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Revert "Route all interrupts to the primary PE by default"


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.15 src/sys/arch/arm/cortex/gicv3.c:1.16
--- src/sys/arch/arm/cortex/gicv3.c:1.15	Wed Jun 12 10:03:28 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Wed Jun 12 10:27:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $");
 
 #include 
 #include 
@@ -178,7 +178,6 @@ gicv3_establish_irq(struct pic_softc *pi
 			gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
 		}
 	} else {
-#if notyet
 		if (is->is_mpsafe) {
 			/* Route MP-safe interrupts to all participating PEs */
 			irouter = GICD_IROUTER_Interrupt_Routing_mode;
@@ -186,10 +185,6 @@ gicv3_establish_irq(struct pic_softc *pi
 			/* Route non-MP-safe interrupts to the primary PE only */
 			irouter = sc->sc_irouter[0];
 		}
-#else
-		/* Route interrupts to the primary PE by default */
-		irouter = sc->sc_irouter[0];
-#endif
 		gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
 
 		/* Update interrupt configuration */



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:27:59 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Revert "Route all interrupts to the primary PE by default"


To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:03:28 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Route all interrupts to the primary PE by default


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:03:28 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Route all interrupts to the primary PE by default


To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.14 src/sys/arch/arm/cortex/gicv3.c:1.15
--- src/sys/arch/arm/cortex/gicv3.c:1.14	Wed Jun 12 10:02:17 2019
+++ src/sys/arch/arm/cortex/gicv3.c	Wed Jun 12 10:03:28 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $");
 
 #include 
 #include 
@@ -178,6 +178,7 @@ gicv3_establish_irq(struct pic_softc *pi
 			gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
 		}
 	} else {
+#if notyet
 		if (is->is_mpsafe) {
 			/* Route MP-safe interrupts to all participating PEs */
 			irouter = GICD_IROUTER_Interrupt_Routing_mode;
@@ -185,6 +186,10 @@ gicv3_establish_irq(struct pic_softc *pi
 			/* Route non-MP-safe interrupts to the primary PE only */
 			irouter = sc->sc_irouter[0];
 		}
+#else
+		/* Route interrupts to the primary PE by default */
+		irouter = sc->sc_irouter[0];
+#endif
 		gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
 
 		/* Update interrupt configuration */



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:02:17 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Adjust priority mappings, NFCI


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:02:17 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3.c

Log Message:
Adjust priority mappings, NFCI


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.13 src/sys/arch/arm/cortex/gicv3.c:1.14
--- src/sys/arch/arm/cortex/gicv3.c:1.13	Fri Nov 23 11:49:04 2018
+++ src/sys/arch/arm/cortex/gicv3.c	Wed Jun 12 10:02:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill 
@@ -31,7 +31,7 @@
 #define	_INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $");
 
 #include 
 #include 
@@ -155,7 +155,7 @@ gicv3_establish_irq(struct pic_softc *pi
 	uint64_t irouter;
 	u_int n;
 
-	const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+	const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
 	const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
 	const u_int icfg_shift = (is->is_irq & 0xf) * 2;
 
@@ -206,7 +206,7 @@ gicv3_establish_irq(struct pic_softc *pi
 static void
 gicv3_set_priority(struct pic_softc *pic, int ipl)
 {
-	icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
+	icc_pmr_write(IPL_TO_PRIORITY(ipl));
 }
 
 static void
@@ -271,7 +271,7 @@ gicv3_redist_enable(struct gicv3_softc *
 			if (is == NULL)
 priority |= 0xff << byte_shift;
 			else {
-const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
 priority |= ipriority_val << byte_shift;
 			}
 		}
@@ -545,7 +545,7 @@ gicv3_lpi_establish_irq(struct pic_softc
 {
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 
-	sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
+	sc->sc_lpiconf.base[is->is_irq] = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1) | GIC_LPICONF_Res1;
 
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
 }



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:00:09 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h

Log Message:
Fail gracefully if gicv3_its_set_affinity is called before a cpu is
brought online.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3_its.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-12 Thread Jared D. McNeill
Module Name:src
Committed By:   jmcneill
Date:   Wed Jun 12 10:00:09 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h

Log Message:
Fail gracefully if gicv3_its_set_affinity is called before a cpu is
brought online.


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3_its.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.10 src/sys/arch/arm/cortex/gicv3_its.c:1.11
--- src/sys/arch/arm/cortex/gicv3_its.c:1.10	Sat Dec  8 15:04:40 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c	Wed Jun 12 10:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.10 2018/12/08 15:04:40 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
 #define _INTR_PRIVATE
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.10 2018/12/08 15:04:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $");
 
 #include 
 #include 
@@ -719,6 +719,8 @@ gicv3_its_cpu_init(void *priv, struct cp
 	gits_command_mapc(its, cpu_index(ci), rdbase, true);
 	gits_command_invall(its, cpu_index(ci));
 	gits_wait(its);
+
+	its->its_cpuonline[cpu_index(ci)] = true;
 }
 
 static void
@@ -749,6 +751,8 @@ gicv3_its_set_affinity(void *priv, size_
 		return EINVAL;
 
 	ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
+	if (its->its_cpuonline[cpu_index(ci)] == false)
+		return ENXIO;
 
 	const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
 	gits_command_movi(its, devid, devid, cpu_index(ci));

Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.4 src/sys/arch/arm/cortex/gicv3_its.h:1.5
--- src/sys/arch/arm/cortex/gicv3_its.h:1.4	Wed Nov 28 22:54:11 2018
+++ src/sys/arch/arm/cortex/gicv3_its.h	Wed Jun 12 10:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.4 2018/11/28 22:54:11 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.5 2019/06/12 10:00:09 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -53,6 +53,7 @@ struct gicv3_its {
 	uint32_t		its_id;
 	uint64_t		its_base;
 	uint64_t		its_rdbase[MAXCPUS];
+	bool			its_cpuonline[MAXCPUS];
 
 	struct gicv3_softc	*its_gic;
 	struct gicv3_lpi_callback its_cb;



CVS commit: src/sys/arch/arm/cortex

2019-06-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jun 11 12:48:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9tmr.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



CVS commit: src/sys/arch/arm/cortex

2019-06-11 Thread Nick Hudson
Module Name:src
Committed By:   skrll
Date:   Tue Jun 11 12:48:30 UTC 2019

Modified Files:
src/sys/arch/arm/cortex: a9tmr.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.19 src/sys/arch/arm/cortex/a9tmr.c:1.20
--- src/sys/arch/arm/cortex/a9tmr.c:1.19	Thu Nov 22 21:08:19 2018
+++ src/sys/arch/arm/cortex/a9tmr.c	Tue Jun 11 12:48:30 2019
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9tmr.c,v 1.19 2018/11/22 21:08:19 aymeric Exp $	*/
+/*	$NetBSD: a9tmr.c,v 1.20 2019/06/11 12:48:30 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.19 2018/11/22 21:08:19 aymeric Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.20 2019/06/11 12:48:30 skrll Exp $");
 
 #include 
 #include 
@@ -238,7 +238,7 @@ a9tmr_init_cpu_clock(struct cpu_info *ci
 	a9tmr_gettime(sc));
 	splx(s);
 #elif 0
-	delay(100 / hz + 1000); 
+	delay(100 / hz + 1000);
 #endif
 }
 
@@ -331,7 +331,7 @@ a9tmr_intr(void *arg)
 	a9tmr_global_write(sc, TMR_GBL_INT, 1);	/* Ack the interrupt */
 
 #if 0
-	printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 
+	printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
 	 __func__, cf, ci->ci_data.cpu_name, now, delta);
 #endif
 	KASSERTMSG(delta > sc->sc_autoinc / 64,