CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Jan 28 21:48:03 UTC 2025 Modified Files: src/sys/arch/arm/cortex: gicv3_its.h Log Message: gicv3_its: rename pt_dev_id to pt_index To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Jan 28 21:48:03 UTC 2025
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.h
Log Message:
gicv3_its: rename pt_dev_id to pt_index
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.9 src/sys/arch/arm/cortex/gicv3_its.h:1.10
--- src/sys/arch/arm/cortex/gicv3_its.h:1.9 Sat Dec 7 19:53:07 2024
+++ src/sys/arch/arm/cortex/gicv3_its.h Tue Jan 28 21:48:03 2025
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.9 2024/12/07 19:53:07 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.10 2025/01/28 21:48:03 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -47,7 +47,7 @@ struct gicv3_its_device {
};
struct gicv3_its_page_table {
- uint32_t pt_dev_id;
+ uint32_t pt_index;
struct gicv3_dma pt_dma;
LIST_ENTRY(gicv3_its_page_table) pt_list;
};
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Jan 28 21:20:45 UTC 2025 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3_its: Fix indirect L2 device table allocation. To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Jan 28 21:20:45 UTC 2025
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3_its: Fix indirect L2 device table allocation.
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.40 src/sys/arch/arm/cortex/gicv3_its.c:1.41
--- src/sys/arch/arm/cortex/gicv3_its.c:1.40 Sun Dec 15 11:24:14 2024
+++ src/sys/arch/arm/cortex/gicv3_its.c Tue Jan 28 21:20:45 2025
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.40 2024/12/15 11:24:14 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.41 2025/01/28 21:20:45 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.40 2024/12/15 11:24:14 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.41 2025/01/28 21:20:45 jmcneill Exp $");
#include
#include
@@ -419,30 +419,32 @@ gicv3_its_device_map(struct gicv3_its *i
}
if (itstab->tab_indirect) {
- /* Need to allocate the L2 table. */
uint64_t *l1_tab = itstab->tab_l1;
- struct gicv3_its_page_table *pt;
const u_int index = devid / itstab->tab_l2_num_ids;
- pt = kmem_alloc(sizeof(*pt), KM_SLEEP);
- pt->pt_dev_id = devid;
- gicv3_dma_alloc(its->its_gic, &pt->pt_dma, itstab->tab_l2_entry_size,
- itstab->tab_page_size);
- LIST_INSERT_HEAD(&itstab->tab_pt, pt, pt_list);
-
- if (!itstab->tab_shareable) {
- cpu_dcache_wb_range((vaddr_t)pt->pt_dma.base,
- itstab->tab_l2_entry_size);
- }
- l1_tab[index] = pt->pt_dma.segs[0].ds_addr | GITS_BASER_Valid;
- if (!itstab->tab_shareable) {
- cpu_dcache_wb_range((vaddr_t)&l1_tab[index],
- sizeof(l1_tab[index]));
- }
- dsb(sy);
+ if ((l1_tab[index] & GITS_BASER_Valid) == 0) {
+ /* Need to allocate the L2 table. */
+ struct gicv3_its_page_table *pt;
+
+ pt = kmem_alloc(sizeof(*pt), KM_SLEEP);
+ pt->pt_index = index;
+ gicv3_dma_alloc(its->its_gic, &pt->pt_dma, itstab->tab_l2_entry_size,
+ itstab->tab_page_size);
+ LIST_INSERT_HEAD(&itstab->tab_pt, pt, pt_list);
+
+ if (!itstab->tab_shareable) {
+cpu_dcache_wb_range((vaddr_t)pt->pt_dma.base,
+itstab->tab_l2_entry_size);
+ }
+ l1_tab[index] = pt->pt_dma.segs[0].ds_addr | GITS_BASER_Valid;
+ if (!itstab->tab_shareable) {
+cpu_dcache_wb_range((vaddr_t)&l1_tab[index],
+sizeof(l1_tab[index]));
+ }
+ dsb(sy);
- DPRINTF(("ITS: Allocated L2 entry at index %u for devid 0x%x\n",
- index, devid));
+ DPRINTF(("ITS: Allocated L2 entry at index %u\n", index));
+ }
}
dev = kmem_alloc(sizeof(*dev), KM_SLEEP);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: rin Date: Thu Jan 9 06:55:25 UTC 2025 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: gtmr_delay: Put SPINLOCK_BACKOFF_HOOK in busy loop It is expanded as a `yield` instruction for aarch64. This slightly improves peak performance for some drivers on MP environments, as tested by msaitoh@ (thanks!). XXX This is what OpenBSD does, while FreeBSD just busy-spins. However, unfortunately, benefits from `yield` should be limited, as we still read count register quite frequently. For long-duration delays, Linux uses `wfit` and `wfet` insns if provided, and falls back to `wfe` otherwise: https://github.com/torvalds/linux/blob/master/arch/arm64/lib/delay.c#L26-L51 Event streams should be configured for this purpose. To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: rin
Date: Thu Jan 9 06:55:25 UTC 2025
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
gtmr_delay: Put SPINLOCK_BACKOFF_HOOK in busy loop
It is expanded as a `yield` instruction for aarch64.
This slightly improves peak performance for some drivers on
MP environments, as tested by msaitoh@ (thanks!).
XXX
This is what OpenBSD does, while FreeBSD just busy-spins.
However, unfortunately, benefits from `yield` should be limited,
as we still read count register quite frequently.
For long-duration delays, Linux uses `wfit` and `wfet` insns if
provided, and falls back to `wfe` otherwise:
https://github.com/torvalds/linux/blob/master/arch/arm64/lib/delay.c#L26-L51
Event streams should be configured for this purpose.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.49 src/sys/arch/arm/cortex/gtmr.c:1.50
--- src/sys/arch/arm/cortex/gtmr.c:1.49 Thu Mar 3 06:26:28 2022
+++ src/sys/arch/arm/cortex/gtmr.c Thu Jan 9 06:55:25 2025
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.49 2022/03/03 06:26:28 riastradh Exp $ */
+/* $NetBSD: gtmr.c,v 1.50 2025/01/09 06:55:25 rin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,13 +30,14 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.49 2022/03/03 06:26:28 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.50 2025/01/09 06:55:25 rin Exp $");
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -327,6 +328,7 @@ gtmr_delay(unsigned int n)
uint64_t last = gtmr_read_cntct(sc);
while (ticks > 0) {
+ SPINLOCK_BACKOFF_HOOK;
uint64_t curr = gtmr_read_cntct(sc);
if (curr >= last)
ticks -= (curr - last);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Dec 15 11:24:14 UTC 2024
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3: its: Fix regression on LX2K.
Page size probing and device ID width changes broke LX2K, revert these
parts of the last set of changes as they are not required on X1E.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.39 src/sys/arch/arm/cortex/gicv3_its.c:1.40
--- src/sys/arch/arm/cortex/gicv3_its.c:1.39 Thu Dec 12 08:33:27 2024
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Dec 15 11:24:14 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.39 2024/12/12 08:33:27 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.40 2024/12/15 11:24:14 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.39 2024/12/12 08:33:27 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.40 2024/12/15 11:24:14 jmcneill Exp $");
#include
#include
@@ -459,7 +459,7 @@ gicv3_its_device_map(struct gicv3_its *i
/*
* Map the device to the ITT
*/
- const u_int size = uimax(1, fls32(vectors));
+ const u_int size = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
mutex_enter(its->its_lock);
error = gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, size, true);
if (error == 0) {
@@ -812,46 +812,6 @@ gicv3_its_table_params(struct gicv3_soft
}
}
-static u_int
-gicv3_its_probe_page_size(struct gicv3_its *its, int tab)
-{
- uint64_t baser, tmp;
- u_int page_size = 65536;
-
- baser = gits_read_8(its, GITS_BASERn(tab));
- for (;;) {
- baser &= ~GITS_BASER_Page_Size;
- switch (page_size) {
- case 4096:
- baser |= __SHIFTIN(GITS_Page_Size_4KB, GITS_BASER_Page_Size);
- break;
- case 16384:
- baser |= __SHIFTIN(GITS_Page_Size_16KB, GITS_BASER_Page_Size);
- break;
- case 65536:
- baser |= __SHIFTIN(GITS_Page_Size_64KB, GITS_BASER_Page_Size);
- break;
- }
-
- gits_write_8(its, GITS_BASERn(tab), baser);
- tmp = gits_read_8(its, GITS_BASERn(tab));
- if ((baser & GITS_BASER_Page_Size) == (tmp & GITS_BASER_Page_Size)) {
- return page_size;
- }
-
- if (page_size == 65536) {
- page_size = 16384;
- } else if (page_size == 16384) {
- page_size = 4096;
- } else {
- aprint_error_dev(its->its_gic->sc_dev,
- "WARNING: Couldn't determine ITS page size, "
- "defaulting to 4KB\n");
- return page_size;
- }
- }
-}
-
static bool
gicv3_its_table_probe_indirect(struct gicv3_its *its, int tab)
{
@@ -892,8 +852,18 @@ gicv3_its_table_init(struct gicv3_softc
l2_entry_size = 0;
l2_num_ids = 0;
- page_size = gicv3_its_probe_page_size(its, tab);
- table_align = 65536; // why not
+ switch (__SHIFTOUT(baser, GITS_BASER_Page_Size)) {
+ case GITS_Page_Size_64KB:
+ page_size = 65536;
+ break;
+ case GITS_Page_Size_16KB:
+ page_size = 16384;
+ break;
+ case GITS_Page_Size_4KB:
+ default:
+ page_size = 4096;
+ }
+ table_align = page_size;
switch (__SHIFTOUT(baser, GITS_BASER_Type)) {
case GITS_Type_Devices:
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Dec 15 11:24:14 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3: its: Fix regression on LX2K. Page size probing and device ID width changes broke LX2K, revert these parts of the last set of changes as they are not required on X1E. To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Dec 12 08:33:27 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3: log the ITS command table information To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.38 src/sys/arch/arm/cortex/gicv3_its.c:1.39 --- src/sys/arch/arm/cortex/gicv3_its.c:1.38 Tue Dec 10 21:33:53 2024 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Dec 12 08:33:27 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.38 2024/12/10 21:33:53 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.39 2024/12/12 08:33:27 skrll Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.38 2024/12/10 21:33:53 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.39 2024/12/12 08:33:27 skrll Exp $"); #include #include @@ -783,6 +783,10 @@ gicv3_its_command_init(struct gicv3_soft its->its_cmd_flush = true; } + aprint_normal_dev(sc->sc_dev, "ITS command table @ %#lx/%#lx, %s, %s\n", + its->its_cmd.segs[0].ds_addr, its->its_cmd.len, + gits_cache_type[__SHIFTOUT(cbaser, GITS_BASER_InnerCache)], + gits_share_type[__SHIFTOUT(cbaser, GITS_BASER_Shareability)]); gits_write_8(its, GITS_CWRITER, 0); }
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Dec 12 08:33:27 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3: log the ITS command table information To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Dec 10 21:33:53 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: fixup! Restore a line accidentally removed in my previous change To generate a diff of this commit: cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Dec 10 21:33:53 UTC 2024
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
fixup! Restore a line accidentally removed in my previous change
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.37 src/sys/arch/arm/cortex/gicv3_its.c:1.38
--- src/sys/arch/arm/cortex/gicv3_its.c:1.37 Sun Dec 8 20:04:21 2024
+++ src/sys/arch/arm/cortex/gicv3_its.c Tue Dec 10 21:33:53 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.37 2024/12/08 20:04:21 riastradh Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.38 2024/12/10 21:33:53 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.37 2024/12/08 20:04:21 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.38 2024/12/10 21:33:53 jmcneill Exp $");
#include
#include
@@ -449,6 +449,7 @@ gicv3_its_device_map(struct gicv3_its *i
dev->dev_id = devid;
dev->dev_size = itt_size;
gicv3_dma_alloc(its->its_gic, &dev->dev_itt, itt_size, GITS_ITT_ALIGN);
+ LIST_INSERT_HEAD(&its->its_devices, dev, dev_list);
if (its->its_cmd_flush) {
cpu_dcache_wb_range((vaddr_t)dev->dev_itt.base, itt_size);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Sun Dec 8 20:04:21 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3_its.c: Do-nothing macros must expand to `__nothing', not empty. No functional change intended -- unless this was accidentally broken before. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.36 src/sys/arch/arm/cortex/gicv3_its.c:1.37 --- src/sys/arch/arm/cortex/gicv3_its.c:1.36 Sat Dec 7 19:53:07 2024 +++ src/sys/arch/arm/cortex/gicv3_its.c Sun Dec 8 20:04:21 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.36 2024/12/07 19:53:07 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.37 2024/12/08 20:04:21 riastradh Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.36 2024/12/07 19:53:07 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.37 2024/12/08 20:04:21 riastradh Exp $"); #include #include @@ -53,7 +53,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c, #ifdef ITS_DEBUG #define DPRINTF(x) printf x #else -#define DPRINTF(x) +#define DPRINTF(x) __nothing #endif /*
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Sun Dec 8 20:04:21 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3_its.c: Do-nothing macros must expand to `__nothing', not empty. No functional change intended -- unless this was accidentally broken before. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Dec 7 19:53:07 UTC 2024
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
gicv3: ITS: Add support for indirect device tables.
When devbits is too large to fit into the first level of device table,
some hardware supports the concept of indirect tables. Add support for
this and use it when supported.
This is required for MSIs to work properly on Snapdragon X Elite platforms
(otherwise, MAPD command fails and stalls the ITS command queue).
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.35 src/sys/arch/arm/cortex/gicv3_its.c:1.36
--- src/sys/arch/arm/cortex/gicv3_its.c:1.35 Sat Nov 11 17:35:45 2023
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Dec 7 19:53:07 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.36 2024/12/07 19:53:07 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.36 2024/12/07 19:53:07 jmcneill Exp $");
#include
#include
@@ -45,9 +45,17 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
#include
#include
+#include
+
#include
#include
+#ifdef ITS_DEBUG
+#define DPRINTF(x) printf x
+#else
+#define DPRINTF(x)
+#endif
+
/*
* ITS translation table sizes
*/
@@ -56,6 +64,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
#define GITS_ITT_ALIGN 0x100
+#define GITS_INDIRECT_ENTRY_SIZE 8
+
/*
* IIDR values used for errata
*/
@@ -109,33 +119,42 @@ gits_write_8(struct gicv3_its *its, bus_
bus_space_write_8(its->its_bst, its->its_bsh, reg, val);
}
-static inline void
+static int
gits_command(struct gicv3_its *its, const struct gicv3_its_command *cmd)
{
- uint64_t cwriter;
+ uint64_t cwriter, creadr;
u_int woff;
+ creadr = gits_read_8(its, GITS_CREADR);
+ if (ISSET(creadr, GITS_CREADR_Stalled)) {
+ DPRINTF(("ITS: stalled! GITS_CREADR = 0x%lx\n", creadr));
+ return EIO;
+ }
+
cwriter = gits_read_8(its, GITS_CWRITER);
woff = cwriter & GITS_CWRITER_Offset;
-#ifdef DIAGNOSTIC
- uint64_t creadr = gits_read_8(its, GITS_CREADR);
- KASSERT(!ISSET(creadr, GITS_CREADR_Stalled));
- KASSERT(((woff + sizeof(cmd->dw)) & (its->its_cmd.len - 1)) != (creadr & GITS_CREADR_Offset));
-#endif
uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff);
- for (int i = 0; i < __arraycount(cmd->dw); i++)
+ for (int i = 0; i < __arraycount(cmd->dw); i++) {
dw[i] = htole64(cmd->dw[i]);
- bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE);
+ DPRINTF(("ITS: dw[%u] = 0x%016lx\n", i, cmd->dw[i]));
+ }
+
+ if (its->its_cmd_flush) {
+ cpu_dcache_wb_range((vaddr_t)dw, sizeof(cmd->dw));
+ }
+ dsb(sy);
woff += sizeof(cmd->dw);
if (woff == its->its_cmd.len)
woff = 0;
gits_write_8(its, GITS_CWRITER, woff);
+
+ return 0;
}
-static inline void
+static int
gits_command_mapc(struct gicv3_its *its, uint16_t icid, uint64_t rdbase, bool v)
{
struct gicv3_its_command cmd;
@@ -153,10 +172,13 @@ gits_command_mapc(struct gicv3_its *its,
cmd.dw[2] |= __BIT(63);
}
- gits_command(its, &cmd);
+ DPRINTF(("ITS #%u: MAPC icid 0x%x rdbase 0x%lx valid %u\n",
+ its->its_id, icid, rdbase, v));
+
+ return gits_command(its, &cmd);
}
-static inline void
+static int
gits_command_mapd(struct gicv3_its *its, uint32_t deviceid, uint64_t itt_addr, u_int size, bool v)
{
struct gicv3_its_command cmd;
@@ -168,15 +190,18 @@ gits_command_mapd(struct gicv3_its *its,
*/
memset(&cmd, 0, sizeof(cmd));
cmd.dw[0] = GITS_CMD_MAPD | ((uint64_t)deviceid << 32);
- cmd.dw[1] = size;
if (v) {
+ cmd.dw[1] = uimax(1, size) - 1;
cmd.dw[2] = itt_addr | __BIT(63);
}
- gits_command(its, &cmd);
+ DPRINTF(("ITS #%u: MAPD deviceid 0x%x itt_addr 0x%lx size %u valid %u\n",
+ its->its_id, deviceid, itt_addr, size, v));
+
+ return gits_command(its, &cmd);
}
-static inline void
+static int
gits_command_mapti(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint32_t pintid, uint16_t icid)
{
struct gicv3_its_command cmd;
@@ -190,10 +215,13 @@ gits_command_mapti(struct gicv3_its *its
cmd.dw[1] = eventid | ((uint64_t)pintid << 32);
cmd.dw[2] = icid;
- gits_command(its, &cmd);
+ DPRINTF(("ITS #%u: MAPTI deviceid 0x%x eventid 0x%x pintid 0x%x icid 0x%x\n",
+ its->its_id, deviceid, eventid, pintid, icid));
+
+ return gits_command(its, &cmd);
}
-static inline void
+static int
gits_command_movi(struct gicv3_its *its, uint32_t deviceid,
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Dec 7 19:53:07 UTC 2024 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: gicv3: ITS: Add support for indirect device tables. When devbits is too large to fit into the first level of device table, some hardware supports the concept of indirect tables. Add support for this and use it when supported. This is required for MSIs to work properly on Snapdragon X Elite platforms (otherwise, MAPD command fails and stalls the ITS command queue). To generate a diff of this commit: cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3_its.c cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: tnn
Date: Sat Nov 11 17:35:45 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3_its: assorted minor improvements
- KASSERT that the command queue is not stalled due to async error
before issuing more commands.
- implement gits_command_int under #if 0 (useful for troubleshooting)
- protect command queue with its_lock consistently
- KASSERT for 32-bit MSI that upper bits are 0
- KASSERT return value of gicv3_its_msi_alloc_lpi
- KASSERT that safe conditions for writing to CBASER are met
- move CWRITER initialization to before CBASER
- fix alignment of tables for the 16KB page size case
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.34 src/sys/arch/arm/cortex/gicv3_its.c:1.35
--- src/sys/arch/arm/cortex/gicv3_its.c:1.34 Sun Oct 31 17:24:11 2021
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Nov 11 17:35:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $");
#include
#include
@@ -117,6 +117,11 @@ gits_command(struct gicv3_its *its, cons
cwriter = gits_read_8(its, GITS_CWRITER);
woff = cwriter & GITS_CWRITER_Offset;
+#ifdef DIAGNOSTIC
+ uint64_t creadr = gits_read_8(its, GITS_CREADR);
+ KASSERT(!ISSET(creadr, GITS_CREADR_Stalled));
+ KASSERT(((woff + sizeof(cmd->dw)) & (its->its_cmd.len - 1)) != (creadr & GITS_CREADR_Offset));
+#endif
uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff);
for (int i = 0; i < __arraycount(cmd->dw); i++)
@@ -256,6 +261,26 @@ gits_command_sync(struct gicv3_its *its,
gits_command(its, &cmd);
}
+#if 0
+static inline void
+gits_command_int(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid)
+{
+ struct gicv3_its_command cmd;
+
+ /*
+ * Translate the deviceid and eventid into an icid and pintid through
+ * the device table and ITT. Mark the pintid as pending
+ * on the redistributor.
+ * If the interrupt is not configured the command queue stalls.
+ */
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.dw[0] = GITS_CMD_INT | ((uint64_t)deviceid << 32);
+ cmd.dw[1] = eventid;
+
+ gits_command(its, &cmd);
+}
+#endif
+
static inline int
gits_wait(struct gicv3_its *its)
{
@@ -358,8 +383,10 @@ gicv3_its_device_map(struct gicv3_its *i
* Map the device to the ITT
*/
const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
+ mutex_enter(its->its_lock);
gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
gits_wait(its);
+ mutex_exit(its->its_lock);
return 0;
}
@@ -391,6 +418,7 @@ gicv3_its_msi_enable(struct gicv3_its *i
pci_conf_write(pc, tag, off + PCI_MSI_MDATA64,
lpi - its->its_pic->pic_irqbase);
} else {
+ KASSERT((addr >> 32) == 0);
pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
addr & 0x);
pci_conf_write(pc, tag, off + PCI_MSI_MDATA,
@@ -485,8 +513,10 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
return NULL;
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
+ mutex_enter(its->its_lock);
for (n = 0; n < *count; n++) {
const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
+ KASSERT(lpi >= 0);
vectors[n] = ARM_PCI_INTR_MSI |
__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
@@ -508,6 +538,7 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
+ mutex_exit(its->its_lock);
return vectors;
}
@@ -555,8 +586,10 @@ gicv3_its_msix_alloc(struct arm_pci_msi
}
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
+ mutex_enter(its->its_lock);
for (n = 0; n < *count; n++) {
const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
+ KASSERT(lpi >= 0);
const int msix_vec = table_indexes ? table_indexes[n] : n;
vectors[msix_vec] = ARM_PCI_INTR_MSIX |
__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
@@ -578,6 +611,7 @@ gicv3_its_msix_alloc(struct arm_pci_msi
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
+ mutex_exit(its->its_lock);
bus_space_unmap(bst, bsh, bsz);
@@ -638,14 +672,17 @@ gicv3_its_command_init(struct gicv3_soft
gicv3_dma_alloc(sc, &its->its_cmd, GITS_COMMANDS_SIZE, GITS_COMMANDS_ALIGN);
+ KASSERT((gits_read_4(its, GITS_CTLR) & GITS_CTLR_Enabled) == 0);
+ KASSERT((gits_read_4(its, GITS_CTLR) & GITS_CTLR_Quiescent) != 0);
+
cbaser = its->its_cmd.segs[0].ds_addr;
cbaser |=
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: tnn Date: Sat Nov 11 17:35:45 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3_its: assorted minor improvements - KASSERT that the command queue is not stalled due to async error before issuing more commands. - implement gits_command_int under #if 0 (useful for troubleshooting) - protect command queue with its_lock consistently - KASSERT for 32-bit MSI that upper bits are 0 - KASSERT return value of gicv3_its_msi_alloc_lpi - KASSERT that safe conditions for writing to CBASER are met - move CWRITER initialization to before CBASER - fix alignment of tables for the 16KB page size case To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Thu Oct 5 12:30:59 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: arm/gic: Check l_blcnt, not l_biglocks. l_biglocks is a now-defunct temporary storage used only when sleeping; l_blcnt is the number of kernel locks held by the lwp when not sleeping. Should fix arm builds. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Thu Oct 5 12:30:59 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: arm/gic: Check l_blcnt, not l_biglocks. l_biglocks is a now-defunct temporary storage used only when sleeping; l_blcnt is the number of kernel locks held by the lwp when not sleeping. Should fix arm builds. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.56 src/sys/arch/arm/cortex/gic.c:1.57 --- src/sys/arch/arm/cortex/gic.c:1.56 Sun Jun 26 11:14:36 2022 +++ src/sys/arch/arm/cortex/gic.c Thu Oct 5 12:30:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.56 2022/06/26 11:14:36 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.57 2023/10/05 12:30:59 riastradh Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.56 2022/06/26 11:14:36 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.57 2023/10/05 12:30:59 riastradh Exp $"); #include #include @@ -320,7 +320,7 @@ armgic_irq_handler(void *tf) struct armgic_softc * const sc = &armgic_softc; const int old_ipl = ci->ci_cpl; const int old_mtx_count = ci->ci_mtx_count; - const int old_l_biglocks = ci->ci_curlwp->l_biglocks; + const int old_l_blcnt = ci->ci_curlwp->l_blcnt; #ifdef DEBUG size_t n = 0; #endif @@ -407,7 +407,7 @@ armgic_irq_handler(void *tf) pic_do_pending_ints(I32_bit, old_ipl, tf); KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); KASSERT(old_mtx_count == ci->ci_mtx_count); - KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); + KASSERT(old_l_blcnt == ci->ci_curlwp->l_blcnt); } void
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:12:26 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gtmr_var.h
Log Message:
G/C gtmr_init function declaration
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr_var.h
diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.15 src/sys/arch/arm/cortex/gtmr_var.h:1.16
--- src/sys/arch/arm/cortex/gtmr_var.h:1.15 Fri Nov 12 21:59:04 2021
+++ src/sys/arch/arm/cortex/gtmr_var.h Sat Nov 19 12:12:25 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_var.h,v 1.15 2021/11/12 21:59:04 jmcneill Exp $ */
+/* $NetBSD: gtmr_var.h,v 1.16 2022/11/19 12:12:25 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -51,7 +51,6 @@ struct gtmr_softc {
#ifdef _KERNEL
#include "opt_arm_timer.h"
struct cpu_info;
-void gtmr_init(device_t);
int gtmr_intr(void *);
void gtmr_init_cpu_clock(struct cpu_info *);
void gtmr_delay(unsigned int n);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 19 12:12:26 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gtmr_var.h Log Message: G/C gtmr_init function declaration To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Nov 5 17:30:20 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h
Log Message:
Handle speed change events
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9ptmr.c
diff -u src/sys/arch/arm/cortex/a9ptmr.c:1.2 src/sys/arch/arm/cortex/a9ptmr.c:1.3
--- src/sys/arch/arm/cortex/a9ptmr.c:1.2 Wed Aug 14 09:20:00 2019
+++ src/sys/arch/arm/cortex/a9ptmr.c Sat Nov 5 17:30:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $ */
+/* $NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -30,13 +30,14 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $");
#include
#include
#include
#include
#include
+#include
#include
@@ -265,3 +266,25 @@ a9ptmr_intr(void *arg)
return 1;
}
+
+static void
+a9ptmr_update_freq_cb(void *arg1, void *arg2)
+{
+ a9ptmr_init_cpu_clock(curcpu());
+}
+
+void
+a9ptmr_update_freq(uint32_t freq)
+{
+ struct a9ptmr_softc * const sc = a9ptmr_sc;
+ uint64_t xc;
+
+ KASSERT(sc->sc_dev != NULL);
+ KASSERT(freq != 0);
+
+ sc->sc_freq = freq;
+ sc->sc_load = (sc->sc_freq / hz) - 1;
+
+ xc = xc_broadcast(0, a9ptmr_update_freq_cb, NULL, NULL);
+ xc_wait(xc);
+}
Index: src/sys/arch/arm/cortex/a9ptmr_var.h
diff -u src/sys/arch/arm/cortex/a9ptmr_var.h:1.1 src/sys/arch/arm/cortex/a9ptmr_var.h:1.2
--- src/sys/arch/arm/cortex/a9ptmr_var.h:1.1 Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr_var.h Sat Nov 5 17:30:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: a9ptmr_var.h,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+/* $NetBSD: a9ptmr_var.h,v 1.2 2022/11/05 17:30:20 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,6 +39,7 @@ struct cpu_info;
void a9ptmr_init_cpu_clock(struct cpu_info *);
int a9ptmr_intr(void *);
+void a9ptmr_update_freq(uint32_t);
void a9ptmr_delay(unsigned int n);
#endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Nov 5 17:30:20 UTC 2022 Modified Files: src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h Log Message: Handle speed change events To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jun 25 18:05:09 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.52 src/sys/arch/arm/cortex/gicv3.c:1.53
--- src/sys/arch/arm/cortex/gicv3.c:1.52 Sat Jun 25 13:24:34 2022
+++ src/sys/arch/arm/cortex/gicv3.c Sat Jun 25 18:05:09 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.53 2022/06/25 18:05:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.53 2022/06/25 18:05:09 jmcneill Exp $");
#include
#include
@@ -60,6 +60,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
#define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define IPL_TO_HWPL(ipl) ((ipl) >= IPL_VM ? (ipl) : IPL_NONE)
#define GIC_SUPPORTS_1OFN(sc) (((sc)->sc_gicd_typer & GICD_TYPER_No1N) == 0)
@@ -232,12 +233,13 @@ gicv3_set_priority(struct pic_softc *pic
{
struct gicv3_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
+ const int hwpl = IPL_TO_HWPL(ipl);
- while (ipl < ci->ci_hwpl) {
+ while (hwpl < ci->ci_hwpl) {
/* Lowering priority mask */
- ci->ci_hwpl = ipl;
+ ci->ci_hwpl = hwpl;
__insn_barrier();
- icc_pmr_write(IPL_TO_PMR(sc, ipl));
+ icc_pmr_write(IPL_TO_PMR(sc, hwpl));
}
__insn_barrier();
ci->ci_cpl = ipl;
@@ -729,13 +731,14 @@ gicv3_irq_handler(void *frame)
struct gicv3_softc * const sc = gicv3_softc;
struct pic_softc *pic;
const int oldipl = ci->ci_cpl;
+ const int oldhwpl = IPL_TO_HWPL(oldipl);
ci->ci_data.cpu_nintr++;
- if (ci->ci_hwpl != oldipl) {
- ci->ci_hwpl = oldipl;
- icc_pmr_write(IPL_TO_PMR(sc, oldipl));
- if (oldipl == IPL_HIGH) {
+ if (ci->ci_hwpl != oldhwpl) {
+ ci->ci_hwpl = oldhwpl;
+ icc_pmr_write(IPL_TO_PMR(sc, oldhwpl));
+ if (oldhwpl == IPL_HIGH) {
return;
}
}
@@ -760,6 +763,7 @@ gicv3_irq_handler(void *frame)
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
} else if (ci->ci_cpl != ipl) {
+ KASSERT(ipl >= IPL_VM);
icc_pmr_write(IPL_TO_PMR(sc, ipl));
ci->ci_hwpl = ci->ci_cpl = ipl;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jun 25 18:05:09 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings To generate a diff of this commit: cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Mon Mar 28 19:59:36 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: arm/cortex: Use container_of, not bespoke offsetof arithmetic. To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.49 src/sys/arch/arm/cortex/gicv3.c:1.50 --- src/sys/arch/arm/cortex/gicv3.c:1.49 Sat Oct 2 20:52:09 2021 +++ src/sys/arch/arm/cortex/gicv3.c Mon Mar 28 19:59:35 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $ */ +/* $NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $"); #include #include @@ -58,9 +58,9 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1. #endif #define PICTOSOFTC(pic) \ - ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) + container_of(pic, struct gicv3_softc, sc_pic) #define LPITOSOFTC(lpi) \ - ((void *)((uintptr_t)(lpi) - offsetof(struct gicv3_softc, sc_lpi))) + container_of(lpi, struct gicv3_softc, sc_lpi) #define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff) #define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Mon Mar 28 19:59:36 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: arm/cortex: Use container_of, not bespoke offsetof arithmetic. To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Sat Nov 13 18:30:28 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: fix aarch64 build To generate a diff of this commit: cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jakllsch
Date: Sat Nov 13 18:30:28 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fix aarch64 build
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.47 src/sys/arch/arm/cortex/gtmr.c:1.48
--- src/sys/arch/arm/cortex/gtmr.c:1.47 Fri Nov 12 21:59:04 2021
+++ src/sys/arch/arm/cortex/gtmr.c Sat Nov 13 18:30:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $");
#include
#include
@@ -257,9 +257,11 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
/* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */
int s = splsched();
+#if defined(__arm__)
if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) {
armreg_cnt_frq_write(sc->sc_freq);
}
+#endif
/*
* Allow the virtual and physical counters to be accessed from
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Oct 31 17:24:11 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to
build for me without DIAGNOSTIC.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.33 src/sys/arch/arm/cortex/gicv3_its.c:1.34
--- src/sys/arch/arm/cortex/gicv3_its.c:1.33 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Oct 31 17:24:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.33 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.33 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $");
#include
#include
@@ -589,7 +589,6 @@ gicv3_its_msi_intr_establish(struct arm_
pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname)
{
struct gicv3_its * const its = msi->msi_priv;
- const struct pci_attach_args *pa;
void *intrh;
const int lpi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
@@ -601,8 +600,7 @@ gicv3_its_msi_intr_establish(struct arm_
return NULL;
/* Invalidate LPI configuration tables */
- pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
- KASSERT(pa != NULL);
+ KASSERT(its->its_pa[lpi - its->its_pic->pic_irqbase] != NULL);
const uint32_t devid = its->its_devid[lpi - its->its_pic->pic_irqbase];
gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase);
@@ -771,7 +769,6 @@ gicv3_its_cpu_init(void *priv, struct cp
{
struct gicv3_its * const its = priv;
struct gicv3_softc * const sc = its->its_gic;
- const struct pci_attach_args *pa;
uint64_t rdbase;
size_t irq;
@@ -798,8 +795,7 @@ gicv3_its_cpu_init(void *priv, struct cp
for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) {
if (its->its_targets[irq] != ci)
continue;
- pa = its->its_pa[irq];
- KASSERT(pa != NULL);
+ KASSERT(its->its_pa[irq] != NULL);
const uint32_t devid = its->its_devid[irq];
gits_command_movi(its, devid, irq, cpu_index(ci));
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Oct 31 17:24:11 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to build for me without DIAGNOSTIC. To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Oct 31 15:32:14 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs_armv8.S
Log Message:
Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_splfuncs_armv8.S
diff -u src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.2 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.3
--- src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.2 Sat Oct 30 20:23:12 2021
+++ src/sys/arch/arm/cortex/gic_splfuncs_armv8.S Sun Oct 31 15:32:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_splfuncs_armv8.S,v 1.2 2021/10/30 20:23:12 jmcneill Exp $ */
+/* $NetBSD: gic_splfuncs_armv8.S,v 1.3 2021/10/31 15:32:14 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -29,7 +29,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: gic_splfuncs_armv8.S,v 1.2 2021/10/30 20:23:12 jmcneill Exp $")
+RCSID("$NetBSD: gic_splfuncs_armv8.S,v 1.3 2021/10/31 15:32:14 jmcneill Exp $")
#ifdef __HAVE_PREEMPTION
#define DISABLE_PREEMPTION \
@@ -84,12 +84,12 @@ ENTRY_NP(gic_splx)
DISABLE_PREEMPTION
ldr x1, [x3, #L_CPU] /* get curcpu */
+.Lagain:
/* If newipl >= cpl, just return */
ldr w2, [x1, #CI_CPL]
cmp w0, w2
b.hs .Ldone
-.Lagain:
/* Slow path if ci_intr_depth != 0 */
ldr w2, [x1, #CI_INTR_DEPTH]
cbnz w2, .Lslow
@@ -120,9 +120,9 @@ ENTRY_NP(gic_splx)
ret
.Lrestart:
- /* Reload w0 and x1 */
- mrs x1, tpidr_el1 /* get curlwp */
- ldr x1, [x1, #L_CPU] /* get curcpu */
+ /* Reload registers */
+ mrs x3, tpidr_el1 /* get curlwp */
+ ldr x1, [x3, #L_CPU] /* get curcpu */
ldr w0, [x1, #CI_SPLX_SAVEDIPL] /* get newipl */
b .Lagain
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Oct 31 15:32:14 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic_splfuncs_armv8.S Log Message: Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Thu Oct 21 04:47:57 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix some conditionals to match gicv3 and add some comments to describe
what's going on.
Fixes PR port-evbarm/56420
To generate a diff of this commit:
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.50 src/sys/arch/arm/cortex/gic.c:1.51
--- src/sys/arch/arm/cortex/gic.c:1.50 Sun Sep 26 13:38:50 2021
+++ src/sys/arch/arm/cortex/gic.c Thu Oct 21 04:47:57 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.50 2021/09/26 13:38:50 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.51 2021/10/21 04:47:57 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,7 +35,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.50 2021/09/26 13:38:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.51 2021/10/21 04:47:57 skrll Exp $");
#include
#include
@@ -331,9 +331,17 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
- if (ci->ci_hwpl != old_ipl) {
+ /*
+ * Raise ci_hwpl (and PMR) to ci_cpl and IAR will tell us if the
+ * interrupt that got us here can have its handler run or not.
+ */
+ if (ci->ci_hwpl <= old_ipl) {
ci->ci_hwpl = old_ipl;
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));
+ /*
+ * we'll get no interrupts when PMR is IPL_HIGH, so bail
+ * early.
+ */
if (old_ipl == IPL_HIGH) {
return;
}
@@ -373,11 +381,13 @@ armgic_irq_handler(void *tf)
*
* However, if are just raising ipl, we can just update ci_cpl.
*/
+
+ /* Surely we can KASSERT(ipl < ci->ci_cpl); */
const int ipl = is->is_ipl;
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, tf);
KASSERT(ci->ci_cpl == ipl);
- } else {
+ } else if (ci->ci_cpl != ipl) {
KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x",
ipl, ci->ci_cpl,
gicc_read(sc, GICC_PMR));
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Oct 21 04:47:57 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Fix some conditionals to match gicv3 and add some comments to describe what's going on. Fixes PR port-evbarm/56420 To generate a diff of this commit: cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Oct 2 20:52:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c
pl310.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9tmr_reg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/pl310.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr_reg.h
diff -u src/sys/arch/arm/cortex/a9tmr_reg.h:1.2 src/sys/arch/arm/cortex/a9tmr_reg.h:1.3
--- src/sys/arch/arm/cortex/a9tmr_reg.h:1.2 Sat Jul 27 07:02:09 2019
+++ src/sys/arch/arm/cortex/a9tmr_reg.h Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_reg.h,v 1.2 2019/07/27 07:02:09 skrll Exp $ */
+/* $NetBSD: a9tmr_reg.h,v 1.3 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -87,7 +87,7 @@
#define TMR_GBL_CTL_PRESCALER __BIT(15,8)
#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled
#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled
-#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
+#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
#define TMR_GBL_CTL_ENABLE __BIT(0)
#endif /* !_ARM_CORTEX_A9TMR_REG_H_ */
Index: src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S
diff -u src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.3 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.4
--- src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.3 Sat Dec 22 18:58:29 2012
+++ src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S Sat Oct 2 20:52:09 2021
@@ -29,7 +29,7 @@
#include
-RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.3 2012/12/22 18:58:29 matt Exp $")
+RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.4 2021/10/02 20:52:09 skrll Exp $")
/*
* uint32_t
@@ -52,7 +52,7 @@ ENTRY(cpu_in_cksum_neon)
* Normally the lower addressed is in d6 but in this case we want to
* reverse it since we might only have a single dword and the final
* fold will want the dword to trim in d7 so put the first dword in
- * d7 until we know we are going to read more than one.
+ * d7 until we know we are going to read more than one.
*/
veor d6, d6, d6 /* clear second dword */
vld1.64 {d7}, [ip:64]! /* load first dword */
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.48 src/sys/arch/arm/cortex/gicv3.c:1.49
--- src/sys/arch/arm/cortex/gicv3.c:1.48 Sun Sep 26 13:38:50 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $");
#include
#include
@@ -837,7 +837,7 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
/*
* If we see fewer PMR bits than IPRIORITYRn bits here, it means
* we have a secure view of IPRIORITYRn (this is not supposed to
- * happen!).
+ * happen!).
*/
if (pmrbits < pribits) {
aprint_verbose_dev(sc->sc_dev,
Index: src/sys/arch/arm/cortex/pl310.c
diff -u src/sys/arch/arm/cortex/pl310.c:1.19 src/sys/arch/arm/cortex/pl310.c:1.20
--- src/sys/arch/arm/cortex/pl310.c:1.19 Sat Jan 19 20:52:26 2019
+++ src/sys/arch/arm/cortex/pl310.c Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $ */
+/* $NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $");
#include
#include
@@ -157,7 +157,7 @@ arml2cc_attach(device_t parent, device_t
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
- bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
off, L2CC_SIZE, &sc->sc_memh);
uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Oct 2 20:52:09 UTC 2021 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c pl310.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9tmr_reg.h cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/pl310.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Sep 26 20:55:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs.c
Log Message:
Add missing insn barrier
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_splfuncs.c
diff -u src/sys/arch/arm/cortex/gic_splfuncs.c:1.3 src/sys/arch/arm/cortex/gic_splfuncs.c:1.4
--- src/sys/arch/arm/cortex/gic_splfuncs.c:1.3 Mon Sep 20 21:05:14 2021
+++ src/sys/arch/arm/cortex/gic_splfuncs.c Sun Sep 26 20:55:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_splfuncs.c,v 1.3 2021/09/20 21:05:14 jmcneill Exp $ */
+/* $NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_splfuncs.c,v 1.3 2021/09/20 21:05:14 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $");
#include
#include
@@ -93,6 +93,7 @@ gic_splx(int newipl)
*/
if (__predict_true(ci->ci_intr_depth == 0)) {
ci->ci_splx_savedipl = newipl;
+ __insn_barrier();
ci->ci_splx_restart = &&restart;
__insn_barrier();
checkhwpl:
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Sep 26 20:55:15 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic_splfuncs.c Log Message: Add missing insn barrier To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Sep 11 01:49:12 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
GIC: Support SPI affinity routing before secondary CPUs have hatched.
Instead of reading MPIDR from CPU init to determine a routing target, trust
system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid.
This allows for SPI affinity routing to work before secondary CPUs are
hatched; previously, one of two things would happen:
a) If 1ofN distribution is supported, the SPI could be distributed to any
participating PE.
b) If 1ofN distribution is not supported, the SPI would not be forwarded
and would stay pending.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.46 src/sys/arch/arm/cortex/gicv3.c:1.47
--- src/sys/arch/arm/cortex/gicv3.c:1.46 Tue Aug 10 17:12:31 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sat Sep 11 01:49:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.47 2021/09/11 01:49:11 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.47 2021/09/11 01:49:11 jmcneill Exp $");
#include
#include
@@ -402,18 +402,6 @@ gicv3_cpu_init(struct pic_softc *pic, st
ci->ci_gic_redist = gicv3_find_redist(sc);
ci->ci_gic_sgir = gicv3_sgir(sc);
- /* Store route to CPU for SPIs */
- const uint64_t cpu_identity = gicv3_cpu_identity();
- const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);
- const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);
- const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);
- const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);
- sc->sc_irouter[cpu_index(ci)] =
- __SHIFTIN(aff0, GICD_IROUTER_Aff0) |
- __SHIFTIN(aff1, GICD_IROUTER_Aff1) |
- __SHIFTIN(aff2, GICD_IROUTER_Aff2) |
- __SHIFTIN(aff3, GICD_IROUTER_Aff3);
-
/* Enable System register access and disable IRQ/FIQ bypass */
icc_sre = ICC_SRE_EL1_SRE | ICC_SRE_EL1_DFB | ICC_SRE_EL1_DIB;
icc_sre_write(icc_sre);
@@ -482,8 +470,7 @@ gicv3_get_affinity(struct pic_softc *pic
if (group == 0) {
/* All CPUs are targets for group 0 (SGI/PPI) */
for (n = 0; n < ncpu; n++) {
- if (sc->sc_irouter[n] != UINT64_MAX)
-kcpuset_set(affinity, n);
+ kcpuset_set(affinity, n);
}
} else {
/* Find distributor targets (SPI) */
@@ -861,15 +848,19 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
int
gicv3_init(struct gicv3_softc *sc)
{
- int n;
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
KASSERT(CPU_IS_PRIMARY(curcpu()));
LIST_INIT(&sc->sc_lpi_callbacks);
+ /* Store route to CPU for SPIs */
sc->sc_irouter = kmem_zalloc(sizeof(*sc->sc_irouter) * ncpu, KM_SLEEP);
- for (n = 0; n < ncpu; n++)
- sc->sc_irouter[n] = UINT64_MAX;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ KASSERT(cpu_index(ci) < ncpu);
+ sc->sc_irouter[cpu_index(ci)] = ci->ci_cpuid;
+ }
sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Sep 11 01:49:12 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: GIC: Support SPI affinity routing before secondary CPUs have hatched. Instead of reading MPIDR from CPU init to determine a routing target, trust system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid. This allows for SPI affinity routing to work before secondary CPUs are hatched; previously, one of two things would happen: a) If 1ofN distribution is supported, the SPI could be distributed to any participating PE. b) If 1ofN distribution is not supported, the SPI would not be forwarded and would stay pending. To generate a diff of this commit: cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Sep 9 21:39:03 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
If we get a spurious interrupt, log a debug message and ignore it.
Otherwise we risk tripping an assertion later on due to an interrupt
firing before it is scheduled.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.44 src/sys/arch/arm/cortex/gtmr.c:1.45
--- src/sys/arch/arm/cortex/gtmr.c:1.44 Mon Aug 30 22:53:37 2021
+++ src/sys/arch/arm/cortex/gtmr.c Thu Sep 9 21:39:02 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.45 2021/09/09 21:39:02 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.45 2021/09/09 21:39:02 jmcneill Exp $");
#include
#include
@@ -334,6 +334,12 @@ gtmr_intr(void *arg)
struct clockframe * const cf = arg;
struct gtmr_softc * const sc = >mr_sc;
+ const uint32_t ctl = gtmr_read_ctl(sc);
+ if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) {
+ aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl);
+ return 0;
+ }
+
const uint64_t now = gtmr_read_cntct(sc);
uint64_t delta = now - ci->ci_lastintr;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Sep 9 21:39:03 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: If we get a spurious interrupt, log a debug message and ignore it. Otherwise we risk tripping an assertion later on due to an interrupt firing before it is scheduled. To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Aug 30 22:53:37 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
- Add an isb before cnt[pv]_ctl read
- cntk_ctl is 64-bits
- Do not toggle CNTCTL_IMASK in intr handler, as this may be needed
elsewhere.
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.43 src/sys/arch/arm/cortex/gtmr.c:1.44
--- src/sys/arch/arm/cortex/gtmr.c:1.43 Mon Jan 18 23:43:34 2021
+++ src/sys/arch/arm/cortex/gtmr.c Mon Aug 30 22:53:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.4
#include
#include
#include
+#include
#include
@@ -195,6 +196,8 @@ gtmr_read_cntct(struct gtmr_softc *sc)
static uint32_t
gtmr_read_ctl(struct gtmr_softc *sc)
{
+ isb();
+
if (sc->sc_physical)
return gtmr_cntp_ctl_read();
else
@@ -239,7 +242,8 @@ void
gtmr_init_cpu_clock(struct cpu_info *ci)
{
struct gtmr_softc * const sc = >mr_sc;
- uint32_t val;
+ uint32_t cntk;
+ uint64_t ctl;
KASSERT(ci == curcpu());
@@ -249,29 +253,34 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
* Allow the virtual and physical counters to be accessed from
* usermode. (PL0)
*/
- val = gtmr_cntk_ctl_read();
- val &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN);
+ cntk = gtmr_cntk_ctl_read();
+ cntk &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN);
if (sc->sc_physical) {
- val |= CNTKCTL_PL0PCTEN;
- val &= ~CNTKCTL_PL0VCTEN;
+ cntk |= CNTKCTL_PL0PCTEN;
+ cntk &= ~CNTKCTL_PL0VCTEN;
} else {
- val |= CNTKCTL_PL0VCTEN;
- val &= ~CNTKCTL_PL0PCTEN;
+ cntk |= CNTKCTL_PL0VCTEN;
+ cntk &= ~CNTKCTL_PL0PCTEN;
}
- gtmr_cntk_ctl_write(val);
+ gtmr_cntk_ctl_write(cntk);
isb();
/*
* enable timer and stop masking the timer.
*/
- gtmr_write_ctl(sc, CNTCTL_ENABLE);
+ ctl = gtmr_read_ctl(sc);
+ ctl &= ~CNTCTL_IMASK;
+ ctl |= CNTCTL_ENABLE;
+ gtmr_write_ctl(sc, ctl);
/*
* Get now and update the compare timer.
*/
ci->ci_lastintr = gtmr_read_cntct(sc);
gtmr_write_tval(sc, sc->sc_autoinc);
+
splx(s);
+
KASSERT(gtmr_read_cntct(sc) != 0);
}
@@ -324,14 +333,6 @@ gtmr_intr(void *arg)
struct cpu_info * const ci = curcpu();
struct clockframe * const cf = arg;
struct gtmr_softc * const sc = >mr_sc;
- uint32_t ctl;
-
- ctl = gtmr_read_ctl(sc);
- if ((ctl & CNTCTL_ISTATUS) == 0)
- return 0;
-
- ctl |= CNTCTL_IMASK;
- gtmr_write_ctl(sc, ctl);
const uint64_t now = gtmr_read_cntct(sc);
uint64_t delta = now - ci->ci_lastintr;
@@ -371,11 +372,6 @@ gtmr_intr(void *arg)
gtmr_write_tval(sc, sc->sc_autoinc - delta);
}
- ctl = gtmr_read_ctl(sc);
- ctl &= ~CNTCTL_IMASK;
- ctl |= CNTCTL_ENABLE;
- gtmr_write_ctl(sc, ctl);
-
ci->ci_lastintr = now;
#ifdef DIAGNOSTIC
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Aug 30 22:53:37 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: - Add an isb before cnt[pv]_ctl read - cntk_ctl is 64-bits - Do not toggle CNTCTL_IMASK in intr handler, as this may be needed elsewhere. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Sep 5 13:33:11 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: - Use pic_do_pending_ints in intr handler - Sprinkle isb - Fix PMR bits detection on eMAG, from OpenBSD To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Sep 5 13:33:11 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
- Use pic_do_pending_ints in intr handler
- Sprinkle isb
- Fix PMR bits detection on eMAG, from OpenBSD
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.20 src/sys/arch/arm/cortex/gicv3.c:1.21
--- src/sys/arch/arm/cortex/gicv3.c:1.20 Sun Jun 30 11:11:38 2019
+++ src/sys/arch/arm/cortex/gicv3.c Thu Sep 5 13:33:11 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.21 2019/09/05 13:33:11 jmcneill Exp $");
#include
#include
@@ -213,6 +213,7 @@ gicv3_set_priority(struct pic_softc *pic
struct gicv3_softc * const sc = PICTOSOFTC(pic);
icc_pmr_write(IPL_TO_PMR(sc, ipl));
+ arm_isb();
}
static void
@@ -437,14 +438,17 @@ gicv3_ipi_send(struct pic_softc *pic, co
if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
if (targets != 0) {
icc_sgi1r_write(intid | aff | targets);
+ arm_isb();
targets = 0;
}
aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff);
}
targets |= (ci->ci_gic_sgir & ICC_SGIR_EL1_TargetList);
}
- if (targets != 0)
+ if (targets != 0) {
icc_sgi1r_write(intid | aff | targets);
+ arm_isb();
+ }
}
}
@@ -715,6 +719,7 @@ gicv3_irq_handler(void *frame)
for (;;) {
const uint32_t iar = icc_iar1_read();
+ arm_dsb();
const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID);
if (irq == ICC_IAR_INTID_SPURIOUS)
break;
@@ -726,26 +731,39 @@ gicv3_irq_handler(void *frame)
struct intrsource * const is = pic->pic_sources[irq - pic->pic_irqbase];
KASSERT(is != NULL);
+ const bool early_eoi = irq < GIC_LPI_BASE && is->is_type == IST_EDGE;
+
const int ipl = is->is_ipl;
- if (ci->ci_cpl < ipl)
- pic_set_priority(ci, ipl);
+ if (__predict_false(ipl < ci->ci_cpl)) {
+ pic_do_pending_ints(I32_bit, ipl, frame);
+ } else {
+ gicv3_set_priority(pic, ipl);
+ ci->ci_cpl = ipl;
+ }
+
+ if (early_eoi) {
+ icc_eoi1r_write(iar);
+ arm_isb();
+ }
cpsie(I32_bit);
pic_dispatch(is, frame);
cpsid(I32_bit);
- icc_eoi1r_write(iar);
+ if (!early_eoi) {
+ icc_eoi1r_write(iar);
+ arm_isb();
+ }
}
- if (ci->ci_cpl != oldipl)
- pic_set_priority(ci, oldipl);
+ pic_do_pending_ints(I32_bit, oldipl, frame);
}
static int
gicv3_detect_pmr_bits(struct gicv3_softc *sc)
{
const uint32_t opmr = icc_pmr_read();
- icc_pmr_write(0xff);
+ icc_pmr_write(0xbf);
const uint32_t npmr = icc_pmr_read();
icc_pmr_write(opmr);
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Wed Aug 14 09:20:00 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c
Log Message:
Various fixes / changes
- don't use prescaler
- improve AB_DEBUG output
- fix a9ptmr_delay to work with a decrementing counter!
Thanks to jmcneill@ for proving I'm an idiot
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9ptmr.c
diff -u src/sys/arch/arm/cortex/a9ptmr.c:1.1 src/sys/arch/arm/cortex/a9ptmr.c:1.2
--- src/sys/arch/arm/cortex/a9ptmr.c:1.1 Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr.c Wed Aug 14 09:20:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+/* $NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.1 2019/08/10 17:03:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $");
#include
#include
@@ -144,6 +144,7 @@ a9ptmr_attach(device_t parent, device_t
sc->sc_ctl = a9ptmr_read(sc, TMR_CTL);
sc->sc_prescaler = 1;
+#if 0
/*
* Let's hope the timer frequency isn't prime.
*/
@@ -154,14 +155,17 @@ a9ptmr_attach(device_t parent, device_t
}
}
sc->sc_freq /= sc->sc_prescaler;
+#endif
- aprint_debug_dev(sc->sc_dev, ": freq %d prescaler %d", sc->sc_freq,
+ aprint_debug(": freq %d prescaler %d", sc->sc_freq,
sc->sc_prescaler);
sc->sc_ctl = TMR_CTL_INT_ENABLE | TMR_CTL_AUTO_RELOAD | TMR_CTL_ENABLE;
sc->sc_ctl |= __SHIFTIN(sc->sc_prescaler - 1, TMR_CTL_PRESCALER);
sc->sc_load = (sc->sc_freq / hz) - 1;
+ aprint_debug(": load %d ", sc->sc_load);
+
a9ptmr_init_cpu_clock(curcpu());
aprint_naive("\n");
@@ -188,7 +192,6 @@ a9ptmr_delay(unsigned int n)
curcpu()->ci_data.cpu_cc_freq / 2;
KASSERT(freq != 0);
-
const uint64_t counts_per_usec = freq / 100;
uint32_t delta, usecs, last, curr;
@@ -200,11 +203,11 @@ a9ptmr_delay(unsigned int n)
while (n > usecs) {
curr = a9ptmr_read(sc, TMR_CTR);
- /* Check to see if the timer has wrapped around. */
- if (curr < last)
- delta += curr + (sc->sc_load - last);
+ /* Check to see if the timer has reloaded. */
+ if (curr > last)
+ delta += (sc->sc_load - curr) + last;
else
- delta += curr - last;
+ delta += last - curr;
last = curr;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Wed Aug 14 09:20:00 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9ptmr.c Log Message: Various fixes / changes - don't use prescaler - improve AB_DEBUG output - fix a9ptmr_delay to work with a decrementing counter! Thanks to jmcneill@ for proving I'm an idiot To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Aug 10 16:50:24 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
spaces to tab
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.8 src/sys/arch/arm/cortex/a9wdt.c:1.9
--- src/sys/arch/arm/cortex/a9wdt.c:1.8 Tue Jul 30 06:57:02 2019
+++ src/sys/arch/arm/cortex/a9wdt.c Sat Aug 10 16:50:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $ */
+/* $NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.9 2019/08/10 16:50:23 skrll Exp $");
#include
#include
@@ -183,7 +183,7 @@ a9wdt_setmode(struct sysmon_wdog *smw)
static void
a9wdt_attach(device_t parent, device_t self, void *aux)
{
-struct a9wdt_softc * const sc = device_private(self);
+ struct a9wdt_softc * const sc = device_private(self);
struct mpcore_attach_args * const mpcaa = aux;
prop_dictionary_t dict = device_properties(self);
const char *cpu_type;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Aug 10 16:50:24 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: spaces to tab To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/a9wdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Tue Jul 30 06:57:02 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9wdt.c Log Message: Fix loop to calculate prescaler divisor. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Tue Jul 30 06:57:02 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
Fix loop to calculate prescaler divisor.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9wdt.c
diff -u src/sys/arch/arm/cortex/a9wdt.c:1.7 src/sys/arch/arm/cortex/a9wdt.c:1.8
--- src/sys/arch/arm/cortex/a9wdt.c:1.7 Fri Dec 29 11:07:03 2017
+++ src/sys/arch/arm/cortex/a9wdt.c Tue Jul 30 06:57:02 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $ */
+/* $NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.7 2017/12/29 11:07:03 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.8 2019/07/30 06:57:02 skrll Exp $");
#include
#include
@@ -214,7 +214,7 @@ a9wdt_attach(device_t parent, device_t s
/*
* Let's hope the timer frequency isn't prime.
*/
- for (size_t div = 256; div >= 2; div++) {
+ for (size_t div = 256; div >= 2; div--) {
if (sc->sc_freq % div == 0) {
sc->sc_wdog_prescaler = div;
break;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Jul 27 07:02:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h Log Message: Rename a register define to make it more obvious it's watchdog only To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9tmr_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9tmr_reg.h diff -u src/sys/arch/arm/cortex/a9tmr_reg.h:1.1 src/sys/arch/arm/cortex/a9tmr_reg.h:1.2 --- src/sys/arch/arm/cortex/a9tmr_reg.h:1.1 Sat Sep 1 00:03:14 2012 +++ src/sys/arch/arm/cortex/a9tmr_reg.h Sat Jul 27 07:02:09 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: a9tmr_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */ +/* $NetBSD: a9tmr_reg.h,v 1.2 2019/07/27 07:02:09 skrll Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -57,7 +57,7 @@ #define TMR_CTR 0x0004 // Timer Counter Register #define TMR_CTL 0x0008 // Timer Control Register #define TMR_INT 0x000C // Timer Interrupt Status -#define TMR_RST 0x0010 // Timer Reset Status (WDOG only) +#define TMR_WDOGRST 0x0010 // Timer Reset Status (WDOG only) #define TMR_WDOGDIS 0x0014 // [WO] Timer Disable (WDOG only) #define TMR_CTL_PRESCALER __BITS(15,8)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Jul 27 07:02:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h Log Message: Rename a register define to make it more obvious it's watchdog only To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9tmr_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 17:33:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Cleanup ThunderX quirk and print cache / shareability details for ITT tables
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.20 src/sys/arch/arm/cortex/gicv3_its.c:1.21
--- src/sys/arch/arm/cortex/gicv3_its.c:1.20 Sun Jun 30 10:10:19 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 30 17:33:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $");
#include
#include
@@ -61,7 +61,29 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
*/
#define GITS_IIDR_PID_CAVIUM_THUNDERX 0xa1
#define GITS_IIDR_IMP_CAVIUM 0x34c
-
+#define GITS_IIDR_CAVIUM_ERRATA_MASK (GITS_IIDR_Implementor|GITS_IIDR_ProductID|GITS_IIDR_Variant)
+#define GITS_IIDR_CAVIUM_ERRATA_VALUE \
+ (__SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) | \
+ __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) | \
+ __SHIFTIN(0, GITS_IIDR_Variant))
+
+static const char * gits_cache_type[] = {
+ [GITS_Cache_DEVICE_nGnRnE] = "Device-nGnRnE",
+ [GITS_Cache_NORMAL_NC] = "Non-cacheable",
+ [GITS_Cache_NORMAL_RA_WT] = "Cacheable RA WT",
+ [GITS_Cache_NORMAL_RA_WB] = "Cacheable RA WB",
+ [GITS_Cache_NORMAL_WA_WT] = "Cacheable WA WT",
+ [GITS_Cache_NORMAL_WA_WB] = "Cacheable WA WB",
+ [GITS_Cache_NORMAL_RA_WA_WT] = "Cacheable RA WA WT",
+ [GITS_Cache_NORMAL_RA_WA_WB] = "Cacheable RA WA WB",
+};
+
+static const char * gits_share_type[] = {
+ [GITS_Shareability_NS] = "Non-shareable",
+ [GITS_Shareability_IS] = "Inner shareable",
+ [GITS_Shareability_OS] = "Outer shareable",
+ [3]= "(Reserved)",
+};
static inline uint32_t
gits_read_4(struct gicv3_its *its, bus_size_t reg)
@@ -617,34 +639,36 @@ gicv3_its_command_init(struct gicv3_soft
}
static void
-gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its)
+gicv3_its_table_params(struct gicv3_softc *sc, struct gicv3_its *its,
+u_int *devbits, u_int *innercache, u_int *share)
{
- u_int table_size, page_size, table_align;
- uint64_t baser;
- int tab;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
+ const uint32_t iidr = gits_read_4(its, GITS_IIDR);
- /* devbits and innercache defaults */
- u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
- u_int innercache = GITS_Cache_NORMAL_WA_WB;
- u_int share = GITS_Shareability_IS;
-
- uint32_t iidr = gits_read_4(its, GITS_IIDR);
- const uint32_t ctx =
- __SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) |
- __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) |
- __SHIFTIN(0, GITS_IIDR_Variant);
- const uint32_t mask =
- GITS_IIDR_Implementor |
- GITS_IIDR_ProductID |
- GITS_IIDR_Variant;
-
- if ((iidr & mask) == ctx) {
- devbits = 20; /* 8Mb */
- innercache = GITS_Cache_DEVICE_nGnRnE;
+ /* Default values */
+ *devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+ *innercache = GITS_Cache_NORMAL_WA_WB;
+ *share = GITS_Shareability_IS;
+
+ /* Cavium ThunderX errata */
+ if ((iidr & GITS_IIDR_CAVIUM_ERRATA_MASK) == GITS_IIDR_CAVIUM_ERRATA_VALUE) {
+ *devbits = 20; /* 8Mb */
+ *innercache = GITS_Cache_DEVICE_nGnRnE;
aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n");
}
+}
+
+static void
+gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its)
+{
+ u_int table_size, page_size, table_align;
+ u_int devbits, innercache, share;
+ const char *table_type;
+ uint64_t baser;
+ int tab;
+
+ gicv3_its_table_params(sc, its, &devbits, &innercache, &share);
for (tab = 0; tab < 8; tab++) {
baser = gits_read_8(its, GITS_BASERn(tab));
@@ -673,12 +697,14 @@ gicv3_its_table_init(struct gicv3_softc
* Table size scales with the width of the DeviceID.
*/
table_size = roundup(entry_size * (1 << devbits), page_size);
+ table_type = "Devices";
break;
case GITS_Type_InterruptCollections:
/*
* Allocate space for one interrupt collection per CPU.
*/
table_size = roundup(entry_size * MAXCPUS, page_size);
+ table_type = "Collections";
break;
default:
table_size = 0;
@@ -688,7 +714,6 @@ gicv3_its_table_init(struct gicv3_softc
if (table_size == 0)
continue;
- aprint_normal_dev(sc->sc_dev, "ITS TT%u type %#x size %#x\n", tab, (u_int)__SHIFTOUT(baser, GITS_BASER_Type),
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 30 17:33:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Cleanup ThunderX quirk and print cache / shareability details for ITT tables To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 11:11:38 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Fix size of LPI pending table allocation and enable caching of LPI conf
and pending tables where possible.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.19 src/sys/arch/arm/cortex/gicv3.c:1.20
--- src/sys/arch/arm/cortex/gicv3.c:1.19 Wed Jun 26 23:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3.c Sun Jun 30 11:11:38 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.20 2019/06/30 11:11:38 jmcneill Exp $");
#include
#include
@@ -41,6 +41,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
+#include
+
#include
#include
@@ -516,10 +518,13 @@ gicv3_lpi_unblock_irqs(struct pic_softc
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] |= GIC_LPICONF_Enable;
+ if (sc->sc_lpiconf_flush)
+ cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
- bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, irqbase, 32, BUS_DMASYNC_PREWRITE);
+ if (!sc->sc_lpiconf_flush)
+ __asm __volatile ("dsb ishst");
}
static void
@@ -530,10 +535,13 @@ gicv3_lpi_block_irqs(struct pic_softc *p
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable;
+ if (sc->sc_lpiconf_flush)
+ cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
- bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, irqbase, 32, BUS_DMASYNC_PREWRITE);
+ if (!sc->sc_lpiconf_flush)
+ __asm __volatile ("dsb ishst");
}
static void
@@ -543,7 +551,10 @@ gicv3_lpi_establish_irq(struct pic_softc
sc->sc_lpiconf.base[is->is_irq] = IPL_TO_LPIPRIO(sc, is->is_ipl) | GIC_LPICONF_Res1;
- bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
+ if (sc->sc_lpiconf_flush)
+ cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[is->is_irq], 1);
+ else
+ __asm __volatile ("dsb ishst");
}
static void
@@ -551,6 +562,7 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
struct gicv3_lpi_callback *cb;
+ uint64_t propbase, pendbase;
uint32_t ctlr;
/* If physical LPIs are not supported on this redistributor, just return. */
@@ -568,18 +580,36 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
arm_dsb();
/* Setup the LPI configuration table */
- const uint64_t propbase = sc->sc_lpiconf.segs[0].ds_addr |
+ propbase = sc->sc_lpiconf.segs[0].ds_addr |
__SHIFTIN(ffs(pic->pic_maxsources) - 1, GICR_PROPBASER_IDbits) |
- __SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability) |
- __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache);
+ __SHIFTIN(GICR_Shareability_IS, GICR_PROPBASER_Shareability) |
+ __SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PROPBASER_InnerCache);
gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase);
+ propbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PROPBASER);
+ if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) != GICR_Shareability_IS) {
+ if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) == GICR_Shareability_NS) {
+ propbase &= ~GICR_PROPBASER_Shareability;
+ propbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability);
+ propbase &= ~GICR_PROPBASER_InnerCache;
+ propbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache);
+ gicr_write_8(sc, ci->ci_gic_redist, GICR_PROPBASER, propbase);
+ }
+ sc->sc_lpiconf_flush = true;
+ }
/* Setup the LPI pending table */
- const uint64_t pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr |
- __SHIFTIN(GICR_Shareability_NS, GICR_PENDBASER_Shareability) |
- __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PENDBASER_InnerCache) |
- GICR_PENDBASER_PTZ;
+ pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr |
+ __SHIFTIN(GICR_Shareability_IS, GICR_PENDBASER_Shareability) |
+ __SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PENDBASER_InnerCache);
gicr_write_8(sc, ci->ci_gic_redist, GICR_PENDBASER, pendbase);
+ pendbase = gicr_read_8(sc, ci->ci_gic_redist, GICR_PENDBASER);
+ if (__SHIFTOUT(pendbase, GICR_PENDBASER_Shareability) == GICR_Shareability_NS) {
+ pendbase &= ~GICR_PENDBASER_Shareability;
+ pendbase |= __SHIFTIN(GICR_Shareability_NS,
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 30 11:11:38 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Fix size of LPI pending table allocation and enable caching of LPI conf and pending tables where possible. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 10:10:20 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Enable caching of ITS tables when possible
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.19 src/sys/arch/arm/cortex/gicv3_its.c:1.20
--- src/sys/arch/arm/cortex/gicv3_its.c:1.19 Sat Jun 29 16:48:07 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 30 10:10:19 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.20 2019/06/30 10:10:19 jmcneill Exp $");
#include
#include
@@ -627,7 +627,8 @@ gicv3_its_table_init(struct gicv3_softc
/* devbits and innercache defaults */
u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
- u_int innercache = GITS_Cache_NORMAL_NC;
+ u_int innercache = GITS_Cache_NORMAL_WA_WB;
+ u_int share = GITS_Shareability_IS;
uint32_t iidr = gits_read_4(its, GITS_IIDR);
const uint32_t ctx =
@@ -697,10 +698,18 @@ gicv3_its_table_init(struct gicv3_softc
baser &= ~GITS_BASER_InnerCache;
baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache);
baser &= ~GITS_BASER_Shareability;
- baser |= __SHIFTIN(GITS_Shareability_NS, GITS_BASER_Shareability);
+ baser |= __SHIFTIN(share, GITS_BASER_Shareability);
baser |= GITS_BASER_Valid;
gits_write_8(its, GITS_BASERn(tab), baser);
+
+ baser = gits_read_8(its, GITS_BASERn(tab));
+ if (__SHIFTOUT(baser, GITS_BASER_Shareability) == GITS_Shareability_NS) {
+ baser &= ~GITS_BASER_InnerCache;
+ baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache);
+
+ gits_write_8(its, GITS_BASERn(tab), baser);
+ }
}
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 30 10:10:20 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Enable caching of ITS tables when possible To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jun 29 16:48:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Restore original size calculation for MAPD and don't disable MSI/MSIX on devices before making changes To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jun 29 16:48:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Restore original size calculation for MAPD and don't disable MSI/MSIX on
devices before making changes
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.18 src/sys/arch/arm/cortex/gicv3_its.c:1.19
--- src/sys/arch/arm/cortex/gicv3_its.c:1.18 Sat Jun 29 13:30:59 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Jun 29 16:48:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.19 2019/06/29 16:48:07 jmcneill Exp $");
#include
#include
@@ -329,8 +329,8 @@ gicv3_its_device_map(struct gicv3_its *i
/*
* Map the device to the ITT
*/
- const u_int size = ilog2(vectors) - 1;
- gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, size, true);
+ const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
+ gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
gits_wait(its);
return 0;
@@ -349,10 +349,6 @@ gicv3_its_msi_enable(struct gicv3_its *i
panic("gicv3_its_msi_enable: device is not MSI-capable");
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
- ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
- pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
-
- ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
ctl &= ~PCI_MSI_CTL_MME_MASK;
ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
@@ -406,10 +402,6 @@ gicv3_its_msix_enable(struct gicv3_its *
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
panic("gicv3_its_msix_enable: device is not MSI-X-capable");
- ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
- ctl &= ~PCI_MSIX_CTL_ENABLE;
- pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
-
const uint64_t addr = its->its_base + GITS_TRANSLATER;
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jun 29 13:30:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Rename lpi pic to gicv3-its when an ITS is found To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.17 src/sys/arch/arm/cortex/gicv3_its.c:1.18 --- src/sys/arch/arm/cortex/gicv3_its.c:1.17 Sun Jun 23 16:19:51 2019 +++ src/sys/arch/arm/cortex/gicv3_its.c Sat Jun 29 13:30:59 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.18 2019/06/29 13:30:59 jmcneill Exp $"); #include #include @@ -821,6 +821,7 @@ gicv3_its_init(struct gicv3_softc *sc, b its->its_dmat = sc->sc_dmat; its->its_base = its_base; its->its_pic = &sc->sc_lpi; + snprintf(its->its_pic->pic_name, sizeof(its->its_pic->pic_name), "gicv3-its"); KASSERT(its->its_pic->pic_maxsources > 0); its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP); its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jun 29 13:30:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Rename lpi pic to gicv3-its when an ITS is found To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:10:42 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.h
Log Message:
Remove unused field
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.5 src/sys/arch/arm/cortex/gicv3.h:1.6
--- src/sys/arch/arm/cortex/gicv3.h:1.5 Mon Jun 17 10:15:08 2019
+++ src/sys/arch/arm/cortex/gicv3.h Wed Jun 26 23:10:42 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.5 2019/06/17 10:15:08 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.6 2019/06/26 23:10:42 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -60,9 +60,6 @@ struct gicv3_softc {
bus_space_handle_t *sc_bsh_r; /* GICR */
u_int sc_bsh_r_count;
- u_int sc_flags;
-#define GICV3_F_SECURE 0x01
-
u_int sc_priority_shift;
u_int sc_pmr_shift;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:10:42 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.h Log Message: Remove unused field To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 26 23:00:10 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Change how we detect secure vs non-secure access. Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented, then do the same with a GICD_IPRIORITYR priority value field. If the values differ, assume we have a shifted view of IPRIORITYR. To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:00:10 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Change how we detect secure vs non-secure access.
Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented,
then do the same with a GICD_IPRIORITYR priority value field.
If the values differ, assume we have a shifted view of IPRIORITYR.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.18 src/sys/arch/arm/cortex/gicv3.c:1.19
--- src/sys/arch/arm/cortex/gicv3.c:1.18 Mon Jun 17 10:15:08 2019
+++ src/sys/arch/arm/cortex/gicv3.c Wed Jun 26 23:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.19 2019/06/26 23:00:09 jmcneill Exp $");
#include
#include
@@ -249,9 +249,7 @@ gicv3_dist_enable(struct gicv3_softc *sc
;
/* Enable Affinity routing and G1NS interrupts */
- gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
- if (ISSET(sc->sc_flags, GICV3_F_SECURE))
- gicd_ctrl = (gicd_ctrl & ~GICD_CTRL_EnableGrp1A) << 1;
+ gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_ARE_NS;
gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
}
@@ -713,6 +711,28 @@ gicv3_irq_handler(void *frame)
pic_set_priority(ci, oldipl);
}
+static int
+gicv3_detect_pmr_bits(struct gicv3_softc *sc)
+{
+ const uint32_t opmr = icc_pmr_read();
+ icc_pmr_write(0xff);
+ const uint32_t npmr = icc_pmr_read();
+ icc_pmr_write(opmr);
+
+ return NBBY - (ffs(npmr) - 1);
+}
+
+static int
+gicv3_detect_ipriority_bits(struct gicv3_softc *sc)
+{
+ const uint32_t oipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
+ gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr | 0xff);
+ const uint32_t nipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
+ gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr);
+
+ return NBBY - (ffs(nipriorityr & 0xff) - 1);
+}
+
int
gicv3_init(struct gicv3_softc *sc)
{
@@ -728,27 +748,21 @@ gicv3_init(struct gicv3_softc *sc)
sc->sc_irouter[n] = UINT64_MAX;
sc->sc_priority_shift = 4;
- const uint32_t oldnsacr = gicd_read_4(sc, GICD_NSACRn(2));
- gicd_write_4(sc, GICD_NSACRn(2), oldnsacr ^ 0x);
- if (gicd_read_4(sc, GICD_NSACRn(2)) != oldnsacr) {
- gicd_write_4(sc, GICD_NSACRn(2), oldnsacr);
- sc->sc_priority_shift--;
- SET(sc->sc_flags, GICV3_F_SECURE);
- }
- aprint_verbose_dev(sc->sc_dev, "access is %ssecure\n",
- ISSET(sc->sc_flags, GICV3_F_SECURE) ? "" : "in");
-
sc->sc_pmr_shift = 4;
+
if ((gicd_ctrl & GICD_CTRL_DS) == 0) {
- const uint32_t icc_ctlr = icc_ctlr_read();
- const u_int nbits = __SHIFTOUT(icc_ctlr, ICC_CTLR_EL1_PRIbits) + 1;
- const u_int oldpmr = icc_pmr_read();
- icc_pmr_write(0xff);
- const u_int pmr = icc_pmr_read();
- icc_pmr_write(oldpmr);
- if (nbits == 8 - (ffs(pmr) - 1))
- sc->sc_pmr_shift--;
+ const int pmr_bits = gicv3_detect_pmr_bits(sc);
+ const int ipriority_bits = gicv3_detect_ipriority_bits(sc);
+
+ if (ipriority_bits != pmr_bits)
+ --sc->sc_priority_shift;
+
+ aprint_verbose_dev(sc->sc_dev, "%d pmr bits, %d ipriority bits\n",
+ pmr_bits, ipriority_bits);
+ } else {
+ aprint_verbose_dev(sc->sc_dev, "security disabled\n");
}
+
aprint_verbose_dev(sc->sc_dev, "priority shift %d, pmr shift %d\n",
sc->sc_priority_shift, sc->sc_pmr_shift);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:19:51 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct EventID to MOVI and INV commands To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:19:51 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct EventID to MOVI and INV commands
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.16 src/sys/arch/arm/cortex/gicv3_its.c:1.17
--- src/sys/arch/arm/cortex/gicv3_its.c:1.16 Sun Jun 23 16:04:52 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 23 16:19:51 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.17 2019/06/23 16:19:51 jmcneill Exp $");
#include
#include
@@ -579,7 +579,7 @@ gicv3_its_msi_intr_establish(struct arm_
pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
KASSERT(pa != NULL);
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_inv(its, devid, lpi);
+ gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase);
return intrh;
}
@@ -757,7 +757,7 @@ gicv3_its_cpu_init(void *priv, struct cp
KASSERT(pa != NULL);
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
+ gits_command_movi(its, devid, irq, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
@@ -796,7 +796,7 @@ gicv3_its_set_affinity(void *priv, size_
if (its->its_cpuonline[cpu_index(ci)] == true) {
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
+ gits_command_movi(its, devid, irq, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:04:52 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Remove unused variable (build fix) To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.15 src/sys/arch/arm/cortex/gicv3_its.c:1.16 --- src/sys/arch/arm/cortex/gicv3_its.c:1.15 Sun Jun 23 16:03:30 2019 +++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 23 16:04:52 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.16 2019/06/23 16:04:52 jmcneill Exp $"); #include #include @@ -312,7 +312,6 @@ gicv3_its_device_map(struct gicv3_its *i vectors++; const uint64_t typer = gits_read_8(its, GITS_TYPER); - const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1; const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:04:52 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Remove unused variable (build fix) To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 23 16:03:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Ensure that the "size" parameter of MAPD matches the size of the ITT being mapped and subtract the LPI base from EventID. Fixes multi-vector MSI/MSI-X on RK3399. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:03:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Ensure that the "size" parameter of MAPD matches the size of the ITT being
mapped and subtract the LPI base from EventID. Fixes multi-vector MSI/MSI-X
on RK3399.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.14 src/sys/arch/arm/cortex/gicv3_its.c:1.15
--- src/sys/arch/arm/cortex/gicv3_its.c:1.14 Sun Jun 16 19:19:30 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 23 16:03:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.15 2019/06/23 16:03:30 jmcneill Exp $");
#include
#include
@@ -148,16 +148,17 @@ gits_command_mapd(struct gicv3_its *its,
}
static inline void
-gits_command_mapi(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint16_t icid)
+gits_command_mapti(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint32_t pintid, uint16_t icid)
{
struct gicv3_its_command cmd;
/*
- * Map the event defined by EventID and DeviceID into an ITT entry with ICID and pINTID = EventID
+ * Map the event defined by EventID and DeviceID to its associated ITE, defined by ICID and pINTID
+ * in the ITT associated with DeviceID.
*/
memset(&cmd, 0, sizeof(cmd));
- cmd.dw[0] = GITS_CMD_MAPI | ((uint64_t)deviceid << 32);
- cmd.dw[1] = eventid;
+ cmd.dw[0] = GITS_CMD_MAPTI | ((uint64_t)deviceid << 32);
+ cmd.dw[1] = eventid | ((uint64_t)pintid << 32);
cmd.dw[2] = icid;
gits_command(its, &cmd);
@@ -329,7 +330,8 @@ gicv3_its_device_map(struct gicv3_its *i
/*
* Map the device to the ITT
*/
- gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
+ const u_int size = ilog2(vectors) - 1;
+ gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, size, true);
gits_wait(its);
return 0;
@@ -363,11 +365,13 @@ gicv3_its_msi_enable(struct gicv3_its *i
addr & 0x);
pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI,
(addr >> 32) & 0x);
- pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, lpi);
+ pci_conf_write(pc, tag, off + PCI_MSI_MDATA64,
+ lpi - its->its_pic->pic_irqbase);
} else {
pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
addr & 0x);
- pci_conf_write(pc, tag, off + PCI_MSI_MDATA, lpi);
+ pci_conf_write(pc, tag, off + PCI_MSI_MDATA,
+ lpi - its->its_pic->pic_irqbase);
}
ctl |= PCI_MSI_CTL_MSI_ENABLE;
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
@@ -411,7 +415,7 @@ gicv3_its_msix_enable(struct gicv3_its *
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
- bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi);
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
@@ -477,7 +481,7 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
/*
* Map event
*/
- gits_command_mapi(its, devid, lpi, cpu_index(ci));
+ gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
@@ -546,7 +550,7 @@ gicv3_its_msix_alloc(struct arm_pci_msi
/*
* Map event
*/
- gits_command_mapi(its, devid, lpi, cpu_index(ci));
+ gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jun 17 10:15:08 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: Improve priority handling for cases where access is secure, from OpenBSD. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 10:15:08 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Improve priority handling for cases where access is secure, from OpenBSD.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.17 src/sys/arch/arm/cortex/gicv3.c:1.18
--- src/sys/arch/arm/cortex/gicv3.c:1.17 Wed Jun 12 11:35:17 2019
+++ src/sys/arch/arm/cortex/gicv3.c Mon Jun 17 10:15:08 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $ */
+/* $NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.18 2019/06/17 10:15:08 jmcneill Exp $");
#include
#include
@@ -52,7 +52,9 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define LPITOSOFTC(lpi) \
((void *)((uintptr_t)(lpi) - offsetof(struct gicv3_softc, sc_lpi)))
-#define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4)
+#define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
+#define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define IPL_TO_LPIPRIO(sc, ipl) (((0xff - (ipl)) << 4) & 0xff)
static struct gicv3_softc *gicv3_softc;
@@ -155,7 +157,7 @@ gicv3_establish_irq(struct pic_softc *pi
uint64_t irouter;
u_int n;
- const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+ const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
const u_int icfg_shift = (is->is_irq & 0xf) * 2;
@@ -206,7 +208,9 @@ gicv3_establish_irq(struct pic_softc *pi
static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
- icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
+ struct gicv3_softc * const sc = PICTOSOFTC(pic);
+
+ icc_pmr_write(IPL_TO_PMR(sc, ipl));
}
static void
@@ -246,6 +250,8 @@ gicv3_dist_enable(struct gicv3_softc *sc
/* Enable Affinity routing and G1NS interrupts */
gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
+ if (ISSET(sc->sc_flags, GICV3_F_SECURE))
+ gicd_ctrl = (gicd_ctrl & ~GICD_CTRL_EnableGrp1A) << 1;
gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
}
@@ -271,7 +277,7 @@ gicv3_redist_enable(struct gicv3_softc *
if (is == NULL)
priority |= 0xff << byte_shift;
else {
-const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
priority |= ipriority_val << byte_shift;
}
}
@@ -303,19 +309,11 @@ gicv3_cpu_identity(void)
{
u_int aff3, aff2, aff1, aff0;
-#ifdef __aarch64__
- const register_t mpidr = reg_mpidr_el1_read();
+ const register_t mpidr = cpu_mpidr_aff_read();
aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3);
-#else
- const register_t mpidr = armreg_mpidr_read();
- aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);
- aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);
- aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);
- aff3 = 0;
-#endif
return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) |
__SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) |
@@ -545,7 +543,7 @@ gicv3_lpi_establish_irq(struct pic_softc
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
+ sc->sc_lpiconf.base[is->is_irq] = IPL_TO_LPIPRIO(sc, is->is_ipl) | GIC_LPICONF_Res1;
bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
}
@@ -719,6 +717,7 @@ int
gicv3_init(struct gicv3_softc *sc)
{
const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
+ const uint32_t gicd_ctrl = gicd_read_4(sc, GICD_CTRL);
int n;
KASSERT(CPU_IS_PRIMARY(curcpu()));
@@ -728,6 +727,31 @@ gicv3_init(struct gicv3_softc *sc)
for (n = 0; n < MAXCPUS; n++)
sc->sc_irouter[n] = UINT64_MAX;
+ sc->sc_priority_shift = 4;
+ const uint32_t oldnsacr = gicd_read_4(sc, GICD_NSACRn(2));
+ gicd_write_4(sc, GICD_NSACRn(2), oldnsacr ^ 0x);
+ if (gicd_read_4(sc, GICD_NSACRn(2)) != oldnsacr) {
+ gicd_write_4(sc, GICD_NSACRn(2), oldnsacr);
+ sc->sc_priority_shift--;
+ SET(sc->sc_flags, GICV3_F_SECURE);
+ }
+ aprint_verbose_dev(sc->sc_dev, "access is %ssecure\n",
+ ISSET(sc->sc_flags, GICV3_F_SECURE) ? "" : "in");
+
+ sc->sc_pmr_shift = 4;
+ if ((gicd_ctrl & GICD_CTRL_DS) == 0) {
+ const uint32_t icc_ctlr = icc_ctlr_read();
+ const u_int nbits = __SHIFTOUT(icc_ctlr, ICC_CTLR_EL1_PRIbits) + 1;
+
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 00:49:55 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.5 src/sys/arch/arm/cortex/gic_v2m.c:1.6
--- src/sys/arch/arm/cortex/gic_v2m.c:1.5 Fri Dec 7 17:56:41 2018
+++ src/sys/arch/arm/cortex/gic_v2m.c Mon Jun 17 00:49:55 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,10 +32,11 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.5 2018/12/07 17:56:41 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $");
#include
#include
+#include
#include
#include
@@ -90,7 +91,7 @@ gic_v2m_msi_available_spi(struct gic_v2m
}
static void
-gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi)
+gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi, int count)
{
const struct pci_attach_args *pa = frame->frame_pa[spi];
pci_chipset_tag_t pc = pa->pa_pc;
@@ -101,6 +102,15 @@ gic_v2m_msi_enable(struct gic_v2m_frame
if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL))
panic("gic_v2m_msi_enable: device is not MSI-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MME_MASK;
+ ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -148,6 +158,10 @@ gic_v2m_msix_enable(struct gic_v2m_frame
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
panic("gic_v2m_msix_enable: device is not MSI-X-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+ ctl &= ~PCI_MSIX_CTL_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+
const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI;
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
@@ -210,10 +224,10 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
__SHIFTIN(spi, ARM_PCI_INTR_IRQ) |
__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
-
- gic_v2m_msi_enable(frame, spi);
}
+ gic_v2m_msi_enable(frame, spi_base, *count);
+
return vectors;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jun 17 00:49:55 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the first LPI number, not the last To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gic_v2m.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 16 19:19:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Pass correct event ID with MOVI commands To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 19:19:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct event ID with MOVI commands
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.13 src/sys/arch/arm/cortex/gicv3_its.c:1.14
--- src/sys/arch/arm/cortex/gicv3_its.c:1.13 Sun Jun 16 11:05:58 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 16 19:19:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.14 2019/06/16 19:19:30 jmcneill Exp $");
#include
#include
@@ -754,7 +754,7 @@ gicv3_its_cpu_init(void *priv, struct cp
KASSERT(pa != NULL);
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_movi(its, devid, devid, cpu_index(ci));
+ gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
@@ -793,7 +793,7 @@ gicv3_its_set_affinity(void *priv, size_
if (its->its_cpuonline[cpu_index(ci)] == true) {
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_movi(its, devid, devid, cpu_index(ci));
+ gits_command_movi(its, devid, irq + its->its_pic->pic_irqbase, cpu_index(ci));
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 11:05:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the first LPI number, not the last
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.12 src/sys/arch/arm/cortex/gicv3_its.c:1.13
--- src/sys/arch/arm/cortex/gicv3_its.c:1.12 Wed Jun 12 21:02:07 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Jun 16 11:05:58 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.13 2019/06/16 11:05:58 jmcneill Exp $");
#include
#include
@@ -336,7 +336,7 @@ gicv3_its_device_map(struct gicv3_its *i
}
static void
-gicv3_its_msi_enable(struct gicv3_its *its, int lpi)
+gicv3_its_msi_enable(struct gicv3_its *its, int lpi, int count)
{
const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
pci_chipset_tag_t pc = pa->pa_pc;
@@ -347,6 +347,15 @@ gicv3_its_msi_enable(struct gicv3_its *i
if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL))
panic("gicv3_its_msi_enable: device is not MSI-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MSI_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+ ctl &= ~PCI_MSI_CTL_MME_MASK;
+ ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);
+ pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
+
const uint64_t addr = its->its_base + GITS_TRANSLATER;
ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -394,6 +403,10 @@ gicv3_its_msix_enable(struct gicv3_its *
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
panic("gicv3_its_msix_enable: device is not MSI-X-capable");
+ ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
+ ctl &= ~PCI_MSIX_CTL_ENABLE;
+ pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+
const uint64_t addr = its->its_base + GITS_TRANSLATER;
const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
@@ -453,7 +466,8 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
- gicv3_its_msi_enable(its, lpi);
+ if (n == 0)
+ gicv3_its_msi_enable(its, lpi, *count);
/*
* Record target PE
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 16 11:05:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: - Disable MSI/MSI-X when making changes - MSI: Write the vector count to the Multi Message Enable (MME) field - MSI: Set DATA to the first LPI number, not the last To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 10:57:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Disable counter before updating cval/tval
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.39 src/sys/arch/arm/cortex/gtmr.c:1.40
--- src/sys/arch/arm/cortex/gtmr.c:1.39 Wed Jan 30 02:01:58 2019
+++ src/sys/arch/arm/cortex/gtmr.c Sun Jun 16 10:57:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.39 2019/01/30 02:01:58 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $");
#include
#include
@@ -268,6 +268,9 @@ gtmr_intr(void *arg)
if ((ctl & CNTCTL_ISTATUS) == 0)
return 0;
+ arm_isb();
+ gtmr_cntv_ctl_write(0);
+
const uint64_t now = gtmr_read_cntvct(sc);
uint64_t delta = now - ci->ci_lastintr;
@@ -299,12 +302,16 @@ gtmr_intr(void *arg)
delta = 0;
}
+ arm_isb();
if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
gtmr_cntv_cval_write(now + sc->sc_autoinc - delta);
} else {
gtmr_cntv_tval_write(sc->sc_autoinc - delta);
}
+ arm_isb();
+ gtmr_cntv_ctl_write(CNTCTL_ENABLE);
+
ci->ci_lastintr = now;
#ifdef DIAGNOSTIC
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Jun 16 10:57:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Disable counter before updating cval/tval To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 21:02:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Allow set_affinity calls before PEs are brought online. We store the
desired target PE if set_affinity is called early and restore the routes
when the PE comes alive.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.11 src/sys/arch/arm/cortex/gicv3_its.c:1.12
--- src/sys/arch/arm/cortex/gicv3_its.c:1.11 Wed Jun 12 10:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3_its.c Wed Jun 12 21:02:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.12 2019/06/12 21:02:07 jmcneill Exp $");
#include
#include
@@ -260,11 +260,14 @@ static int
gicv3_its_msi_alloc_lpi(struct gicv3_its *its,
const struct pci_attach_args *pa)
{
+ struct pci_attach_args *new_pa;
int n;
for (n = 0; n < its->its_pic->pic_maxsources; n++) {
if (its->its_pa[n] == NULL) {
- its->its_pa[n] = pa;
+ new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+ memcpy(new_pa, pa, sizeof(*new_pa));
+ its->its_pa[n] = new_pa;
return n + its->its_pic->pic_irqbase;
}
}
@@ -275,8 +278,13 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its
static void
gicv3_its_msi_free_lpi(struct gicv3_its *its, int lpi)
{
+ struct pci_attach_args *pa;
+
KASSERT(lpi >= its->its_pic->pic_irqbase);
+
+ pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL;
+ kmem_free(pa, sizeof(*pa));
}
static uint32_t
@@ -702,7 +710,9 @@ gicv3_its_cpu_init(void *priv, struct cp
{
struct gicv3_its * const its = priv;
struct gicv3_softc * const sc = its->its_gic;
+ const struct pci_attach_args *pa;
uint64_t rdbase;
+ size_t irq;
const uint64_t typer = bus_space_read_8(sc->sc_bst, its->its_bsh, GITS_TYPER);
if (typer & GITS_TYPER_PTA) {
@@ -720,6 +730,20 @@ gicv3_its_cpu_init(void *priv, struct cp
gits_command_invall(its, cpu_index(ci));
gits_wait(its);
+ /*
+ * Update routing for LPIs targetting this CPU
+ */
+ for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) {
+ if (its->its_targets[irq] != ci)
+ continue;
+ pa = its->its_pa[irq];
+ KASSERT(pa != NULL);
+
+ const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
+ gits_command_movi(its, devid, devid, cpu_index(ci));
+ gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+ }
+
its->its_cpuonline[cpu_index(ci)] = true;
}
@@ -751,15 +775,14 @@ gicv3_its_set_affinity(void *priv, size_
return EINVAL;
ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
- if (its->its_cpuonline[cpu_index(ci)] == false)
- return ENXIO;
-
- const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
- gits_command_movi(its, devid, devid, cpu_index(ci));
- gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
-
its->its_targets[irq] = ci;
+ if (its->its_cpuonline[cpu_index(ci)] == true) {
+ const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
+ gits_command_movi(its, devid, devid, cpu_index(ci));
+ gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+ }
+
return 0;
}
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.5 src/sys/arch/arm/cortex/gicv3_its.h:1.6
--- src/sys/arch/arm/cortex/gicv3_its.h:1.5 Wed Jun 12 10:00:09 2019
+++ src/sys/arch/arm/cortex/gicv3_its.h Wed Jun 12 21:02:07 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.5 2019/06/12 10:00:09 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.6 2019/06/12 21:02:07 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -59,7 +59,7 @@ struct gicv3_its {
struct gicv3_lpi_callback its_cb;
struct pic_softc *its_pic;
- const struct pci_attach_args **its_pa;
+ struct pci_attach_args **its_pa;
struct cpu_info **its_targets;
LIST_HEAD(, gicv3_its_device) its_devices;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 12 21:02:07 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Allow set_affinity calls before PEs are brought online. We store the desired target PE if set_affinity is called early and restore the routes when the PE comes alive. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gicv3_its.c cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: mrg Date: Wed Jun 12 11:35:18 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: revert rev 1.4: >Adjust priority mappings, NFCI it has some unintended change that makes nvme hangy. ok @jmcneill. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: mrg
Date: Wed Jun 12 11:35:18 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
revert rev 1.4:
>Adjust priority mappings, NFCI
it has some unintended change that makes nvme hangy. ok @jmcneill.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.16 src/sys/arch/arm/cortex/gicv3.c:1.17
--- src/sys/arch/arm/cortex/gicv3.c:1.16 Wed Jun 12 10:27:59 2019
+++ src/sys/arch/arm/cortex/gicv3.c Wed Jun 12 11:35:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.17 2019/06/12 11:35:17 mrg Exp $");
#include
#include
@@ -155,7 +155,7 @@ gicv3_establish_irq(struct pic_softc *pi
uint64_t irouter;
u_int n;
- const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
+ const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
const u_int icfg_shift = (is->is_irq & 0xf) * 2;
@@ -206,7 +206,7 @@ gicv3_establish_irq(struct pic_softc *pi
static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
- icc_pmr_write(IPL_TO_PRIORITY(ipl));
+ icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
}
static void
@@ -271,7 +271,7 @@ gicv3_redist_enable(struct gicv3_softc *
if (is == NULL)
priority |= 0xff << byte_shift;
else {
-const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
+const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
priority |= ipriority_val << byte_shift;
}
}
@@ -545,7 +545,7 @@ gicv3_lpi_establish_irq(struct pic_softc
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- sc->sc_lpiconf.base[is->is_irq] = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1) | GIC_LPICONF_Res1;
+ sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:27:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Revert "Route all interrupts to the primary PE by default"
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.15 src/sys/arch/arm/cortex/gicv3.c:1.16
--- src/sys/arch/arm/cortex/gicv3.c:1.15 Wed Jun 12 10:03:28 2019
+++ src/sys/arch/arm/cortex/gicv3.c Wed Jun 12 10:27:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.16 2019/06/12 10:27:59 jmcneill Exp $");
#include
#include
@@ -178,7 +178,6 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
} else {
-#if notyet
if (is->is_mpsafe) {
/* Route MP-safe interrupts to all participating PEs */
irouter = GICD_IROUTER_Interrupt_Routing_mode;
@@ -186,10 +185,6 @@ gicv3_establish_irq(struct pic_softc *pi
/* Route non-MP-safe interrupts to the primary PE only */
irouter = sc->sc_irouter[0];
}
-#else
- /* Route interrupts to the primary PE by default */
- irouter = sc->sc_irouter[0];
-#endif
gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
/* Update interrupt configuration */
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:27:59 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Revert "Route all interrupts to the primary PE by default" To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:03:28 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Route all interrupts to the primary PE by default To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:03:28 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Route all interrupts to the primary PE by default
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.14 src/sys/arch/arm/cortex/gicv3.c:1.15
--- src/sys/arch/arm/cortex/gicv3.c:1.14 Wed Jun 12 10:02:17 2019
+++ src/sys/arch/arm/cortex/gicv3.c Wed Jun 12 10:03:28 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.15 2019/06/12 10:03:28 jmcneill Exp $");
#include
#include
@@ -178,6 +178,7 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
} else {
+#if notyet
if (is->is_mpsafe) {
/* Route MP-safe interrupts to all participating PEs */
irouter = GICD_IROUTER_Interrupt_Routing_mode;
@@ -185,6 +186,10 @@ gicv3_establish_irq(struct pic_softc *pi
/* Route non-MP-safe interrupts to the primary PE only */
irouter = sc->sc_irouter[0];
}
+#else
+ /* Route interrupts to the primary PE by default */
+ irouter = sc->sc_irouter[0];
+#endif
gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
/* Update interrupt configuration */
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:02:17 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Adjust priority mappings, NFCI To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:02:17 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Adjust priority mappings, NFCI
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.13 src/sys/arch/arm/cortex/gicv3.c:1.14
--- src/sys/arch/arm/cortex/gicv3.c:1.13 Fri Nov 23 11:49:04 2018
+++ src/sys/arch/arm/cortex/gicv3.c Wed Jun 12 10:02:17 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.13 2018/11/23 11:49:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.14 2019/06/12 10:02:17 jmcneill Exp $");
#include
#include
@@ -155,7 +155,7 @@ gicv3_establish_irq(struct pic_softc *pi
uint64_t irouter;
u_int n;
- const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+ const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
const u_int ipriority_shift = (is->is_irq & 0x3) * 8;
const u_int icfg_shift = (is->is_irq & 0xf) * 2;
@@ -206,7 +206,7 @@ gicv3_establish_irq(struct pic_softc *pi
static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
- icc_pmr_write(IPL_TO_PRIORITY(ipl) << 1);
+ icc_pmr_write(IPL_TO_PRIORITY(ipl));
}
static void
@@ -271,7 +271,7 @@ gicv3_redist_enable(struct gicv3_softc *
if (is == NULL)
priority |= 0xff << byte_shift;
else {
-const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl);
+const u_int ipriority_val = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1);
priority |= ipriority_val << byte_shift;
}
}
@@ -545,7 +545,7 @@ gicv3_lpi_establish_irq(struct pic_softc
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
- sc->sc_lpiconf.base[is->is_irq] = 0x80 | IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
+ sc->sc_lpiconf.base[is->is_irq] = 0x80 | (IPL_TO_PRIORITY(is->is_ipl) >> 1) | GIC_LPICONF_Res1;
bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Wed Jun 12 10:00:09 UTC 2019 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h Log Message: Fail gracefully if gicv3_its_set_affinity is called before a cpu is brought online. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3_its.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:00:09 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Fail gracefully if gicv3_its_set_affinity is called before a cpu is
brought online.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.10 src/sys/arch/arm/cortex/gicv3_its.c:1.11
--- src/sys/arch/arm/cortex/gicv3_its.c:1.10 Sat Dec 8 15:04:40 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Wed Jun 12 10:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.10 2018/12/08 15:04:40 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.10 2018/12/08 15:04:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.11 2019/06/12 10:00:09 jmcneill Exp $");
#include
#include
@@ -719,6 +719,8 @@ gicv3_its_cpu_init(void *priv, struct cp
gits_command_mapc(its, cpu_index(ci), rdbase, true);
gits_command_invall(its, cpu_index(ci));
gits_wait(its);
+
+ its->its_cpuonline[cpu_index(ci)] = true;
}
static void
@@ -749,6 +751,8 @@ gicv3_its_set_affinity(void *priv, size_
return EINVAL;
ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
+ if (its->its_cpuonline[cpu_index(ci)] == false)
+ return ENXIO;
const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
gits_command_movi(its, devid, devid, cpu_index(ci));
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.4 src/sys/arch/arm/cortex/gicv3_its.h:1.5
--- src/sys/arch/arm/cortex/gicv3_its.h:1.4 Wed Nov 28 22:54:11 2018
+++ src/sys/arch/arm/cortex/gicv3_its.h Wed Jun 12 10:00:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.h,v 1.4 2018/11/28 22:54:11 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.5 2019/06/12 10:00:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -53,6 +53,7 @@ struct gicv3_its {
uint32_t its_id;
uint64_t its_base;
uint64_t its_rdbase[MAXCPUS];
+ bool its_cpuonline[MAXCPUS];
struct gicv3_softc *its_gic;
struct gicv3_lpi_callback its_cb;
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Tue Jun 11 12:48:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr.c
diff -u src/sys/arch/arm/cortex/a9tmr.c:1.19 src/sys/arch/arm/cortex/a9tmr.c:1.20
--- src/sys/arch/arm/cortex/a9tmr.c:1.19 Thu Nov 22 21:08:19 2018
+++ src/sys/arch/arm/cortex/a9tmr.c Tue Jun 11 12:48:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr.c,v 1.19 2018/11/22 21:08:19 aymeric Exp $ */
+/* $NetBSD: a9tmr.c,v 1.20 2019/06/11 12:48:30 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.19 2018/11/22 21:08:19 aymeric Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9tmr.c,v 1.20 2019/06/11 12:48:30 skrll Exp $");
#include
#include
@@ -238,7 +238,7 @@ a9tmr_init_cpu_clock(struct cpu_info *ci
a9tmr_gettime(sc));
splx(s);
#elif 0
- delay(100 / hz + 1000);
+ delay(100 / hz + 1000);
#endif
}
@@ -331,7 +331,7 @@ a9tmr_intr(void *arg)
a9tmr_global_write(sc, TMR_GBL_INT, 1); /* Ack the interrupt */
#if 0
- printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
+ printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n",
__func__, cf, ci->ci_data.cpu_name, now, delta);
#endif
KASSERTMSG(delta > sc->sc_autoinc / 64,
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Tue Jun 11 12:48:30 UTC 2019 Modified Files: src/sys/arch/arm/cortex: a9tmr.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
