CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: rillig Date: Sat Apr 27 06:01:08 UTC 2024 Modified Files: src/sys/arch/mips/include: float.h Log Message: mips: fix syntax error in LDBL_MAX (since 2011) To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/float.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/float.h diff -u src/sys/arch/mips/include/float.h:1.18 src/sys/arch/mips/include/float.h:1.19 --- src/sys/arch/mips/include/float.h:1.18 Sun Jul 26 08:08:41 2020 +++ src/sys/arch/mips/include/float.h Sat Apr 27 06:01:08 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: float.h,v 1.18 2020/07/26 08:08:41 simonb Exp $ */ +/* $NetBSD: float.h,v 1.19 2024/04/27 06:01:08 rillig Exp $ */ /*- * Copyright (c) 2013 The NetBSD Foundation, Inc. @@ -55,7 +55,7 @@ #if __STDC_VERSION__ >= 199901L #define LDBL_EPSILON 0x1p-112L #define LDBL_MIN 0x1p-16382L -#define LDBL_MAX 0x1.p+16383L, +#define LDBL_MAX 0x1.p+16383L #else #define LDBL_EPSILON 1.9259299443872358530559779425849273E-34L #define LDBL_MIN 3.3621031431120935062626778173217526E-4932L
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: rillig Date: Sat Apr 27 06:01:08 UTC 2024 Modified Files: src/sys/arch/mips/include: float.h Log Message: mips: fix syntax error in LDBL_MAX (since 2011) To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/float.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: rin Date: Thu Sep 14 03:37:01 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Add initial support to gprof(1) for n64 userland Use gp relative call for _mcount(). Stop using macro name MCOUNT as well for clarity. It has nothing to do with one provided by . Now, gprof(1) works just fine for C programs. On the other hand, some C++ profiling tests of ATF fail as partially observed for n32. More C++ profile tests become broken for GCC12 in comparison to GCC10. Something needs to be adjusted for us, or GCC, or both. To generate a diff of this commit: cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: rin Date: Thu Sep 14 03:37:01 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Add initial support to gprof(1) for n64 userland Use gp relative call for _mcount(). Stop using macro name MCOUNT as well for clarity. It has nothing to do with one provided by . Now, gprof(1) works just fine for C programs. On the other hand, some C++ profiling tests of ATF fail as partially observed for n32. More C++ profile tests become broken for GCC12 in comparison to GCC10. Something needs to be adjusted for us, or GCC, or both. To generate a diff of this commit: cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/asm.h diff -u src/sys/arch/mips/include/asm.h:1.74 src/sys/arch/mips/include/asm.h:1.75 --- src/sys/arch/mips/include/asm.h:1.74 Thu Feb 23 14:56:00 2023 +++ src/sys/arch/mips/include/asm.h Thu Sep 14 03:37:01 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.74 2023/02/23 14:56:00 riastradh Exp $ */ +/* $NetBSD: asm.h,v 1.75 2023/09/14 03:37:01 rin Exp $ */ /* * Copyright (c) 1992, 1993 @@ -71,6 +71,9 @@ #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) #endif /* __ASSEMBLER__ */ +#ifndef GPROF +#define _MIPS_ASM_MCOUNT(x) +#else /* * Define -pg profile entry code. * Must always be noreorder, must never use a macro instruction. @@ -81,7 +84,7 @@ * stack and the final addiu to t9 must always equal the size of this * _MIPS_ASM_MCOUNT. */ -#define _MIPS_ASM_MCOUNT \ +#define _MIPS_ASM_MCOUNT(x) \ .set push; \ .set noreorder; \ .set noat; \ @@ -104,7 +107,8 @@ * call _mcount(). For the no abicalls case, skip the reloc dance. */ #ifdef __mips_abicalls -#define _MIPS_ASM_MCOUNT \ +#if defined(__mips_n32) /* n32 */ +#define _MIPS_ASM_MCOUNT(x) \ .set push; \ .set noreorder; \ .set noat; \ @@ -118,8 +122,28 @@ lw t9,8(sp); \ addiu sp,16; \ .set pop; +#else/* n64 */ +#define _MIPS_ASM_MCOUNT(x) \ + .set push; \ + .set noreorder; \ + .set noat; \ + dsubu sp,16; \ + sd gp,0(sp); \ + sd t9,8(sp); \ + move AT,ra; \ + lui gp,%hi(%neg(%gp_rel(x))); \ + daddiu gp,%lo(%neg(%gp_rel(x))); \ + daddu gp,gp,t9; \ + ld t9,%call16(_mcount)(gp); \ + jalr t9; \ + nop; \ + ld gp,0(sp); \ + ld t9,8(sp); \ + daddiu sp,16; \ + .set pop; +#endif #else /* !__mips_abicalls */ -#define _MIPS_ASM_MCOUNT \ +#define _MIPS_ASM_MCOUNT(x) \ .set push; \ .set noreorder; \ .set noat; \ @@ -129,12 +153,7 @@ .set pop; #endif /* !__mips_abicalls */ #endif /* n32/n64 */ - -#ifdef GPROF -#define MCOUNT _MIPS_ASM_MCOUNT -#else -#define MCOUNT -#endif +#endif /* GPROF */ #ifdef USE_AENT #define AENT(x)\ @@ -187,7 +206,7 @@ _C_LABEL(x): ;\ */ #define STATIC_LEAF(x) \ STATIC_LEAF_NOPROFILE(x); \ - MCOUNT + _MIPS_ASM_MCOUNT(x) /* * LEAF @@ -198,7 +217,7 @@ _C_LABEL(x): ;\ */ #define LEAF(x)\ LEAF_NOPROFILE(x); \ - MCOUNT + _MIPS_ASM_MCOUNT(x) /* * STATIC_XLEAF @@ -241,7 +260,7 @@ _C_LABEL(x): ; \ */ #define NESTED(x, fsize, retpc) \ NESTED_NOPROFILE(x, fsize, retpc); \ - MCOUNT + _MIPS_ASM_MCOUNT(x) /* * STATIC_NESTED @@ -249,7 +268,7 @@ _C_LABEL(x): ; \ */ #define STATIC_NESTED(x, fsize, retpc) \ STATIC_NESTED_NOPROFILE(x, fsize, retpc); \ - MCOUNT + _MIPS_ASM_MCOUNT(x) /* * XNESTED
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: andvar Date: Sat Sep 9 18:49:21 UTC 2023 Modified Files: src/sys/arch/mips/include: mips3_pte.h Log Message: change #define to #error for MIPS3_4100i 8KB page size build protection. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/mips3_pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/mips3_pte.h diff -u src/sys/arch/mips/include/mips3_pte.h:1.31 src/sys/arch/mips/include/mips3_pte.h:1.32 --- src/sys/arch/mips/include/mips3_pte.h:1.31 Mon Aug 17 03:19:35 2020 +++ src/sys/arch/mips/include/mips3_pte.h Sat Sep 9 18:49:21 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: mips3_pte.h,v 1.31 2020/08/17 03:19:35 mrg Exp $ */ +/* $NetBSD: mips3_pte.h,v 1.32 2023/09/09 18:49:21 andvar Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -77,7 +77,7 @@ unsigned int pg_g:1, /* HW: ignore as #define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN) #elif PGSHIFT == 13 #ifdef MIPS3_4100 -#define 8KB page size is not supported on the MIPS3_4100 +#error 8KB page size is not supported on the MIPS3_4100 #endif #define MIPS3_PG_SVPN (~0UL << 13) /* Software page no mask */ #define MIPS3_PG_HVPN (~0UL << 13) /* Hardware page no mask */
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: andvar Date: Sat Sep 9 18:49:21 UTC 2023 Modified Files: src/sys/arch/mips/include: mips3_pte.h Log Message: change #define to #error for MIPS3_4100i 8KB page size build protection. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/mips3_pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: skrll
Date: Sun Jul 23 07:20:45 UTC 2023
Modified Files:
src/sys/arch/mips/include: cpu.h
Log Message:
USE __BIT() for CPUF_* flags. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.134 -r1.135 src/sys/arch/mips/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.134 src/sys/arch/mips/include/cpu.h:1.135
--- src/sys/arch/mips/include/cpu.h:1.134 Tue Jan 31 21:11:24 2023
+++ src/sys/arch/mips/include/cpu.h Sun Jul 23 07:20:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.134 2023/01/31 21:11:24 andvar Exp $ */
+/* $NetBSD: cpu.h,v 1.135 2023/07/23 07:20:45 skrll Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -150,11 +150,11 @@ struct cpu_info {
struct evcnt ci_evcnt_synci_deferred_rqst;
struct evcnt ci_evcnt_synci_ipi_rqst;
-#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */
-#define CPUF_PRESENT 0x02 /* CPU is present */
-#define CPUF_RUNNING 0x04 /* CPU is running */
-#define CPUF_PAUSED 0x08 /* CPU is paused */
-#define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */
+#define CPUF_PRIMARY __BIT(0) /* CPU is primary CPU */
+#define CPUF_PRESENT __BIT(1) /* CPU is present */
+#define CPUF_RUNNING __BIT(2) /* CPU is running */
+#define CPUF_PAUSED __BIT(3) /* CPU is paused */
+#define CPUF_USERPMAP __BIT(5) /* CPU has a user pmap activated */
kcpuset_t *ci_shootdowncpus;
kcpuset_t *ci_multicastcpus;
kcpuset_t *ci_watchcpus;
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Sun Jul 23 07:20:45 UTC 2023 Modified Files: src/sys/arch/mips/include: cpu.h Log Message: USE __BIT() for CPUF_* flags. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.134 -r1.135 src/sys/arch/mips/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: he Date: Sun May 14 18:44:27 UTC 2023 Modified Files: src/sys/arch/mips/include: vmparam.h Log Message: Bump MAXTSIZ from 64MB to 128MB also for o32. This so that the rather large cc1 from gcc12 can be run. OK'ed by simonb@ To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: he Date: Sun May 14 18:44:27 UTC 2023 Modified Files: src/sys/arch/mips/include: vmparam.h Log Message: Bump MAXTSIZ from 64MB to 128MB also for o32. This so that the rather large cc1 from gcc12 can be run. OK'ed by simonb@ To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/vmparam.h diff -u src/sys/arch/mips/include/vmparam.h:1.66 src/sys/arch/mips/include/vmparam.h:1.67 --- src/sys/arch/mips/include/vmparam.h:1.66 Wed Jun 23 15:11:40 2021 +++ src/sys/arch/mips/include/vmparam.h Sun May 14 18:44:27 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.66 2021/06/23 15:11:40 simonb Exp $ */ +/* $NetBSD: vmparam.h,v 1.67 2023/05/14 18:44:27 he Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -88,7 +88,7 @@ */ #if defined(__mips_o32) #ifndef MAXTSIZ -#define MAXTSIZ (64*1024*1024) /* max text size */ +#define MAXTSIZ (128*1024*1024) /* max text size */ #endif #ifndef DFLDSIZ #define DFLDSIZ (128*1024*1024) /* initial data size limit */
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: nakayama Date: Tue Mar 28 10:54:13 UTC 2023 Modified Files: src/sys/arch/mips/include: bus_space_defs.h types.h Log Message: Add missing PRIuBUSSIZE to mips. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/bus_space_defs.h cvs rdiff -u -r1.77 -r1.78 src/sys/arch/mips/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/bus_space_defs.h diff -u src/sys/arch/mips/include/bus_space_defs.h:1.4 src/sys/arch/mips/include/bus_space_defs.h:1.5 --- src/sys/arch/mips/include/bus_space_defs.h:1.4 Sun Jul 26 08:08:41 2020 +++ src/sys/arch/mips/include/bus_space_defs.h Tue Mar 28 10:54:13 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: bus_space_defs.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */ +/* $NetBSD: bus_space_defs.h,v 1.5 2023/03/28 10:54:13 nakayama Exp $ */ /*- * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc. @@ -112,11 +112,13 @@ typedef int64_t bus_addr_t; typedef uint64_t bus_size_t; #define PRIxBUSADDR PRIx64 #define PRIxBUSSIZE PRIx64 +#define PRIuBUSSIZE PRIu64 #else typedef paddr_t bus_addr_t; typedef psize_t bus_size_t; #define PRIxBUSADDR PRIxPADDR #define PRIxBUSSIZE PRIxPSIZE +#define PRIuBUSSIZE PRIuPSIZE #endif /* Index: src/sys/arch/mips/include/types.h diff -u src/sys/arch/mips/include/types.h:1.77 src/sys/arch/mips/include/types.h:1.78 --- src/sys/arch/mips/include/types.h:1.77 Thu Jul 7 10:06:02 2022 +++ src/sys/arch/mips/include/types.h Tue Mar 28 10:54:13 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.77 2022/07/07 10:06:02 martin Exp $ */ +/* $NetBSD: types.h,v 1.78 2023/03/28 10:54:13 nakayama Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -74,12 +74,14 @@ typedef __uint64_t psize_t; #define PRIxPADDR PRIx64 #define PRIxPSIZE PRIx64 #define PRIdPSIZE PRId64 +#define PRIuPSIZE PRIu64 #else typedef __uint32_t paddr_t; typedef __uint32_t psize_t; #define PRIxPADDR PRIx32 #define PRIxPSIZE PRIx32 #define PRIdPSIZE PRId32 +#define PRIuPSIZE PRIu32 #endif #ifdef _LP64 typedef __uint64_t vaddr_t;
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: nakayama Date: Tue Mar 28 10:54:13 UTC 2023 Modified Files: src/sys/arch/mips/include: bus_space_defs.h types.h Log Message: Add missing PRIuBUSSIZE to mips. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/bus_space_defs.h cvs rdiff -u -r1.77 -r1.78 src/sys/arch/mips/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Mon Feb 20 13:30:47 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips/asm.h: Make membar macros conditional on MULTIPROCESSOR. For !MULTIPROCESSOR, define them to be empty or nop as appropriate. To generate a diff of this commit: cvs rdiff -u -r1.72 -r1.73 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Mon Feb 20 13:30:47 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips/asm.h: Make membar macros conditional on MULTIPROCESSOR. For !MULTIPROCESSOR, define them to be empty or nop as appropriate. To generate a diff of this commit: cvs rdiff -u -r1.72 -r1.73 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/asm.h diff -u src/sys/arch/mips/include/asm.h:1.72 src/sys/arch/mips/include/asm.h:1.73 --- src/sys/arch/mips/include/asm.h:1.72 Mon Feb 13 12:00:18 2023 +++ src/sys/arch/mips/include/asm.h Mon Feb 20 13:30:47 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.72 2023/02/13 12:00:18 riastradh Exp $ */ +/* $NetBSD: asm.h,v 1.73 2023/02/20 13:30:47 riastradh Exp $ */ /* * Copyright (c) 1992, 1993 @@ -59,6 +59,7 @@ #if defined(_KERNEL_OPT) #include "opt_gprof.h" +#include "opt_multiprocessor.h" #endif #ifdef __ASSEMBLER__ @@ -573,7 +574,7 @@ _C_LABEL(x): #endif /* compiler define */ -#if defined(__OCTEON__) +#if defined(MULTIPROCESSOR) && defined(__OCTEON__) /* * See common/lib/libc/arch/mips/atomic/membar_ops.S for notes on * Octeon memory ordering guarantees and barriers. @@ -614,7 +615,7 @@ _C_LABEL(x): #define SYNC_REL sync 4 #define BDSYNC_PLUNGER sync 4 #define SYNC_PLUNGER sync 4 -#elif __mips >= 3 || !defined(__mips_o32) +#elif defined(MULTIPROCESSOR) && (__mips >= 3 || !defined(__mips_o32)) #define LLSCSYNC /* nothing */ #define BDSYNC sync #define BDSYNC_ACQ sync
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Mon Feb 13 12:00:18 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips/asm.h: Cite source for Cavium sync plunger business. To generate a diff of this commit: cvs rdiff -u -r1.71 -r1.72 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/asm.h diff -u src/sys/arch/mips/include/asm.h:1.71 src/sys/arch/mips/include/asm.h:1.72 --- src/sys/arch/mips/include/asm.h:1.71 Thu Apr 21 12:06:31 2022 +++ src/sys/arch/mips/include/asm.h Mon Feb 13 12:00:18 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.71 2022/04/21 12:06:31 riastradh Exp $ */ +/* $NetBSD: asm.h,v 1.72 2023/02/13 12:00:18 riastradh Exp $ */ /* * Copyright (c) 1992, 1993 @@ -582,7 +582,30 @@ _C_LABEL(x): * we need to apply a plunger to it _after_ releasing a lock or else * other CPUs may spin for hundreds of thousands of cycles before they * see the lock is released. So we also have the quirky SYNC_PLUNGER - * barrier as syncw. + * barrier as syncw. See the note in the SYNCW instruction description + * on p. 2168 of Cavium OCTEON III CN78XX Hardware Reference Manual, + * CN78XX-HM-0.99E, September 2014: + * + * Core A (writer) + * + * SW R1, DATA# change shared DATA value + * LI R1, 1 + * SYNCW# (or SYNCWS) Perform DATA store before performing FLAG store + * SW R2, FLAG# say that the shared DATA value is valid + * SYNCW# (or SYNCWS) Force the FLAG store soon (CN78XX-specific) + * + * ... + * + * The second SYNCW instruction executed by core A is not + * necessary for correctness, but has very important performance + * effects on the CN78XX. Without it, the store to FLAG may + * linger in core A's write buffer before it becomes visible to + * any other cores. (If core A is not performing many stores, + * this may add hundreds of thousands of cycles to the flag + * release time since the CN78XX core nominally retains stores to + * attempt to merge them before sending the store on the CMI.) + * Applications should include this second SYNCW instruction after + * flag or lock release. */ #define LLSCSYNC /* nothing */ #define BDSYNC sync
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Mon Feb 13 12:00:18 UTC 2023 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips/asm.h: Cite source for Cavium sync plunger business. To generate a diff of this commit: cvs rdiff -u -r1.71 -r1.72 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:04:49 UTC 2022 Modified Files: src/sys/arch/mips/include: mipsNN.h Log Message: Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/mipsNN.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/mipsNN.h diff -u src/sys/arch/mips/include/mipsNN.h:1.12 src/sys/arch/mips/include/mipsNN.h:1.13 --- src/sys/arch/mips/include/mipsNN.h:1.12 Sun Aug 2 23:20:25 2020 +++ src/sys/arch/mips/include/mipsNN.h Tue Nov 8 13:04:49 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: mipsNN.h,v 1.12 2020/08/02 23:20:25 simonb Exp $ */ +/* $NetBSD: mipsNN.h,v 1.13 2022/11/08 13:04:49 simonb Exp $ */ /* * Copyright 2000, 2001 @@ -677,7 +677,7 @@ #define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */ /* "PREF" (R/W): Instruction Prefetching (74K, 1074K). */ -#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12:11) +#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12,11) #define MIPSNN_MTI_CFG7_PREF_SHIFT 11 #define MIPSNN_MTI_CFG7_PREF_DISABLE 0 #define MIPSNN_MTI_CFG7_PREF_ONELINE 1
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:04:49 UTC 2022 Modified Files: src/sys/arch/mips/include: mipsNN.h Log Message: Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/include/mipsNN.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: skrll
Date: Tue Aug 16 13:50:55 UTC 2022
Modified Files:
src/sys/arch/mips/include: pci_machdep.h
Log Message:
Provide pci_intr_setattr
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/pci_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/pci_machdep.h
diff -u src/sys/arch/mips/include/pci_machdep.h:1.9 src/sys/arch/mips/include/pci_machdep.h:1.10
--- src/sys/arch/mips/include/pci_machdep.h:1.9 Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/pci_machdep.h Tue Aug 16 13:50:54 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.h,v 1.9 2020/07/26 08:08:41 simonb Exp $ */
+/* $NetBSD: pci_machdep.h,v 1.10 2022/08/16 13:50:54 skrll Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -68,6 +68,8 @@ struct mips_pci_chipset {
const char *(*pc_intr_string)(void *, pci_intr_handle_t,
char *, size_t);
const struct evcnt *(*pc_intr_evcnt)(void *, pci_intr_handle_t);
+ int (*pc_intr_setattr)(void *, pci_intr_handle_t *,
+ int, uint64_t);
void *(*pc_intr_establish)(void *, pci_intr_handle_t,
int, int (*)(void *), void *);
void (*pc_intr_disestablish)(void *, void *);
@@ -110,6 +112,15 @@ struct mips_pci_chipset {
#define pci_conf_interrupt(c, b, d, p, s, lp)\
(*(c)->pc_conf_interrupt)((c)->pc_intr_v, (b), (d), (p), (s), (lp))
+static inline int
+pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ihp,
+int attr, uint64_t data)
+{
+ if (!pc->pc_intr_setattr)
+ return ENODEV;
+ return pc->pc_intr_setattr(pc, ihp, attr, data);
+}
+
/*
* mips-specific PCI functions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Tue Aug 16 13:50:55 UTC 2022 Modified Files: src/sys/arch/mips/include: pci_machdep.h Log Message: Provide pci_intr_setattr To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/pci_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: martin Date: Thu Jul 7 10:06:02 UTC 2022 Modified Files: src/sys/arch/mips/include: types.h Log Message: Add PRIuVSIZE To generate a diff of this commit: cvs rdiff -u -r1.76 -r1.77 src/sys/arch/mips/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: martin Date: Thu Jul 7 10:06:02 UTC 2022 Modified Files: src/sys/arch/mips/include: types.h Log Message: Add PRIuVSIZE To generate a diff of this commit: cvs rdiff -u -r1.76 -r1.77 src/sys/arch/mips/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/types.h diff -u src/sys/arch/mips/include/types.h:1.76 src/sys/arch/mips/include/types.h:1.77 --- src/sys/arch/mips/include/types.h:1.76 Sat May 15 02:37:07 2021 +++ src/sys/arch/mips/include/types.h Thu Jul 7 10:06:02 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.76 2021/05/15 02:37:07 simonb Exp $ */ +/* $NetBSD: types.h,v 1.77 2022/07/07 10:06:02 martin Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -87,12 +87,14 @@ typedef __uint64_t vsize_t; #define PRIxVADDR PRIx64 #define PRIxVSIZE PRIx64 #define PRIdVSIZE PRId64 +#define PRIuVSIZE PRIu64 #else typedef __uint32_t vaddr_t; typedef __uint32_t vsize_t; #define PRIxVADDR PRIx32 #define PRIxVSIZE PRIx32 #define PRIdVSIZE PRId32 +#define PRIuVSIZE PRIu32 #endif typedef vaddr_t vm_offset_t; /* deprecated (cddl/FreeBSD compat) */
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: riastradh
Date: Sat Apr 9 23:43:20 UTC 2022
Modified Files:
src/sys/arch/mips/include: lock.h
Log Message:
mips: Convert lock.h to membar_release/acquire.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/lock.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/lock.h
diff -u src/sys/arch/mips/include/lock.h:1.22 src/sys/arch/mips/include/lock.h:1.23
--- src/sys/arch/mips/include/lock.h:1.22 Sat Feb 12 17:10:02 2022
+++ src/sys/arch/mips/include/lock.h Sat Apr 9 23:43:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: lock.h,v 1.22 2022/02/12 17:10:02 riastradh Exp $ */
+/* $NetBSD: lock.h,v 1.23 2022/04/09 23:43:20 riastradh Exp $ */
/*-
* Copyright (c) 2001, 2007 The NetBSD Foundation, Inc.
@@ -114,7 +114,7 @@ __cpu_simple_lock_try(__cpu_simple_lock_
* Successful _atomic_cas_uint functions as a load-acquire --
* on MP systems, it issues sync after the LL/SC CAS succeeds;
* on non-MP systems every load is a load-acquire so it's moot.
- * This pairs with the membar_exit and store sequence in
+ * This pairs with the membar_release and store sequence in
* __cpu_simple_unlock that functions as a store-release
* operation.
*
@@ -153,14 +153,14 @@ __cpu_simple_unlock(__cpu_simple_lock_t
{
/*
- * The membar_exit and then store functions as a store-release
- * operation that pairs with the load-acquire operation in
- * successful __cpu_simple_lock_try.
+ * The membar_release and then store functions as a
+ * store-release operation that pairs with the load-acquire
+ * operation in successful __cpu_simple_lock_try.
*
* Can't use atomic_store_release here because that's not
* available in userland at the moment.
*/
- membar_exit();
+ membar_release();
*lp = __SIMPLELOCK_UNLOCKED;
#ifdef _MIPS_ARCH_OCTEONP
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Sat Apr 9 23:43:20 UTC 2022 Modified Files: src/sys/arch/mips/include: lock.h Log Message: mips: Convert lock.h to membar_release/acquire. To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/lock.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Sun Feb 27 19:22:20 UTC 2022 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Redefine LLSCSYNC as empty on non-Octeon MP. This change deletes memory barriers on non-Octeon MP. However, all the appropriate acquire and release barriers are already used in mutex stubs, and no barriers are needed in atomic_* unless we set __HAVE_ATOMIC_AS_MEMBAR which we don't on MIPS. So this should be safe. Unclear whether we need this even on Octeon -- don't have a clear reference on why it's here. To generate a diff of this commit: cvs rdiff -u -r1.68 -r1.69 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/asm.h diff -u src/sys/arch/mips/include/asm.h:1.68 src/sys/arch/mips/include/asm.h:1.69 --- src/sys/arch/mips/include/asm.h:1.68 Sun Feb 27 19:22:12 2022 +++ src/sys/arch/mips/include/asm.h Sun Feb 27 19:22:20 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.68 2022/02/27 19:22:12 riastradh Exp $ */ +/* $NetBSD: asm.h,v 1.69 2022/02/27 19:22:20 riastradh Exp $ */ /* * Copyright (c) 1992, 1993 @@ -581,7 +581,7 @@ _C_LABEL(x): #define BDSYNC_PLUNGER sync 4 #define SYNC_PLUNGER sync 4 #elif __mips >= 3 || !defined(__mips_o32) -#define LLSCSYNC sync +#define LLSCSYNC /* nothing */ #define BDSYNC sync #define BDSYNC_ACQ sync #define SYNC_ACQ sync
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Sun Feb 27 19:22:20 UTC 2022 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Redefine LLSCSYNC as empty on non-Octeon MP. This change deletes memory barriers on non-Octeon MP. However, all the appropriate acquire and release barriers are already used in mutex stubs, and no barriers are needed in atomic_* unless we set __HAVE_ATOMIC_AS_MEMBAR which we don't on MIPS. So this should be safe. Unclear whether we need this even on Octeon -- don't have a clear reference on why it's here. To generate a diff of this commit: cvs rdiff -u -r1.68 -r1.69 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Sun Feb 27 19:22:12 UTC 2022 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Redefine BDSYNC as sync on Octeon, not syncw. BDSYNC is used for membar_sync, which is supposed to be a full sequential consistency barrier, which is not provided by syncw, so this is necessary for correctness. BDSYNC is not used for anything else, so this can't hurt performance, except where it was necessary for correctness anyway or where the semantic choice of membar_sync was too strong anyway. To generate a diff of this commit: cvs rdiff -u -r1.67 -r1.68 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/asm.h diff -u src/sys/arch/mips/include/asm.h:1.67 src/sys/arch/mips/include/asm.h:1.68 --- src/sys/arch/mips/include/asm.h:1.67 Sun Feb 27 19:22:02 2022 +++ src/sys/arch/mips/include/asm.h Sun Feb 27 19:22:12 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.67 2022/02/27 19:22:02 riastradh Exp $ */ +/* $NetBSD: asm.h,v 1.68 2022/02/27 19:22:12 riastradh Exp $ */ /* * Copyright (c) 1992, 1993 @@ -574,7 +574,7 @@ _C_LABEL(x): #if defined(__OCTEON__) /* early cnMIPS have erratum which means 2 */ #define LLSCSYNC sync 4; sync 4 -#define BDSYNC sync 4 /* sync 4 == syncw - sync all writes */ +#define BDSYNC sync #define BDSYNC_ACQ sync #define SYNC_ACQ sync #define SYNC_REL sync
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: riastradh Date: Sun Feb 27 19:22:12 UTC 2022 Modified Files: src/sys/arch/mips/include: asm.h Log Message: mips: Redefine BDSYNC as sync on Octeon, not syncw. BDSYNC is used for membar_sync, which is supposed to be a full sequential consistency barrier, which is not provided by syncw, so this is necessary for correctness. BDSYNC is not used for anything else, so this can't hurt performance, except where it was necessary for correctness anyway or where the semantic choice of membar_sync was too strong anyway. To generate a diff of this commit: cvs rdiff -u -r1.67 -r1.68 src/sys/arch/mips/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Tue Jan 4 05:39:12 UTC 2022 Modified Files: src/sys/arch/mips/include: pmap.h Log Message: consistency. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.75 -r1.76 src/sys/arch/mips/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/pmap.h diff -u src/sys/arch/mips/include/pmap.h:1.75 src/sys/arch/mips/include/pmap.h:1.76 --- src/sys/arch/mips/include/pmap.h:1.75 Sun Dec 20 16:38:25 2020 +++ src/sys/arch/mips/include/pmap.h Tue Jan 4 05:39:12 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.75 2020/12/20 16:38:25 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.76 2022/01/04 05:39:12 skrll Exp $ */ /* * Copyright (c) 1992, 1993 @@ -100,7 +100,7 @@ struct vm_page_md; #define PMAP_VIRTUAL_CACHE_ALIASES #define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)NULL) -#define PMAP_TLB_NEED_SHOOTDOWN +#define PMAP_TLB_NEED_SHOOTDOWN 1 #define PMAP_TLB_FLUSH_ASID_ON_RESET false #if UPAGES > 1 #define PMAP_TLB_WIRED_UPAGES MIPS3_TLB_WIRED_UPAGES
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Tue Jan 4 05:39:12 UTC 2022 Modified Files: src/sys/arch/mips/include: pmap.h Log Message: consistency. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.75 -r1.76 src/sys/arch/mips/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 16 06:04:53 UTC 2021 Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Add some comments for the RDHWR register numbers. To generate a diff of this commit: cvs rdiff -u -r1.114 -r1.115 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/cpuregs.h diff -u src/sys/arch/mips/include/cpuregs.h:1.114 src/sys/arch/mips/include/cpuregs.h:1.115 --- src/sys/arch/mips/include/cpuregs.h:1.114 Tue Nov 16 06:04:00 2021 +++ src/sys/arch/mips/include/cpuregs.h Tue Nov 16 06:04:52 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpuregs.h,v 1.114 2021/11/16 06:04:00 simonb Exp $ */ +/* $NetBSD: cpuregs.h,v 1.115 2021/11/16 06:04:52 simonb Exp $ */ /* * Copyright (c) 2009 Miodrag Vallat. @@ -876,13 +876,13 @@ /* * RDHWR register numbers */ -#define MIPS_HWR_CPUNUM _(0) -#define MIPS_HWR_SYNCI_STEP _(1) -#define MIPS_HWR_CC _(2) -#define MIPS_HWR_CCRES _(3) +#define MIPS_HWR_CPUNUM _(0) /* Which CPU are we on? */ +#define MIPS_HWR_SYNCI_STEP _(1) /* Address step size for SYNCI */ +#define MIPS_HWR_CC _(2) /* Hi-res cycle counter */ +#define MIPS_HWR_CCRES _(3) /* Cycle counter resolution */ #define MIPS_HWR_UL _(29) /* Userlocal */ -#define MIPS_HWR_IMPL30 _(30) -#define MIPS_HWR_IMPL31 _(31) +#define MIPS_HWR_IMPL30 _(30) /* Implementation dependent use */ +#define MIPS_HWR_IMPL31 _(31) /* Implementation dependent use */ /* * Bits defined for HWREna (CP0 register 7, select 0).
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 16 06:04:53 UTC 2021 Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Add some comments for the RDHWR register numbers. To generate a diff of this commit: cvs rdiff -u -r1.114 -r1.115 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 16 06:04:00 UTC 2021 Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Only need one #define for MIPS_HWR_CPUNUM. To generate a diff of this commit: cvs rdiff -u -r1.113 -r1.114 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/cpuregs.h diff -u src/sys/arch/mips/include/cpuregs.h:1.113 src/sys/arch/mips/include/cpuregs.h:1.114 --- src/sys/arch/mips/include/cpuregs.h:1.113 Mon Nov 1 21:28:02 2021 +++ src/sys/arch/mips/include/cpuregs.h Tue Nov 16 06:04:00 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpuregs.h,v 1.113 2021/11/01 21:28:02 andvar Exp $ */ +/* $NetBSD: cpuregs.h,v 1.114 2021/11/16 06:04:00 simonb Exp $ */ /* * Copyright (c) 2009 Miodrag Vallat. @@ -883,7 +883,6 @@ #define MIPS_HWR_UL _(29) /* Userlocal */ #define MIPS_HWR_IMPL30 _(30) #define MIPS_HWR_IMPL31 _(31) -#define MIPS_HWR_CPUNUM _(0) /* * Bits defined for HWREna (CP0 register 7, select 0).
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: simonb Date: Tue Nov 16 06:04:00 UTC 2021 Modified Files: src/sys/arch/mips/include: cpuregs.h Log Message: Only need one #define for MIPS_HWR_CPUNUM. To generate a diff of this commit: cvs rdiff -u -r1.113 -r1.114 src/sys/arch/mips/include/cpuregs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: thorpej
Date: Sat Oct 30 14:05:40 UTC 2021
Modified Files:
src/sys/arch/mips/include: signal.h
Log Message:
Adjust the rules for sigcontext visibility on MIPS:
- Define __HAVE_STRUCT_SIGCONTEXT if _KERNEL (because it's needed for
32-bit binary compatibility) or if the O32 ABI is active (because
that's the only ABI that ever used sigcontext for signal delivery).
- For _KERNEL, define a "struct sigcontext" suitable only for 32-bit
compatible signal delivery.
- For userspace, define a "struct sigcontext" appropriate for any ABI
if _LIBC is defined (it's used for setjmp / longjmp) or if O32 is
the active ABI (because it was part of the old BSD signal API).
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/mips/include/signal.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/signal.h
diff -u src/sys/arch/mips/include/signal.h:1.32 src/sys/arch/mips/include/signal.h:1.33
--- src/sys/arch/mips/include/signal.h:1.32 Wed Oct 27 02:00:46 2021
+++ src/sys/arch/mips/include/signal.h Sat Oct 30 14:05:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: signal.h,v 1.32 2021/10/27 02:00:46 thorpej Exp $ */
+/* $NetBSD: signal.h,v 1.33 2021/10/30 14:05:40 thorpej Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -78,8 +78,12 @@ struct sigcontext13 {
};
#endif /* _KERNEL && COMPAT_13 */
-#if defined(_LIBC) || (defined(_KERNEL) && (defined(COMPAT_16) || defined(COMPAT_ULTRIX)))
+#if defined(_KERNEL) || defined(__mips_o32)
#define __HAVE_STRUCT_SIGCONTEXT
+#endif
+
+#if defined(_NETBSD_SOURCE)
+#include
/*
* Only need an O32 version.
*/
@@ -98,19 +102,17 @@ struct sigcontext { \
}
/*
- * These will be identical in O32
- */
-#ifdef _KERNEL
-/*
- * We need this only compatibility.
+ * The only binaries that used sigcontext used the O32 ABI. The kernel
+ * needs this for 32-bit compatibility, and O32 ABI user-space needs this
+ * natively.
*/
+#if defined(_KERNEL)
_SIGCONTEXT_DEFINE(sigcontext, int, int);
-#endif
-#ifdef _LIBC
+#elif defined(__mips_o32) || defined(_LIBC)
_SIGCONTEXT_DEFINE(sigcontext, __register_t, __fpregister_t);
#endif
-#endif /* _LIBC || _KERNEL */
+#endif /* _NETBSD_SOURCE */
#endif /* !_LANGUAGE_ASSEMBLY */
#endif /* !_MIPS_SIGNAL_H_ */
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: thorpej Date: Sat Oct 30 14:05:40 UTC 2021 Modified Files: src/sys/arch/mips/include: signal.h Log Message: Adjust the rules for sigcontext visibility on MIPS: - Define __HAVE_STRUCT_SIGCONTEXT if _KERNEL (because it's needed for 32-bit binary compatibility) or if the O32 ABI is active (because that's the only ABI that ever used sigcontext for signal delivery). - For _KERNEL, define a "struct sigcontext" suitable only for 32-bit compatible signal delivery. - For userspace, define a "struct sigcontext" appropriate for any ABI if _LIBC is defined (it's used for setjmp / longjmp) or if O32 is the active ABI (because it was part of the old BSD signal API). To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/mips/include/signal.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: thorpej
Date: Wed Oct 27 02:00:46 UTC 2021
Modified Files:
src/sys/arch/mips/include: signal.h
Log Message:
Define __HAVE_STRUCT_SIGCONTEXT for _KERNEL in addition to _LIBC.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/signal.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/signal.h
diff -u src/sys/arch/mips/include/signal.h:1.31 src/sys/arch/mips/include/signal.h:1.32
--- src/sys/arch/mips/include/signal.h:1.31 Tue Oct 26 16:16:35 2021
+++ src/sys/arch/mips/include/signal.h Wed Oct 27 02:00:46 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: signal.h,v 1.31 2021/10/26 16:16:35 christos Exp $ */
+/* $NetBSD: signal.h,v 1.32 2021/10/27 02:00:46 thorpej Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -79,6 +79,7 @@ struct sigcontext13 {
#endif /* _KERNEL && COMPAT_13 */
#if defined(_LIBC) || (defined(_KERNEL) && (defined(COMPAT_16) || defined(COMPAT_ULTRIX)))
+#define __HAVE_STRUCT_SIGCONTEXT
/*
* Only need an O32 version.
*/
@@ -106,7 +107,6 @@ struct sigcontext { \
_SIGCONTEXT_DEFINE(sigcontext, int, int);
#endif
#ifdef _LIBC
-#define __HAVE_STRUCT_SIGCONTEXT
_SIGCONTEXT_DEFINE(sigcontext, __register_t, __fpregister_t);
#endif
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: thorpej Date: Wed Oct 27 02:00:46 UTC 2021 Modified Files: src/sys/arch/mips/include: signal.h Log Message: Define __HAVE_STRUCT_SIGCONTEXT for _KERNEL in addition to _LIBC. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/signal.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src
Committed By: christos
Date: Tue Oct 29 04:55:36 UTC 2019
Modified Files:
src/sys/arch/mips/include: fenv.h
Log Message:
do the pragma dance to avoid -Wshadow
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/fenv.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/fenv.h
diff -u src/sys/arch/mips/include/fenv.h:1.4 src/sys/arch/mips/include/fenv.h:1.5
--- src/sys/arch/mips/include/fenv.h:1.4 Wed Mar 22 19:11:09 2017
+++ src/sys/arch/mips/include/fenv.h Tue Oct 29 00:55:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: fenv.h,v 1.4 2017/03/22 23:11:09 chs Exp $ */
+/* $NetBSD: fenv.h,v 1.5 2019/10/29 04:55:36 christos Exp $ */
/*-
* Copyright (c) 2004-2005 David Schultz
@@ -86,6 +86,11 @@ __wfs(fpu_control_t __fpsr)
__asm __volatile("ctc1 %0,$31" : : "r" (__fpsr));
}
+#if __GNUC_PREREQ__(8, 0)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshadow"
+#endif
+
__fenv_static inline int
feclearexcept(int __excepts)
{
@@ -201,6 +206,10 @@ feupdateenv(const fenv_t *__envp)
return (0);
}
+#if __GNUC_PREREQ__(8, 0)
+#pragma GCC diagnostic pop
+#endif
+
#if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE)
__fenv_static inline int
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: christos Date: Tue Oct 29 04:55:36 UTC 2019 Modified Files: src/sys/arch/mips/include: fenv.h Log Message: do the pragma dance to avoid -Wshadow To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Wed Jun 19 09:55:27 UTC 2019 Modified Files: src/sys/arch/mips/include: mips_param.h Log Message: Whitespace and whitespace consistency To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/mips/include/mips_param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/mips_param.h diff -u src/sys/arch/mips/include/mips_param.h:1.39 src/sys/arch/mips/include/mips_param.h:1.40 --- src/sys/arch/mips/include/mips_param.h:1.39 Sat May 11 06:50:42 2019 +++ src/sys/arch/mips/include/mips_param.h Wed Jun 19 09:55:27 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: mips_param.h,v 1.39 2019/05/11 06:50:42 skrll Exp $ */ +/* $NetBSD: mips_param.h,v 1.40 2019/06/19 09:55:27 skrll Exp $ */ /*- * Copyright (c) 2013 The NetBSD Foundation, Inc. @@ -93,24 +93,24 @@ #define PGSHIFT 12 /* LOG2(NBPG) */ #endif #define NBPG (1 << PGSHIFT) /* bytes/page */ -#define PGOFSET (NBPG-1) /* byte offset into page */ +#define PGOFSET (NBPG - 1) /* byte offset into page */ #define PTPSHIFT 2 -#define PTPLENGTH (PGSHIFT-PTPSHIFT) +#define PTPLENGTH (PGSHIFT - PTPSHIFT) #define NPTEPG (1 << PTPLENGTH) -#define SEGSHIFT (PGSHIFT+PTPLENGTH) /* LOG2(NBSEG) */ -#define NBSEG (1 << SEGSHIFT) /* bytes/segment */ +#define SEGSHIFT (PGSHIFT + PTPLENGTH) /* LOG2(NBSEG) */ +#define NBSEG (1 << SEGSHIFT) /* bytes/segment */ #define SEGOFSET (NBSEG-1) /* byte offset into segment */ #ifdef _LP64 -#define SEGLENGTH (PGSHIFT-3) -#define XSEGSHIFT (SEGSHIFT+SEGLENGTH) /* LOG2(NBXSEG) */ +#define SEGLENGTH (PGSHIFT - 3) +#define XSEGSHIFT (SEGSHIFT + SEGLENGTH) /* LOG2(NBXSEG) */ #define NBXSEG (1UL << XSEGSHIFT) /* bytes/xsegment */ -#define XSEGOFSET (NBXSEG-1) /* byte offset into xsegment */ -#define XSEGLENGTH (PGSHIFT-3) +#define XSEGOFSET (NBXSEG - 1) /* byte offset into xsegment */ +#define XSEGLENGTH (PGSHIFT - 3) #define NXSEGPG (1 << XSEGLENGTH) #else -#define SEGLENGTH (31-SEGSHIFT) +#define SEGLENGTH (31 - SEGSHIFT) #endif #define NSEGPG (1 << SEGLENGTH)
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Wed Jun 19 09:55:27 UTC 2019 Modified Files: src/sys/arch/mips/include: mips_param.h Log Message: Whitespace and whitespace consistency To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/mips/include/mips_param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Sat May 11 06:50:42 UTC 2019 Modified Files: src/sys/arch/mips/include: mips_param.h Log Message: #define for consistency To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/mips/include/mips_param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: skrll Date: Sat May 11 06:50:42 UTC 2019 Modified Files: src/sys/arch/mips/include: mips_param.h Log Message: #define for consistency To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/mips/include/mips_param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/mips_param.h diff -u src/sys/arch/mips/include/mips_param.h:1.38 src/sys/arch/mips/include/mips_param.h:1.39 --- src/sys/arch/mips/include/mips_param.h:1.38 Mon Jul 11 16:15:35 2016 +++ src/sys/arch/mips/include/mips_param.h Sat May 11 06:50:42 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: mips_param.h,v 1.38 2016/07/11 16:15:35 matt Exp $ */ +/* $NetBSD: mips_param.h,v 1.39 2019/05/11 06:50:42 skrll Exp $ */ /*- * Copyright (c) 2013 The NetBSD Foundation, Inc. @@ -98,16 +98,16 @@ #define PTPLENGTH (PGSHIFT-PTPSHIFT) #define NPTEPG (1 << PTPLENGTH) -#define SEGSHIFT (PGSHIFT+PTPLENGTH) /* LOG2(NBSEG) */ +#define SEGSHIFT (PGSHIFT+PTPLENGTH) /* LOG2(NBSEG) */ #define NBSEG (1 << SEGSHIFT) /* bytes/segment */ #define SEGOFSET (NBSEG-1) /* byte offset into segment */ #ifdef _LP64 -#define SEGLENGTH (PGSHIFT-3) +#define SEGLENGTH (PGSHIFT-3) #define XSEGSHIFT (SEGSHIFT+SEGLENGTH) /* LOG2(NBXSEG) */ -#define NBXSEG (1UL << XSEGSHIFT) /* bytes/xsegment */ +#define NBXSEG (1UL << XSEGSHIFT) /* bytes/xsegment */ #define XSEGOFSET (NBXSEG-1) /* byte offset into xsegment */ -#define XSEGLENGTH (PGSHIFT-3) +#define XSEGLENGTH (PGSHIFT-3) #define NXSEGPG (1 << XSEGLENGTH) #else #define SEGLENGTH (31-SEGSHIFT)
Re: CVS commit: src/sys/arch/mips/include
On May 1, 1:46pm, m...@3am-software.com (Matt Thomas) wrote: -- Subject: Re: CVS commit: src/sys/arch/mips/include | | On May 1, 2015, at 11:37 AM, Christos Zoulas chris...@netbsd.org wrote: | | Module Name:src | Committed By: christos | Date: Fri May 1 18:37:40 UTC 2015 | | Modified Files: | src/sys/arch/mips/include: locore.h | | Log Message: | change #error to KASSERT | | | To generate a diff of this commit: | cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/include/locore.h | | This change is incorrect. #error is the right thing for this case. Please read the comment in cpu.h: /* Assume all CPU architectures are valid for LKM's and standlone progs */ You can't have it both ways... I.e. You'll need to make changes to cpu.h if you want to keep #error, or add more ifdefs around it. christos
Re: CVS commit: src/sys/arch/mips/include
On May 2, 2015, at 4:52 AM, Christos Zoulas chris...@zoulas.com wrote: On May 1, 1:46pm, m...@3am-software.com (Matt Thomas) wrote: -- Subject: Re: CVS commit: src/sys/arch/mips/include | | On May 1, 2015, at 11:37 AM, Christos Zoulas chris...@netbsd.org wrote: | | Module Name: src | Committed By: christos | Date: Fri May 1 18:37:40 UTC 2015 | | Modified Files: |src/sys/arch/mips/include: locore.h | | Log Message: | change #error to KASSERT | | | To generate a diff of this commit: | cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/include/locore.h | | This change is incorrect. #error is the right thing for this case. Please read the comment in cpu.h: /* Assume all CPU architectures are valid for LKM's and standlone progs */ You can't have it both ways... I.e. You'll need to make changes to cpu.h if you want to keep #error, or add more ifdefs around it. Not all ABIs run on all CPU architectures. N32/N64 are 64-bit only so you can exclude all MIPS32 and MIPS1/MIPS2 cpus. The ABI for the kernel must be the same as the ABI for modules. This is not a CPU issue as much as an ABI issue. And that’s invariant so #error is correct.
Re: CVS commit: src/sys/arch/mips/include
On May 2, 7:33am, m...@3am-software.com (Matt Thomas) wrote: -- Subject: Re: CVS commit: src/sys/arch/mips/include | Not all ABIs run on all CPU architectures. N32/N64 are 64-bit only | so you can exclude all MIPS32 and MIPS1/MIPS2 cpus. | | The ABI for the kernel must be the same as the ABI for modules. | | This is not a CPU issue as much as an ABI issue. And that=E2=80=99s invari= | ant | so #error is correct. Yes, then the defines in cpu.h are wrong... If we put back #error it will break the build again. christos
re: CVS commit: src/sys/arch/mips/include
If reasonably possible, use MACHINE=MACHINE_ARCH=whatever config.guess uses for the platform. A lot of the different MACHINE values are due to historical reasons annd wouldn't happen again. I think keeping evb* for boards makes sense, though. I agree. MACHINE=evbavr32 and MACHINE_ARCH=avr32 make the most sense. i'm not convinced. i find it annoying that, for instance, RPI is in evbarm. it's not an eval board in the original sense. i don't think having evb prefix buys anything useful, and would rather they were both just avr32. .mrg.
Re: CVS commit: src/sys/arch/mips/include
On May 1, 2015, at 11:37 AM, Christos Zoulas chris...@netbsd.org wrote: Module Name: src Committed By: christos Date: Fri May 1 18:37:40 UTC 2015 Modified Files: src/sys/arch/mips/include: locore.h Log Message: change #error to KASSERT To generate a diff of this commit: cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/include/locore.h This change is incorrect. #error is the right thing for this case.
Re: CVS commit: src/sys/arch/mips/include
On Tue, Jul 22, 2014 at 10:40:02PM +0100, Alexander Nasonov wrote: Matt Thomas wrote: On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned). sljit allocates 64K exec chucks which are managed by a special allocator. You need to run pmap_protect for each chunk. I think it's cheaper to flush icache. Wouldn't it be preferable to have *two* mappings for the code? One which is writeable and another which is executable? Joerg
Re: CVS commit: src/sys/arch/mips/include
On Jul 23, 2014, at 1:46 PM, Joerg Sonnenberger jo...@britannica.bec.de wrote: On Tue, Jul 22, 2014 at 10:40:02PM +0100, Alexander Nasonov wrote: Matt Thomas wrote: On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned). sljit allocates 64K exec chucks which are managed by a special allocator. You need to run pmap_protect for each chunk. I think it's cheaper to flush icache. Wouldn't it be preferable to have *two* mappings for the code? One which is writeable and another which is executable? won’t give you cleaning by the pmap since that’s done by pmap_protect.
Re: CVS commit: src/sys/arch/mips/include
On Jul 22, 2014, at 12:54 PM, Alexander Nasonov al...@netbsd.org wrote: Module Name: src Committed By: alnsn Date: Tue Jul 22 19:54:55 UTC 2014 Modified Files: src/sys/arch/mips/include: sljitarch.h Log Message: Define SLJIT_CACHE_FLUSH() for mips. Actually, this isn't enough. You need to allocate a page of mapped memory as RWX and then when you are done use pmap_protect to change it to RX followed by pmap_update() and the pmap will automagically sync the page for you. Indeed, you must make sure the page containing the code had execute protect which the kmem_* routines won't give you.
Re: CVS commit: src/sys/arch/mips/include
Matt Thomas wrote: On Jul 22, 2014, at 12:54 PM, Alexander Nasonov al...@netbsd.org wrote: Module Name:src Committed By: alnsn Date: Tue Jul 22 19:54:55 UTC 2014 Modified Files: src/sys/arch/mips/include: sljitarch.h Log Message: Define SLJIT_CACHE_FLUSH() for mips. Actually, this isn't enough. You need to allocate a page of mapped memory as RWX and then when you are done use pmap_protect to change it to RX followed by pmap_update() and the pmap will automagically sync the page for you. I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); Alex
Re: CVS commit: src/sys/arch/mips/include
On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: Matt Thomas wrote: On Jul 22, 2014, at 12:54 PM, Alexander Nasonov al...@netbsd.org wrote: Module Name:src Committed By: alnsn Date: Tue Jul 22 19:54:55 UTC 2014 Modified Files: src/sys/arch/mips/include: sljitarch.h Log Message: Define SLJIT_CACHE_FLUSH() for mips. Actually, this isn't enough. You need to allocate a page of mapped memory as RWX and then when you are done use pmap_protect to change it to RX followed by pmap_update() and the pmap will automagically sync the page for you. I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned).
Re: CVS commit: src/sys/arch/mips/include
Matt Thomas wrote: On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned). sljit allocates 64K exec chucks which are managed by a special allocator. You need to run pmap_protect for each chunk. I think it's cheaper to flush icache. Alex
Re: CVS commit: src/sys/arch/mips/include
On Jul 22, 2014, at 2:40 PM, Alexander Nasonov al...@yandex.ru wrote: Matt Thomas wrote: On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned). sljit allocates 64K exec chucks which are managed by a special allocator. You need to run pmap_protect for each chunk. I think it's cheaper to flush icache. Maybe. But I'd prefer executable code to be in read-only pages so that malicious code can't be placed in them and executed. I think trading space for security is a valid tradeoff.
Re: CVS commit: src/sys/arch/mips/include
Matt Thomas wrote: On Jul 22, 2014, at 2:40 PM, Alexander Nasonov al...@yandex.ru wrote: Matt Thomas wrote: On Jul 22, 2014, at 2:27 PM, Alexander Nasonov al...@yandex.ru wrote: I allocate with the X flag and it seems to work: /* in sljitExecAllocator.c */ return (void *)uvm_km_alloc(module_map, size, PAGE_SIZE, UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_EXEC); ok. Then you need don't a hook for cache flushing pmap_protect(vm_map_pamp(module_map), va, size) will do that for you. At least for arm/mips/ppc/vax. (e.g. changing a writeable exec page to read-only automatically causes it exec cleaned). sljit allocates 64K exec chucks which are managed by a special allocator. You need to run pmap_protect for each chunk. I think it's cheaper to flush icache. Maybe. But I'd prefer executable code to be in read-only pages so that malicious code can't be placed in them and executed. I think trading space for security is a valid tradeoff. That would be my preference too but it's not how sljit is designed. The author of sljit doing some refactoring at the moment. I'll ask if he can look into this issue too. Alex
Re: CVS commit: src/sys/arch/mips/include
martin@ wrote: Added Files: src/sys/arch/mips/include: cache_r5900.h Log Message: Restore file for playstation2 accidently overlooked in the big revitilazation Much more r5900 files and #ifdefs have been removed since mips64 merge. http://www.nerv.org/netbsd/?q=id:20110220T074548Z.8dc3e4a80ea6bfb94b5a5334dbda9e5c56fcddea Are they no longer required for new playstation2 port? --- Izumi tsutsui
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: snj Date: Sat Feb 27 19:10:42 UTC 2010 Modified Files: src/sys/arch/mips/include: locore.h Log Message: Fix a couple old typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.80 -r1.81 src/sys/arch/mips/include/locore.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/include/locore.h diff -u src/sys/arch/mips/include/locore.h:1.80 src/sys/arch/mips/include/locore.h:1.81 --- src/sys/arch/mips/include/locore.h:1.80 Mon Dec 14 00:46:04 2009 +++ src/sys/arch/mips/include/locore.h Sat Feb 27 19:10:41 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.h,v 1.80 2009/12/14 00:46:04 matt Exp $ */ +/* $NetBSD: locore.h,v 1.81 2010/02/27 19:10:41 snj Exp $ */ /* * Copyright 1996 The Board of Trustees of The Leland Stanford @@ -16,7 +16,7 @@ /* * Jump table for MIPS CPU locore functions that are implemented * differently on different generations, or instruction-level - * archtecture (ISA) level, the Mips family. + * architecture (ISA) level, the Mips family. * * We currently provide support for MIPS I and MIPS III. */ @@ -308,7 +308,7 @@ }; /* - * The active locore-fuction vector, and + * The active locore-function vector, and */ extern mips_locore_jumpvec_t mips_locore_jumpvec; extern struct locoresw mips_locoresw;
CVS commit: src/sys/arch/mips/include
Module Name:src Committed By: snj Date: Sat Feb 27 19:10:42 UTC 2010 Modified Files: src/sys/arch/mips/include: locore.h Log Message: Fix a couple old typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.80 -r1.81 src/sys/arch/mips/include/locore.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
