CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Fri Jul 7 04:43:15 UTC 2023
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
tprof(8): Add support for Skylake-X and Cascade Lake.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.18 src/usr.sbin/tprof/arch/tprof_x86.c:1.19
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.18 Fri Jul 7 04:37:03 2023
+++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Jul 7 04:43:15 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.18 2023/07/07 04:37:03 msaitoh Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.19 2023/07/07 04:43:15 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -529,11 +529,276 @@ init_intel_skylake_kabylake(void)
return _skylake_kabylake;
}
+/*
+ * Intel Skylake-X (and Cascade Lake).
+ */
+static struct name_to_event intel_skylake_x_names[] = {
+ { "INST_RETIRED.ANY",0x00, 0x01, true },
+ { "CPU_CLK_UNHALTED.THREAD", 0x00, 0x02, true },
+ { "CPU_CLK_UNHALTED.REF_TSC", 0x00, 0x03, true },
+ { "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
+ { "LD_BLOCKS.NO_SR",0x03, 0x08, true },
+ { "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 0x07, 0x01, true },
+ { "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 0x08, 0x08, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED", 0x08, 0x0E, true },
+ { "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
+ { "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
+ { "INT_MISC.RECOVERY_CYCLES", 0x0D, 0x01, true },
+ { "INT_MISC.CLEAR_RESTEER_CYCLES", 0x0D, 0x80, true },
+ { "UOPS_ISSUED.ANY",0x0E, 0x01, true },
+ { "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 0x0E, 0x02, true },
+ { "UOPS_ISSUED.SLOW_LEA", 0x0E, 0x20, true },
+ { "ARITH.DIVIDER_ACTIVE", 0x14, 0x01, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_MISS", 0x24, 0x21, true },
+ { "L2_RQSTS.RFO_MISS",0x24, 0x22, true },
+ { "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
+ { "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
+ { "L2_RQSTS.PF_MISS",0x24, 0x38, true },
+ { "L2_RQSTS.MISS",0x24, 0x3F, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_HIT", 0x24, 0x41, true },
+ { "L2_RQSTS.RFO_HIT",0x24, 0x42, true },
+ { "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
+ { "L2_RQSTS.PF_HIT",0x24, 0xD8, true },
+ { "L2_RQSTS.ALL_DEMAND_DATA_RD", 0x24, 0xE1, true },
+ { "L2_RQSTS.ALL_RFO",0x24, 0xE2, true },
+ { "L2_RQSTS.ALL_CODE_RD", 0x24, 0xE4, true },
+ { "L2_RQSTS.ALL_DEMAND_REFERENCES", 0x24, 0xE7, true },
+ { "L2_RQSTS.ALL_PF",0x24, 0xF8, true },
+ { "L2_RQSTS.REFERENCES All L2", 0x24, 0xFF, true },
+ { "CORE_POWER.LVL0_TURBO_LICENSE", 0x28, 0x07, true },
+ { "CORE_POWER.LVL1_TURBO_LICENSE", 0x28, 0x18, true },
+ { "CORE_POWER.LVL2_TURBO_LICENSE", 0x28, 0x20, true },
+ { "CORE_POWER.THROTTLE", 0x28, 0x40, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
+ { "CPU_CLK_UNHALTED.THREAD_P", 0x3C, 0x00, true },
+ { "CPU_CLK_THREAD_UNHALTED.REF_XCLK", 0x3C, 0x01, true },
+ { "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
+ { "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
+ { "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
+ { "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED", 0x49, 0x0E, true },
+ { "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
+ { "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
+ { "LOAD_HIT_PRE.SW_PF",0x4C, 0x01, true },
+ { "EPT.WALK_PENDING",0x4F, 0x10, true },
+ { "L1D.REPLACEMENT",0x51, 0x01, true },
+ { "TX_MEM.ABORT_CONFLICT", 0x54, 0x01, true },
+ { "TX_MEM.ABORT_CAPACITY", 0x54, 0x02, true },
+ { "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 0x54, 0x04, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 0x54, 0x08, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 0x54, 0x10, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
+ 0x54, 0x20, true },
+ { "TX_MEM.HLE_ELISION_BUFFER_FULL", 0x54, 0x40, true },
+ { "TX_EXEC.MISC1",0x5D, 0x01, true },
+ { "TX_EXEC.MISC2",0x5D, 0x02, true },
+ { "TX_EXEC.MISC3",0x5D, 0x04, true },
+ { "TX_EXEC.MISC4",0x5D, 0x08, true },
+ { "TX_EXEC.MISC5",0x5D, 0x10, true },
+ { "RS_EVENTS.EMPTY_CYCLES", 0x5E, 0x01, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+ 0x60, 0x01, true },
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Fri Jul 7 04:43:15 UTC 2023 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: tprof(8): Add support for Skylake-X and Cascade Lake. To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Fri Jul 7 04:37:03 UTC 2023 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Modify comment. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/tprof/arch/tprof_x86.c diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.17 src/usr.sbin/tprof/arch/tprof_x86.c:1.18 --- src/usr.sbin/tprof/arch/tprof_x86.c:1.17 Wed Apr 12 02:15:51 2023 +++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Jul 7 04:37:03 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: tprof_x86.c,v 1.17 2023/04/12 02:15:51 msaitoh Exp $ */ +/* $NetBSD: tprof_x86.c,v 1.18 2023/07/07 04:37:03 msaitoh Exp $ */ /* * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. @@ -570,10 +570,10 @@ init_intel_generic(void) break; case 0x4e: /* Skylake */ case 0x5e: /* Skylake */ - case 0x8e: /* Kabylake */ - case 0x9e: /* Kabylake */ - case 0xa5: /* Cometlake */ - case 0xa6: /* Cometlake */ + case 0x8e: /* Kaby Lake */ + case 0x9e: /* Kaby Lake */ + case 0xa5: /* Comet Lake */ + case 0xa6: /* Comet Lake */ table->next = init_intel_skylake_kabylake(); break; }
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Fri Jul 7 04:37:03 UTC 2023 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Modify comment. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Wed Apr 12 02:15:51 UTC 2023
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
KNF. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.16 src/usr.sbin/tprof/arch/tprof_x86.c:1.17
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.16 Mon Apr 10 06:08:56 2023
+++ src/usr.sbin/tprof/arch/tprof_x86.c Wed Apr 12 02:15:51 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.16 2023/04/10 06:08:56 msaitoh Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.17 2023/04/12 02:15:51 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -60,7 +60,8 @@ struct event_table {
static struct event_table *cpuevents = NULL;
-static void x86_cpuid(unsigned int *eax, unsigned int *ebx,
+static void
+x86_cpuid(unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
{
asm volatile("cpuid"
@@ -429,7 +430,7 @@ static struct name_to_event intel_skylak
{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
{ "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
{ "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
- 0x60, 0x10, true },
+ 0x60, 0x10, true },
{ "IDQ.MITE_UOPS",0x79, 0x04, true },
{ "IDQ.DSB_UOPS",0x79, 0x08, true },
{ "IDQ.MS_MITE_UOPS",0x79, 0x20, true },
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Wed Apr 12 02:15:51 UTC 2023 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Thu Dec 8 02:12:18 UTC 2022 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Use lowercase consistently for hexadecimal numbers. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Thu Dec 8 02:12:18 UTC 2022
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Use lowercase consistently for hexadecimal numbers. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.13 src/usr.sbin/tprof/arch/tprof_x86.c:1.14
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.13 Wed Dec 7 08:11:49 2022
+++ src/usr.sbin/tprof/arch/tprof_x86.c Thu Dec 8 02:12:18 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.13 2022/12/07 08:11:49 msaitoh Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.14 2022/12/08 02:12:18 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -78,14 +78,14 @@ static void x86_cpuid(unsigned int *eax,
*/
static struct name_to_event intel_arch1_names[] = {
/* Event Name - Event Select - UMask */
- { "unhalted-core-cycles", 0x3C, 0x00, true },
- { "instruction-retired", 0xC0, 0x00, true },
- { "unhalted-reference-cycles", 0x3C, 0x01, true },
- { "llc-reference", 0x2E, 0x4F, true },
- { "llc-misses", 0x2E, 0x41, true },
- { "branch-instruction-retired", 0xC4, 0x00, true },
- { "branch-misses-retired", 0xC5, 0x00, true },
- { "topdown-slots", 0xA4, 0x01, true },
+ { "unhalted-core-cycles", 0x3c, 0x00, true },
+ { "instruction-retired", 0xc0, 0x00, true },
+ { "unhalted-reference-cycles", 0x3c, 0x01, true },
+ { "llc-reference", 0x2e, 0x4f, true },
+ { "llc-misses", 0x2e, 0x41, true },
+ { "branch-instruction-retired", 0xc4, 0x00, true },
+ { "branch-misses-retired", 0xc5, 0x00, true },
+ { "topdown-slots", 0xa4, 0x01, true },
};
static struct event_table intel_arch1 = {
@@ -103,7 +103,7 @@ init_intel_arch1(void)
struct event_table *table;
size_t i;
- eax = 0x0A;
+ eax = 0x0a;
ebx = 0;
ecx = 0;
edx = 0;
@@ -150,53 +150,53 @@ static struct name_to_event intel_silver
{ "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
{ "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
{ "PAGE_WALKS.WALKS", 0x05, 0x03, true },
- { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
- { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2e, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2e, 0x4f, true },
{ "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
{ "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
- { "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
- { "CPU_CLK_UNHALTED.REF_P", 0x3C, 0x01, true },
+ { "CPU_CLK_UNHALTED.CORE_P", 0x3c, 0x00, true },
+ { "CPU_CLK_UNHALTED.REF_P", 0x3c, 0x01, true },
{ "ICACHE.HIT",0x80, 0x01, true },
{ "ICACHE.MISSES", 0x80, 0x02, true },
{ "ICACHE.ACCESSES", 0x80, 0x03, true },
- { "OFFCORE_RESPONSE_0", 0xB7, 0x01, true },
- { "OFFCORE_RESPONSE_1", 0xB7, 0x02, true },
- { "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
- { "UOPS_RETIRED.MS", 0xC2, 0x01, true },
- { "UOPS_RETIRED.ALL", 0xC2, 0x10, true },
- { "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
- { "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
- { "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
- { "MACHINE_CLEARS.ALL", 0xC3, 0x08, true },
- { "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
- { "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
- { "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
- { "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
- { "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
- { "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
- { "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
- { "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
- { "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
- { "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
- { "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
- { "BR_MISP_RETIRED.FAR", 0xC5, 0xBF, true },
- { "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
- { "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
- { "BR_MISP_RETIRED.CALL", 0xC5, 0xF9, true },
- { "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
- { "BR_MISP_RETIRED.REL_CALL", 0xC5, 0xFD, true },
- { "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
- { "NO_ALLOC_CYCLES.ROB_FULL", 0xCA, 0x01, true },
- { "NO_ALLOC_CYCLES.RAT_STALL", 0xCA, 0x20, true },
- { "NO_ALLOC_CYCLES.ALL", 0xCA, 0x3F, true },
- { "NO_ALLOC_CYCLES.NOT_DELIVERED", 0xCA, 0x50, true },
- { "RS_FULL_STALL.MEC", 0xCB, 0x01, true },
- { "RS_FULL_STALL.ALL", 0xCB, 0x1F, true },
- { "CYCLES_DIV_BUSY.ANY", 0xCD, 0x01, true },
- { "BACLEARS.ALL", 0xE6, 0x01, true },
- { "BACLEARS.RETURN", 0xE6, 0x08, true },
- { "BACLEARS.COND", 0xE6, 0x10, true },
- { "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
+ { "OFFCORE_RESPONSE_0", 0xb7, 0x01, true },
+ { "OFFCORE_RESPONSE_1", 0xb7, 0x02, true },
+ { "INST_RETIRED.ANY_P", 0xc0, 0x00, true },
+ {
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Wed Dec 7 08:11:49 UTC 2022
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
KNF. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.12 src/usr.sbin/tprof/arch/tprof_x86.c:1.13
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.12 Mon Jun 13 09:28:58 2022
+++ src/usr.sbin/tprof/arch/tprof_x86.c Wed Dec 7 08:11:49 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.12 2022/06/13 09:28:58 msaitoh Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.13 2022/12/07 08:11:49 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -71,7 +71,7 @@ static void x86_cpuid(unsigned int *eax,
: "0" (*eax), "2" (*ecx));
}
-/* -- */
+/* - */
/*
* Intel Architectural Version 1.
@@ -374,142 +374,143 @@ init_intel_goldmontplus(void)
*/
static struct name_to_event intel_skylake_kabylake_names[] = {
/* Event Name - Event Select - UMask */
- { "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
- { "LD_BLOCKS.NO_SR", 0x03, 0x08, true },
- { "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",0x07, 0x01, true },
- { "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",0x08, 0x02, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",0x08, 0x08, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED",0x08, 0x0E, true },
- { "DTLB_LOAD_MISSES.WALK_PENDING",0x08, 0x10, true },
- { "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
- { "INT_MISC.RECOVERY_CYCLES", 0x0D, 0x01, true },
- { "INT_MISC.CLEAR_RESTEER_CYCLES",0x0D, 0x80, true },
- { "UOPS_ISSUED.ANY", 0x0E, 0x01, true },
- { "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",0x0E, 0x02, true },
- { "UOPS_ISSUED.SLOW_LEA", 0x0E, 0x20, true },
- { "L2_RQSTS.DEMAND_DATA_RD_MISS",0x24, 0x21, true },
- { "L2_RQSTS.RFO_MISS", 0x24, 0x22, true },
- { "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
- { "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
- { "L2_RQSTS.PF_MISS", 0x24, 0x38, true },
- { "L2_RQSTS.MISS", 0x24, 0x3F, true },
- { "L2_RQSTS.DEMAND_DATA_RD_HIT",0x24, 0x41, true },
- { "L2_RQSTS.RFO_HIT", 0x24, 0x42, true },
- { "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
- { "L2_RQSTS.PF_HIT", 0x24, 0xD8, true },
- { "L2_RQSTS.ALL_DEMAND_DATA_RD",0x24, 0xE1, true },
- { "L2_RQSTS.ALL_RFO", 0x24, 0xE2, true },
- { "L2_RQSTS.ALL_CODE_RD", 0x24, 0xE4, true },
- { "L2_RQSTS.ALL_DEMAND_REFERENCES",0x24, 0xE7, true },
- { "L2_RQSTS.ALL_PF", 0x24, 0xF8, true },
- { "L2_RQSTS.REFERENCES", 0x24, 0xFF, true },
- { "SW_PREFETCH_ACCESS.NTA", 0x32, 0x01, true },
- { "SW_PREFETCH_ACCESS.T0", 0x32, 0x02, true },
- { "SW_PREFETCH_ACCESS.T1_T2", 0x32, 0x04, true },
- { "SW_PREFETCH_ACCESS.PREFETCHW",0x32, 0x08, true },
- { "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
- { "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",0x3C, 0x02, true },
- { "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
- { "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
- { "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED",0x49, 0x0E, true },
- { "DTLB_STORE_MISSES.WALK_PENDING",0x49, 0x10, true },
- { "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
- { "LOAD_HIT_PRE.SW_PF", 0x4C, 0x01, true },
- { "EPT.WALK_PENDING", 0x4F, 0x10, true },
- { "L1D.REPLACEMENT", 0x51, 0x01, true },
- { "RS_EVENTS.EMPTY_CYCLES", 0x5E, 0x01, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 0x60, 0x01, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 0x60, 0x02, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 0x60, 0x10, true },
- { "IDQ.MITE_UOPS", 0x79, 0x04, true },
- { "IDQ.DSB_UOPS", 0x79, 0x08, true },
- { "IDQ.MS_MITE_UOPS", 0x79, 0x20, true },
- { "IDQ.MS_UOPS", 0x79, 0x30, true },
- { "ICACHE_16B.IFDATA_STALL", 0x80, 0x04, true },
- { "ICACHE_64B.IFTAG_HIT", 0x83, 0x01, true },
- { "ICACHE_64B.IFTAG_MISS", 0x83, 0x02, true },
- { "ICACHE_64B.IFTAG_STALL", 0x83, 0x04, true },
- {
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Wed Dec 7 08:11:49 UTC 2022 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Mon Jun 13 09:28:58 UTC 2022
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Disable the unsupported events from the bit vector length in EAX.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.11 src/usr.sbin/tprof/arch/tprof_x86.c:1.12
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.11 Mon Jun 13 07:40:58 2022
+++ src/usr.sbin/tprof/arch/tprof_x86.c Mon Jun 13 09:28:58 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.11 2022/06/13 07:40:58 msaitoh Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.12 2022/06/13 09:28:58 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -99,7 +99,7 @@ static struct event_table intel_arch1 =
static struct event_table *
init_intel_arch1(void)
{
- unsigned int eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx, vectorlen;
struct event_table *table;
size_t i;
@@ -109,9 +109,17 @@ init_intel_arch1(void)
edx = 0;
x86_cpuid(, , , );
+ vectorlen = __SHIFTOUT(eax, CPUID_PERF_BVECLEN);
+
table = _arch1;
for (i = 0; i < table->nevents; i++) {
- /* Disable the unsupported events. */
+ /*
+ * Disable the unsupported events from:
+ * a) the bit vector length in EAX.
+ * b) the disable bit in EBX.
+ */
+ if (i >= vectorlen)
+ table->names[i].enabled = false;
if ((ebx & (i << 1)) != 0)
table->names[i].enabled = false;
}
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Mon Jun 13 09:28:58 UTC 2022 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Disable the unsupported events from the bit vector length in EAX. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: msaitoh
Date: Mon Jun 13 07:40:58 UTC 2022
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Add topdown-slots to Intel architectural performance monitoring version 1.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.10 src/usr.sbin/tprof/arch/tprof_x86.c:1.11
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.10 Fri Apr 17 03:15:50 2020
+++ src/usr.sbin/tprof/arch/tprof_x86.c Mon Jun 13 07:40:58 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.10 2020/04/17 03:15:50 knakahara Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.11 2022/06/13 07:40:58 msaitoh Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -85,6 +85,7 @@ static struct name_to_event intel_arch1_
{ "llc-misses", 0x2E, 0x41, true },
{ "branch-instruction-retired", 0xC4, 0x00, true },
{ "branch-misses-retired", 0xC5, 0x00, true },
+ { "topdown-slots", 0xA4, 0x01, true },
};
static struct event_table intel_arch1 = {
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: msaitoh Date: Mon Jun 13 07:40:58 UTC 2022 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Add topdown-slots to Intel architectural performance monitoring version 1. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: jmcneill
Date: Fri Oct 11 18:05:52 UTC 2019
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Add support for AMD Family 15h
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.8 src/usr.sbin/tprof/arch/tprof_x86.c:1.9
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.8 Wed May 29 17:09:18 2019
+++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Oct 11 18:05:52 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.8 2019/05/29 17:09:18 maxv Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.9 2019/10/11 18:05:52 jmcneill Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -655,6 +655,120 @@ static struct event_table amd_f10h = {
};
/*
+ * AMD Family 15h
+ */
+static struct name_to_event amd_f15h_names[] = {
+ { "FpPipeAssignment", 0x000, 0x77, true },
+ { "FpSchedulerEmpty", 0x001, 0x00, true },
+ { "FpRetSseAvxOps", 0x003, 0xff, true },
+ { "FpNumMovElim", 0x004, 0x0f, true },
+ { "FpRetiredSerOps", 0x005, 0x0f, true },
+ { "LsSegRegLoads", 0x020, 0x7f, true },
+ { "LsPipeRestartSelfMod", 0x021, 0x00, true },
+ { "LsPipeRestartVarious", 0x022, 0x1f, true },
+ { "LsLoadQueueStoreQFull", 0x023, 0x03, true },
+ { "LsLockedOps", 0x024, 0x00, true },
+ { "LsRetClflushInstr", 0x026, 0x00, true },
+ { "LsRetCpuidInstr", 0x027, 0x00, true },
+ { "LsDispatch", 0x029, 0x07, true },
+ { "LsCanStoreToLoadFwOps", 0x02a, 0x03, true },
+ { "LsSmisReceived", 0x02b, 0x00, true },
+ { "LsExecClflushInstr", 0x030, 0x00, true },
+ { "LsMisalignStore", 0x032, 0x00, true },
+ { "LsFpLoadBufStall", 0x034, 0x00, true },
+ { "LsStlf", 0x035, 0x00, true },
+ { "DcCacheAccess", 0x040, 0x00, true },
+ { "DcCacheMiss", 0x041, 0x00, true },
+ { "DcCacheFillL2Sys", 0x042, 0x1f, true },
+ { "DcCacheFillSys", 0x043, 0x00, true },
+ { "DcUnifiedTlbHit", 0x045, 0x77, true },
+ { "DcUnifiedTlbMiss", 0x046, 0x77, true },
+ { "DcMisalignAccess", 0x047, 0x00, true },
+ { "DcPrefetchInstrDisp", 0x04b, 0x07, true },
+ { "DcIneffSwPrefetch", 0x052, 0x09, true },
+ { "CuCmdVictimBuf", 0x060, 0x98, true },
+ { "CuCmdMaskedOps", 0x061, 0x65, true },
+ { "CuCmdReadBlkOps", 0x062, 0x77, true },
+ { "CuCmdChgDirtyOps", 0x063, 0x08, true },
+ { "CuDramSysReq", 0x064, 0x00, true },
+ { "CuMemReqByType", 0x065, 0x83, true },
+ { "CuDataCachePrefetch", 0x067, 0x03, true },
+ { "CuMabReq", 0x068, 0xff, true },
+ { "CuMabWaitCyc", 0x069, 0xff, true },
+ { "CuSysRespCacheFill", 0x06c, 0x3f, true },
+ { "CuOctwordsWritten", 0x06d, 0x01, true },
+ { "CuCacheXInv", 0x075, 0x0f, true },
+ { "CuCpuClkNotHalted", 0x076, 0x00, true },
+ { "CuL2Req", 0x07d, 0x5f, true },
+ { "CuL2Miss", 0x07e, 0x17, true },
+ { "CuL2FillWb", 0x07f, 0x07, true },
+ { "CuPageSplintering", 0x165, 0x07, true },
+ { "CuL2PrefetchTrigEv", 0x16c, 0x03, true },
+ { "CuXabAllocStall", 0x177, 0x03, true },
+ { "CuFreeXabEntries", 0x17f, 0x01, true },
+ { "IcCacheFetch", 0x080, 0x00, true },
+ { "IcCacheMiss", 0x081, 0x00, true },
+ { "IcCacheFillL2", 0x082, 0x00, true },
+ { "IcCacheFillSys", 0x083, 0x00, true },
+ { "IcL1TlbMissL2Hit", 0x084, 0x00, true },
+ { "IcL1TlbMissL2Miss", 0x085, 0x07, true },
+ { "IcPipeRestartInstrStrProbe", 0x086, 0x00, true },
+ { "IcFetchStall", 0x087, 0x00, true },
+ { "IcRetStackHits", 0x088, 0x00, true },
+ { "IcRetStackOver", 0x089, 0x00, true },
+ { "IcCacheVictims", 0x08b, 0x00, true },
+ { "IcCacheLinesInv", 0x08c, 0x0f, true },
+ { "IcTlbReload", 0x099, 0x00, true },
+ { "IcTlbReloadAbort", 0x09a, 0x00, true },
+ { "IcUopsDispatched", 0x186, 0x01, true },
+ { "ExRetInstr", 0x0c0, 0x00, true },
+ { "ExRetCops", 0x0c1, 0x00, true },
+ { "ExRetBrn", 0x0c2, 0x00, true },
+ { "ExRetBrnMisp", 0x0c3, 0x00, true },
+ { "ExRetBrnTkn", 0x0c4, 0x00, true },
+ { "ExRetBrnTknMisp", 0x0c5, 0x00, true },
+ { "ExRetBrnFar", 0x0c6, 0x00, true },
+ { "ExRetBrnResync", 0x0c7, 0x00, true },
+ { "ExRetNearRet", 0x0c8, 0x00, true },
+ { "ExRetNearRetMispred", 0x0c9, 0x00, true },
+ { "ExRetBrnIndMisp", 0x0ca, 0x00, true },
+ { "ExRetMmxFpInstr@X87", 0x0cb, 0x01, true },
+ { "ExRetMmxFpInstr@Mmx", 0x0cb, 0x02, true },
+ { "ExRetMmxFpInstr@Sse", 0x0cb, 0x04, true },
+ { "ExIntMaskedCyc", 0x0cd, 0x00, true },
+ { "ExIntMaskedCycIntPend", 0x0ce, 0x00, true },
+ { "ExIntTaken", 0x0cf, 0x00, true },
+ { "ExDecEmpty", 0x0d0, 0x00, true },
+ { "ExDispStall", 0x0d1, 0x00, true },
+ { "ExUseqStallSer", 0x0d2, 0x00, true },
+ { "ExDispStallInstrRetQFull", 0x0d5, 0x00, true },
+ { "ExDispStallIntSchedQFull", 0x0d6, 0x00, true },
+ { "ExDispStallFpSchedQFull", 0x0d7, 0x00, true },
+ { "ExDispStallLdqFull", 0x0d8, 0x00, true },
+ { "ExUseqStallAllQuiet", 0x0d9, 0x00, true },
+ {
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: jmcneill Date: Fri Oct 11 18:05:52 UTC 2019 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Add support for AMD Family 15h To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
