CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Thu Mar 27 23:21:36 UTC 2014 Modified Files: src/sys/arch/arm/cortex [matt-nb5-mips64]: a9_mpsubr.S Log Message: Don't = since that isn't BE8 friendly To generate a diff of this commit: cvs rdiff -u -r1.12.2.5 -r1.12.2.6 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.5 src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.6 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.5 Wed Mar 26 02:13:54 2014 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Thu Mar 27 23:21:36 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.12.2.5 2014/03/26 02:13:54 matt Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.12.2.6 2014/03/27 23:21:36 matt Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -341,7 +341,7 @@ cortex_init: bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache #else adr ip, cortex_init - ldr r0, =armv7_icache_inv_all + ldr r0, .Larmv7_icache_inv_all bfi ip, r0, #0, #28 blx ip #endif @@ -370,7 +370,7 @@ cortex_init: bl _C_LABEL(armv7_dcache_wbinv_all) @ writeback/invalidate d-cache #else adr ip, cortex_init - ldr r0, =armv7_dcache_wbinv_all + ldr r0, .Larmv7_dcache_wbinv_all bfi ip, r0, #0, #28 blx ip #endif @@ -401,7 +401,7 @@ cortex_init: bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache #else adr ip, cortex_init - ldr r0, =armv7_icache_inv_all + ldr r0, .Larmv7_icache_inv_all bfi ip, r0, #0, #28 blx ip #endif @@ -432,6 +432,13 @@ cortex_init: #endif bx r10 + +#ifndef KERNEL_BASES_EQUAL +.Larmv7_icache_inv_all: + .word armv7_icache_inv_all +.Larmv7_dcache_wbinv_all: + .word armv7_dcache_wbinv_all +#endif ASEND(a9_start) /*
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src
Committed By: matt
Date: Wed Mar 26 01:59:08 UTC 2014
Modified Files:
src/sys/arch/arm/cortex [matt-nb5-mips64]: gic.c
Log Message:
Let bus_space so the endian conversion if needed
To generate a diff of this commit:
cvs rdiff -u -r1.5.2.2 -r1.5.2.3 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.5.2.2 src/sys/arch/arm/cortex/gic.c:1.5.2.3
--- src/sys/arch/arm/cortex/gic.c:1.5.2.2 Sat Feb 15 16:18:36 2014
+++ src/sys/arch/arm/cortex/gic.c Wed Mar 26 01:59:08 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.5.2.2 2014/02/15 16:18:36 matt Exp $ */
+/* $NetBSD: gic.c,v 1.5.2.3 2014/03/26 01:59:08 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.5.2.2 2014/02/15 16:18:36 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.5.2.3 2014/03/26 01:59:08 matt Exp $);
#include sys/param.h
#include sys/bus.h
@@ -109,28 +109,24 @@ __CTASSERT(NIPL == 8);
static inline uint32_t
gicc_read(struct armgic_softc *sc, bus_size_t o)
{
- uint32_t v = bus_space_read_4(sc-sc_memt, sc-sc_gicch, o);
- return le32toh(v);
+ return bus_space_read_4(sc-sc_memt, sc-sc_gicch, o);
}
static inline void
gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
{
- v = htole32(v);
bus_space_write_4(sc-sc_memt, sc-sc_gicch, o, v);
}
static inline uint32_t
gicd_read(struct armgic_softc *sc, bus_size_t o)
{
- uint32_t v = bus_space_read_4(sc-sc_memt, sc-sc_gicdh, o);
- return le32toh(v);
+ return bus_space_read_4(sc-sc_memt, sc-sc_gicdh, o);
}
static inline void
gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v)
{
- v = htole32(v);
bus_space_write_4(sc-sc_memt, sc-sc_gicdh, o, v);
}
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Wed Mar 26 02:13:54 UTC 2014 Modified Files: src/sys/arch/arm/cortex [matt-nb5-mips64]: a9_mpsubr.S Log Message: flush the icache after enabling the SCU To generate a diff of this commit: cvs rdiff -u -r1.12.2.4 -r1.12.2.5 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.4 src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.5 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.4 Mon Mar 24 18:44:13 2014 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Wed Mar 26 02:13:54 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.12.2.4 2014/03/24 18:44:13 matt Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.12.2.5 2014/03/26 02:13:54 matt Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -397,13 +397,23 @@ cortex_init: isb XPUTC(#50) +#ifdef KERNEL_BASES_EQUAL + bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache +#else + adr ip, cortex_init + ldr r0, =armv7_icache_inv_all + bfi ip, r0, #0, #28 + blx ip +#endif + XPUTC(#51) + /* * Step 4a, enable the data cache */ orr r2, r2, #CPU_CONTROL_DC_ENABLE @ set data cache enable mcr p15, 0, r2, c1, c0, 0 @ reenable caches isb - XPUTC(#51) + XPUTC(#52) #endif /*
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Mon Mar 24 18:44:13 UTC 2014 Modified Files: src/sys/arch/arm/cortex [matt-nb5-mips64]: a9_mpsubr.S Log Message: Allow A7 to use this. To generate a diff of this commit: cvs rdiff -u -r1.12.2.3 -r1.12.2.4 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.3 src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.4 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.3 Thu Feb 20 20:36:29 2014 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Mon Mar 24 18:44:13 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.12.2.3 2014/02/20 20:36:29 matt Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.12.2.4 2014/03/24 18:44:13 matt Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -330,15 +330,23 @@ comlock: #endif /* MULTIPROCESSOR */ #endif /* VERBOSE_INIT_ARM */ -#ifdef CPU_CORTEXA9 a9_start: +cortex_init: mov r10, lr@ save lr cpsid if, #PSR_SVC32_MODE XPUTC(#64) +#ifdef KERNEL_BASES_EQUAL bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache +#else + adr ip, cortex_init + ldr r0, =armv7_icache_inv_all + bfi ip, r0, #0, #28 + blx ip +#endif +#ifdef CPU_CORTEXA9 /* * Step 1a, invalidate the all cache tags in all ways on the SCU. */ @@ -352,14 +360,23 @@ a9_start: str r1, [r3, #SCU_INV_ALL_REG] @ write scu invalidate all dsb isb +#endif /* * Step 1b, invalidate the data cache */ XPUTC(#66) +#ifdef KERNEL_BASES_EQUAL bl _C_LABEL(armv7_dcache_wbinv_all) @ writeback/invalidate d-cache +#else + adr ip, cortex_init + ldr r0, =armv7_dcache_wbinv_all + bfi ip, r0, #0, #28 + blx ip +#endif XPUTC(#67) +#ifdef CPU_CORTEXA9 /* * Step 2, disable the data cache */ @@ -387,8 +404,8 @@ a9_start: mcr p15, 0, r2, c1, c0, 0 @ reenable caches isb XPUTC(#51) +#endif -#ifdef MULTIPROCESSOR /* * Step 4b, set ACTLR.SMP=1 (and ACTRL.FX=1) */ @@ -396,6 +413,8 @@ a9_start: orr r0, r0, #CORTEXA9_AUXCTL_SMP @ enable SMP mcr p15, 0, r0, c1, c0, 1 @ write aux ctl isb +#ifdef CPU_CORTEXA9 + mrc p15, 0, r0, c1, c0, 1 @ read aux ctl orr r0, r0, #CORTEXA9_AUXCTL_FW @ enable cache/tlb/coherency mcr p15, 0, r0, c1, c0, 1 @ write aux ctl isb @@ -526,4 +545,3 @@ ASEND(a9_mpstart) .Lbcm53xx_cpu_hatch: .word _C_LABEL(bcm53xx_cpu_hatch) #endif /* MULTIPROCESSOR */ -#endif /* CPU_CORTEXA9 */
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Thu Feb 20 20:36:29 UTC 2014 Modified Files: src/sys/arch/arm/cortex [matt-nb5-mips64]: a9_mpsubr.S Log Message: Use right register when setting ttbr To generate a diff of this commit: cvs rdiff -u -r1.12.2.2 -r1.12.2.3 src/sys/arch/arm/cortex/a9_mpsubr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/a9_mpsubr.S diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.2 src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.3 --- src/sys/arch/arm/cortex/a9_mpsubr.S:1.12.2.2 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/cortex/a9_mpsubr.S Thu Feb 20 20:36:29 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: a9_mpsubr.S,v 1.12.2.2 2014/02/15 16:18:36 matt Exp $ */ +/* $NetBSD: a9_mpsubr.S,v 1.12.2.3 2014/02/20 20:36:29 matt Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -178,7 +178,7 @@ arm_cpuinit: cmp r1, #0 orrlt r10, r10, #0x5b /* MP, cachable (Normal WB) */ orrge r10, r10, #0x1b /* Non-MP, cacheable, normal WB */ - mcr p15, 0, r1, c2, c0, 0 /* Set Translation Table Base */ + mcr p15, 0, r10, c2, c0, 0 /* Set Translation Table Base */ XPUTC(#49) mov r1, #0
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/cortex
Module Name:src Committed By: matt Date: Wed Feb 19 23:18:40 UTC 2014 Modified Files: src/sys/arch/arm/cortex [matt-nb5-mips64]: files.cortex Log Message: arml2cc - needs-flag To generate a diff of this commit: cvs rdiff -u -r1.4.6.2 -r1.4.6.3 src/sys/arch/arm/cortex/files.cortex Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/files.cortex diff -u src/sys/arch/arm/cortex/files.cortex:1.4.6.2 src/sys/arch/arm/cortex/files.cortex:1.4.6.3 --- src/sys/arch/arm/cortex/files.cortex:1.4.6.2 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/cortex/files.cortex Wed Feb 19 23:18:40 2014 @@ -1,4 +1,4 @@ -# $NetBSD: files.cortex,v 1.4.6.2 2014/02/15 16:18:36 matt Exp $ +# $NetBSD: files.cortex,v 1.4.6.3 2014/02/19 23:18:40 matt Exp $ defflag opt_cpu_in_cksum.h NEON_IN_CKSUM @@ -17,7 +17,7 @@ file arch/arm/cortex/gic.c armgic # ARM PL310 L2 Cache Controller(initially on Cortex-A9) device arml2cc attach arml2cc at armperiph -file arch/arm/cortex/pl310.c arml2cc +file arch/arm/cortex/pl310.c arml2cc needs-flag # ARMv7 Generic Timer device armgtmr
