CVS commit: [netbsd-9] src/sys/arch/mips/mips
Module Name:src
Committed By: martin
Date: Thu Jul 16 12:34:49 UTC 2020
Modified Files:
src/sys/arch/mips/mips [netbsd-9]: mips_machdep.c
Log Message:
Pull up following revision(s) (requested by simonb in ticket #1016):
sys/arch/mips/mips/mips_machdep.c: revision 1.294
Fix mm_md_kernacc() for 64 bit kernels (including n32):
- FAULT for any physical address less than start of cached XKPHY address.
- Pass any remaining physical address less then end of RAM.
- Pass any remaining physical address within the KEGS0 kernel address range.
Ignore all remaining addresses and fall back to uvm_kernacc() for checking
virtual address ranges.
Fixes pmap(1) (and probably other kmem grovellers).
To generate a diff of this commit:
cvs rdiff -u -r1.279 -r1.279.4.1 src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.279 src/sys/arch/mips/mips/mips_machdep.c:1.279.4.1
--- src/sys/arch/mips/mips/mips_machdep.c:1.279 Fri Mar 29 05:23:12 2019
+++ src/sys/arch/mips/mips/mips_machdep.c Thu Jul 16 12:34:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.279 2019/03/29 05:23:12 simonb Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.279.4.1 2020/07/16 12:34:49 martin Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
*/
#include /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.279 2019/03/29 05:23:12 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.279.4.1 2020/07/16 12:34:49 martin Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -2421,21 +2421,28 @@ mm_md_kernacc(void *ptr, vm_prot_t prot,
const vaddr_t v = (vaddr_t)ptr;
#ifdef _LP64
- if (v < MIPS_XKPHYS_START) {
+ extern char end[];
+
+ /* For any address < XKPHYS cached address 0, fault */
+ if (v < MIPS_PHYS_TO_XKPHYS_CACHED(0)) {
return EFAULT;
}
- if (MIPS_XKPHYS_P(v) && v > MIPS_PHYS_TO_XKPHYS_CACHED(pmap_limits.avail_end +
+
+ /* If address < XKPHY(end of message buffer), good! */
+ if (v < MIPS_PHYS_TO_XKPHYS_CACHED(pmap_limits.avail_end +
mips_round_page(MSGBUFSIZE))) {
- return EFAULT;
- }
- if (MIPS_KSEG0_P(v) ||
- (MIPS_XKSEG_P(v) && v < MIPS_KSEG0_START)) {
+ /* XXX holes in RAM (eg, EdgeRouter 4) */
*handled = true;
return 0;
}
- if (MIPS_KSEG1_P(v) || MIPS_KSEG2_P(v)) {
- return EFAULT;
+
+ /* If address in KSEG0 and is before end of kernel, good! */
+ if (MIPS_KSEG0_P(v) && v < (vaddr_t)end) {
+ *handled = true;
+ return 0;
}
+
+ /* Otherwise, fall back to the uvm_kernacc() check. */
#else
if (v < MIPS_KSEG0_START) {
return EFAULT;
CVS commit: [netbsd-9] src/sys/arch/mips/mips
Module Name:src Committed By: martin Date: Sat Jun 20 16:35:02 UTC 2020 Modified Files: src/sys/arch/mips/mips [netbsd-9]: cache.c Log Message: Pull up following revision(s) (requested by tsutsui in ticket #964): sys/arch/mips/mips/cache.c: revision 1.67 Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache. PR/55138 Commented "I think this is bad copy" from skrll@. No visible regression on Cobalt Qube 2700 (Rm5230) through whole installation using netbsd-9 based Cobalt RestoreCD/USB. To generate a diff of this commit: cvs rdiff -u -r1.60 -r1.60.4.1 src/sys/arch/mips/mips/cache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/mips/cache.c diff -u src/sys/arch/mips/mips/cache.c:1.60 src/sys/arch/mips/mips/cache.c:1.60.4.1 --- src/sys/arch/mips/mips/cache.c:1.60 Mon Sep 3 16:29:26 2018 +++ src/sys/arch/mips/mips/cache.c Sat Jun 20 16:35:02 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $ */ +/* $NetBSD: cache.c,v 1.60.4.1 2020/06/20 16:35:02 martin Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -68,7 +68,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.60.4.1 2020/06/20 16:35:02 martin Exp $"); #include "opt_cputype.h" #include "opt_mips_cache.h" @@ -494,11 +494,11 @@ primary_cache_is_2way: case 32: /* used internally by mipsNN_picache_sync_range */ mco->mco_intern_icache_sync_range = - cache_r4k_icache_hit_inv_16; + cache_r4k_icache_hit_inv_32; /* used internally by mipsNN_picache_sync_range_index */ mco->mco_intern_icache_sync_range_index = - cache_r4k_icache_index_inv_16; + cache_r4k_icache_index_inv_32; break; default:
CVS commit: [netbsd-9] src/sys/arch/mips/mips
Module Name:src
Committed By: martin
Date: Sat Jun 20 16:22:57 UTC 2020
Modified Files:
src/sys/arch/mips/mips [netbsd-9]: bus_dma.c
Log Message:
Pull up following revision(s) (requested by tsutsui in ticket #963):
sys/arch/mips/mips/bus_dma.c: revision 1.41
Fix inconsistent mips_o32, _mips_o32, and __mips_o32 macro. PR/54216
Not sure what the original intention was, but no responce for a year,
and no visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
To generate a diff of this commit:
cvs rdiff -u -r1.38.20.1 -r1.38.20.2 src/sys/arch/mips/mips/bus_dma.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/bus_dma.c
diff -u src/sys/arch/mips/mips/bus_dma.c:1.38.20.1 src/sys/arch/mips/mips/bus_dma.c:1.38.20.2
--- src/sys/arch/mips/mips/bus_dma.c:1.38.20.1 Fri Mar 13 05:35:42 2020
+++ src/sys/arch/mips/mips/bus_dma.c Sat Jun 20 16:22:57 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.38.20.1 2020/03/13 05:35:42 martin Exp $ */
+/* $NetBSD: bus_dma.c,v 1.38.20.2 2020/06/20 16:22:57 martin Exp $ */
/*-
* Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.38.20.1 2020/03/13 05:35:42 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.38.20.2 2020/06/20 16:22:57 martin Exp $");
#define _MIPS_BUS_DMA_PRIVATE
@@ -829,7 +829,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
|| (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) == 0)
goto bounce_it;
-#ifdef _mips_o32
+#ifdef __mips_o32
/*
* If the mapping belongs to the kernel, or it belongs
* to the currently-running process (XXX actually, vmspace),
@@ -871,7 +871,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
* If we are forced to use Index ops, it's always a
* Write-back,Invalidate, so just do one test.
*/
-#ifdef mips_o32
+#ifdef __mips_o32
if (__predict_false(useindex || vaddr == 0)) {
mips_dcache_wbinv_range_index(vaddr, minlen);
#ifdef BUS_DMA_DEBUG
CVS commit: [netbsd-9] src/sys/arch/mips/mips
Module Name:src
Committed By: martin
Date: Fri Mar 13 05:35:43 UTC 2020
Modified Files:
src/sys/arch/mips/mips [netbsd-9]: bus_dma.c
Log Message:
Pull up following revision(s) (requested by thorpej in ticket #779):
sys/arch/mips/mips/bus_dma.c: revision 1.39
Allow len == 0 in bus_dmamap_sync().
XXX pullup-9
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.38.20.1 src/sys/arch/mips/mips/bus_dma.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/bus_dma.c
diff -u src/sys/arch/mips/mips/bus_dma.c:1.38 src/sys/arch/mips/mips/bus_dma.c:1.38.20.1
--- src/sys/arch/mips/mips/bus_dma.c:1.38 Wed Aug 17 22:02:19 2016
+++ src/sys/arch/mips/mips/bus_dma.c Fri Mar 13 05:35:42 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.38 2016/08/17 22:02:19 skrll Exp $ */
+/* $NetBSD: bus_dma.c,v 1.38.20.1 2020/03/13 05:35:42 martin Exp $ */
/*-
* Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.38 2016/08/17 22:02:19 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.38.20.1 2020/03/13 05:35:42 martin Exp $");
#define _MIPS_BUS_DMA_PRIVATE
@@ -750,11 +750,12 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
panic("_bus_dmamap_sync: mix PRE and POST");
if (offset >= map->dm_mapsize)
- panic("_bus_dmamap_sync: bad offset %"PRIxPADDR
- " (map size is %"PRIxPSIZE")",
-offset, map->dm_mapsize);
- if (len == 0 || (offset + len) > map->dm_mapsize)
- panic("_bus_dmamap_sync: bad length");
+ panic("%s: bad offset 0x%jx >= 0x%jx", __func__,
+ (intmax_t)offset, (intmax_t)map->dm_mapsize);
+ if ((offset + len) > map->dm_mapsize)
+ panic("%s: bad length 0x%jx + 0x%jx > 0x%jx", __func__,
+ (intmax_t)offset, (intmax_t)len,
+ (intmax_t)map->dm_mapsize);
#endif
/*
@@ -777,7 +778,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
#ifdef _MIPS_NEED_BUS_DMA_BOUNCE
struct mips_bus_dma_cookie * const cookie = map->_dm_cookie;
if (cookie != NULL && (cookie->id_flags & _BUS_DMA_IS_BOUNCING)
- && (ops & BUS_DMASYNC_PREWRITE)) {
+ && (ops & BUS_DMASYNC_PREWRITE) && len != 0) {
STAT_INCR(write_bounces);
/*
* Copy the caller's buffer to the bounce buffer.
@@ -920,7 +921,8 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
#ifdef _MIPS_NEED_BUS_DMA_BOUNCE
if ((ops & BUS_DMASYNC_POSTREAD) == 0
|| cookie == NULL
- || (cookie->id_flags & _BUS_DMA_IS_BOUNCING) == 0)
+ || (cookie->id_flags & _BUS_DMA_IS_BOUNCING) == 0
+ || len == 0)
return;
STAT_INCR(read_bounces);
