CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: skrll
Date: Sun Aug 9 07:08:29 UTC 2020
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
Type consistency
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.25 src/sys/arch/mips/ingenic/ingenic_regs.h:1.26
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.25 Sun May 21 06:49:13 2017
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sun Aug 9 07:08:29 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.25 2017/05/21 06:49:13 skrll Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.26 2020/08/09 07:08:29 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -118,7 +118,7 @@
static inline void
writereg(uint32_t reg, uint32_t val)
{
- *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
+ *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
wbflush();
}
@@ -126,7 +126,7 @@ static inline uint32_t
readreg(uint32_t reg)
{
wbflush();
- return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
+ return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg);
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: nisimura
Date: Thu Apr 2 13:03:03 UTC 2020
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dme.c
Log Message:
add miivar.h and put a stop gap to compile.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_dme.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dme.c
diff -u src/sys/arch/mips/ingenic/ingenic_dme.c:1.3 src/sys/arch/mips/ingenic/ingenic_dme.c:1.4
--- src/sys/arch/mips/ingenic/ingenic_dme.c:1.3 Fri May 19 07:43:31 2017
+++ src/sys/arch/mips/ingenic/ingenic_dme.c Thu Apr 2 13:03:03 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dme.c,v 1.3 2017/05/19 07:43:31 skrll Exp $ */
+/* $NetBSD: ingenic_dme.c,v 1.4 2020/04/02 13:03:03 nisimura Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,14 +27,13 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.3 2017/05/19 07:43:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.4 2020/04/02 13:03:03 nisimura Exp $");
#include
-#include
-#include
-#include
+#include
#include
-#include
+#include
+#include
#include
#include
@@ -42,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: ingenic_dme.
#include
#include
#include
+#include
#include
#include
@@ -132,7 +132,7 @@ ingenic_dme_attach(device_t parent, devi
13);
goto fail;
}
-
+#if 0
eaddrprop = prop_dictionary_get(device_properties(self), "mac-address");
if (eaddrprop != NULL && prop_data_size(eaddrprop) == ETHER_ADDR_LEN) {
@@ -148,6 +148,13 @@ ingenic_dme_attach(device_t parent, devi
aprint_error_dev(self, "reading MAC address from chip\n");
dme_read_c(sc, DM9000_PAB0, enaddr, 6);
}
+#else
+ (void)eaddrprop;
+ /*
+ * dme_attach checks dictionary, then previous setting, then roll
+ * a dice to make random MAC address
+ */
+#endif
dme_attach(sc, enaddr);
return;
fail:
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: thorpej
Date: Mon Dec 23 02:16:43 UTC 2019
Modified Files:
src/sys/arch/mips/ingenic: jziic.c
Log Message:
No need to check cold ourselves; iic_exec() does it for us.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/ingenic/jziic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/jziic.c
diff -u src/sys/arch/mips/ingenic/jziic.c:1.6 src/sys/arch/mips/ingenic/jziic.c:1.7
--- src/sys/arch/mips/ingenic/jziic.c:1.6 Sun Dec 22 23:23:31 2019
+++ src/sys/arch/mips/ingenic/jziic.c Mon Dec 23 02:16:43 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: jziic.c,v 1.6 2019/12/22 23:23:31 thorpej Exp $ */
+/* $NetBSD: jziic.c,v 1.7 2019/12/23 02:16:43 thorpej Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: jziic.c,v 1.6 2019/12/22 23:23:31 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jziic.c,v 1.7 2019/12/23 02:16:43 thorpej Exp $");
/*
* a preliminary driver for JZ4780's on-chip SMBus controllers
@@ -266,7 +266,7 @@ jziic_i2c_exec(void *cookie, i2c_op_t op
{
struct jziic_softc *sc = cookie;
- if (cold || (flags & I2C_F_POLL)) {
+ if (flags & I2C_F_POLL) {
return jziic_i2c_exec_poll(sc, op, addr, vcmd, cmdlen, vbuf,
buflen, flags);
} else {
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: skrll
Date: Fri May 19 07:43:31 UTC 2017
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_com.c ingenic_dme.c
jzfb_regs.h jziic.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/ingenic_com.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_dme.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/jzfb_regs.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/jziic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.18 src/sys/arch/mips/ingenic/apbus.c:1.19
--- src/sys/arch/mips/ingenic/apbus.c:1.18 Thu Oct 8 17:54:30 2015
+++ src/sys/arch/mips/ingenic/apbus.c Fri May 19 07:43:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.18 2015/10/08 17:54:30 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.19 2017/05/19 07:43:31 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -25,11 +25,11 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
+
/* catch-all for on-chip peripherals */
#include
-__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.18 2015/10/08 17:54:30 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.19 2017/05/19 07:43:31 skrll Exp $");
#include "locators.h"
#define _MIPS_BUS_DMA_PRIVATE
@@ -264,7 +264,7 @@ apbus_attach(device_t parent, device_t s
reg &= ~adv->clk1;
writereg(JZ_CLKGR1, reg);
}
-
+
(void) config_found_ia(self, "apbus", , apbus_print);
}
}
Index: src/sys/arch/mips/ingenic/ingenic_com.c
diff -u src/sys/arch/mips/ingenic/ingenic_com.c:1.5 src/sys/arch/mips/ingenic/ingenic_com.c:1.6
--- src/sys/arch/mips/ingenic/ingenic_com.c:1.5 Sat Jul 11 19:00:04 2015
+++ src/sys/arch/mips/ingenic/ingenic_com.c Fri May 19 07:43:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_com.c,v 1.5 2015/07/11 19:00:04 macallan Exp $ */
+/* $NetBSD: ingenic_com.c,v 1.6 2017/05/19 07:43:31 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_com.c,v 1.5 2015/07/11 19:00:04 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_com.c,v 1.6 2017/05/19 07:43:31 skrll Exp $");
#include
#include
@@ -112,7 +112,7 @@ ingenic_putchar_init(void)
com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
com0addr[com_fifo] = htole32(
- FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
+ FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
FIFO_TRIGGER_1 | FIFO_UART_ON);
#if 0
}
@@ -149,7 +149,7 @@ void
ingenic_com_cnattach(void)
{
int i;
-
+
bus_space_map(apbus_memt, JZ_UART0, 0x100, 0, );
cons_com = JZ_UART0;
memset(, 0, sizeof(regs));
Index: src/sys/arch/mips/ingenic/ingenic_dme.c
diff -u src/sys/arch/mips/ingenic/ingenic_dme.c:1.2 src/sys/arch/mips/ingenic/ingenic_dme.c:1.3
--- src/sys/arch/mips/ingenic/ingenic_dme.c:1.2 Thu Oct 8 17:55:58 2015
+++ src/sys/arch/mips/ingenic/ingenic_dme.c Fri May 19 07:43:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dme.c,v 1.2 2015/10/08 17:55:58 macallan Exp $ */
+/* $NetBSD: ingenic_dme.c,v 1.3 2017/05/19 07:43:31 skrll Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.2 2015/10/08 17:55:58 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.3 2017/05/19 07:43:31 skrll Exp $");
#include
#include
@@ -160,7 +160,7 @@ fail:
static int
ingenic_dme_intr(void *arg)
{
- uint32_t reg;
+ uint32_t reg;
int ret = 0;
/* see if it's us */
Index: src/sys/arch/mips/ingenic/jzfb_regs.h
diff -u src/sys/arch/mips/ingenic/jzfb_regs.h:1.1 src/sys/arch/mips/ingenic/jzfb_regs.h:1.2
--- src/sys/arch/mips/ingenic/jzfb_regs.h:1.1 Thu Apr 7 01:00:05 2016
+++ src/sys/arch/mips/ingenic/jzfb_regs.h Fri May 19 07:43:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: jzfb_regs.h,v 1.1 2016/04/07 01:00:05 macallan Exp $ */
+/* $NetBSD: jzfb_regs.h,v 1.2 2017/05/19 07:43:31 skrll Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -86,4 +86,4 @@
#define JZ_LCDENH_GAMMA 0x0800
#define JZ_LCDENH_VEE 0x1000
-#endif /* JZFB_REGS_H */
\ No newline at end of file
+#endif /* JZFB_REGS_H */
Index: src/sys/arch/mips/ingenic/jziic.c
diff -u src/sys/arch/mips/ingenic/jziic.c:1.3 src/sys/arch/mips/ingenic/jziic.c:1.4
--- src/sys/arch/mips/ingenic/jziic.c:1.3 Mon Dec 14 23:21:23 2015
+++ src/sys/arch/mips/ingenic/jziic.c Fri May 19 07:43:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: jziic.c,v 1.3 2015/12/14 23:21:23 macallan Exp $ */
+/* $NetBSD: jziic.c,v 1.4 2017/05/19 07:43:31 skrll Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,12 +27,12 @@
*/
#include
-__KERNEL_RCSID(0,
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: skrll
Date: Sat Aug 27 05:56:33 UTC 2016
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.23 src/sys/arch/mips/ingenic/ingenic_regs.h:1.24
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.23 Thu Apr 7 01:00:05 2016
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Aug 27 05:56:33 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.23 2016/04/07 01:00:05 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.24 2016/08/27 05:56:33 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -63,15 +63,15 @@
/* timers and PWMs */
#define JZ_TC_TER 0x10002010 /* TC enable reg, ro */
#define JZ_TC_TESR 0x10002014 /* TC enable set reg. */
- #define TESR_TCST0 0x0001 /* enable counter 0 */
- #define TESR_TCST1 0x0002 /* enable counter 1 */
- #define TESR_TCST2 0x0004 /* enable counter 2 */
- #define TESR_TCST3 0x0008 /* enable counter 3 */
- #define TESR_TCST4 0x0010 /* enable counter 4 */
- #define TESR_TCST5 0x0020 /* enable counter 5 */
- #define TESR_TCST6 0x0040 /* enable counter 6 */
- #define TESR_TCST7 0x0080 /* enable counter 7 */
- #define TESR_OST 0x8000 /* enable OST */
+ #define TESR_TCST0 0x0001 /* enable counter 0 */
+ #define TESR_TCST1 0x0002 /* enable counter 1 */
+ #define TESR_TCST2 0x0004 /* enable counter 2 */
+ #define TESR_TCST3 0x0008 /* enable counter 3 */
+ #define TESR_TCST4 0x0010 /* enable counter 4 */
+ #define TESR_TCST5 0x0020 /* enable counter 5 */
+ #define TESR_TCST6 0x0040 /* enable counter 6 */
+ #define TESR_TCST7 0x0080 /* enable counter 7 */
+ #define TESR_OST 0x8000 /* enable OST */
#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */
#define JZ_TC_TFR 0x10002020
#define TFR_FFLAG0 0x0001 /* channel 0 */
@@ -167,7 +167,7 @@ MFC0(uint32_t r, uint32_t s)
#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
#define CP0_CORE0_MBOX _(20), 0
-#define CP0_CORE1_MBOX _(20), 1
+#define CP0_CORE1_MBOX _(20), 1
@@ -289,7 +289,7 @@ MFC0(uint32_t r, uint32_t s)
#define PCR_CLK_48 0x0200 /* 48MHz */
#define PCR_CLK_24 0x0100 /* 24MHz */
#define PCR_CLK_12 0x /* 12MHz */
- #define PCR_DMPD1 0x0080 /* pull down D- on port 1 */
+ #define PCR_DMPD1 0x0080 /* pull down D- on port 1 */
#define PCR_DPPD1 0x0040 /* pull down D+ on port 1 */
#define PCR_PORT0_RST 0x0020 /* port 0 reset */
#define PCR_PORT1_RST 0x0010 /* port 1 reset */
@@ -399,7 +399,7 @@ MFC0(uint32_t r, uint32_t s)
/*
* INT == 1: 0 - level triggered, 1 - edge triggered
* INT == 0: 0 - device select, see below
- */
+ */
#define JZ_GPIO_PAT1 0x0030 /* pattern 1 register */
#define JZ_GPIO_PAT1S 0x0034 /* pattern 1 set register */
#define JZ_GPIO_PAT1C 0x0038 /* pattern 1 clear register */
@@ -468,7 +468,7 @@ gpio_as_dev0(uint32_t g, int pin)
writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
writereg(reg + JZ_GPIO_PAT0C, mask);
}
-
+
static inline void
gpio_as_dev1(uint32_t g, int pin)
{
@@ -480,7 +480,7 @@ gpio_as_dev1(uint32_t g, int pin)
writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */
writereg(reg + JZ_GPIO_PAT0S, mask);
}
-
+
static inline void
gpio_as_dev2(uint32_t g, int pin)
{
@@ -492,7 +492,7 @@ gpio_as_dev2(uint32_t g, int pin)
writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */
writereg(reg + JZ_GPIO_PAT0C, mask);
}
-
+
static inline void
gpio_as_dev3(uint32_t g, int pin)
{
@@ -504,7 +504,7 @@ gpio_as_dev3(uint32_t g, int pin)
writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */
writereg(reg + JZ_GPIO_PAT0S, mask);
}
-
+
static inline void
gpio_as_intr_level(uint32_t g, int pin)
{
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Thu Apr 7 01:00:05 UTC 2016 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Added Files: src/sys/arch/mips/ingenic: jzfb_regs.h Log Message: moar registers, less tpyos To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/ingenic/ingenic_regs.h cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/jzfb_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.22 src/sys/arch/mips/ingenic/ingenic_regs.h:1.23 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.22 Thu Oct 8 17:54:30 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Thu Apr 7 01:00:05 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.22 2015/10/08 17:54:30 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.23 2016/04/07 01:00:05 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -162,17 +162,25 @@ MFC0(uint32_t r, uint32_t s) #define REIM_MIRQ1_M 0x2 /* allow mailbox IRQ for core 1 */ #define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */ #define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */ -#define REIM_ENTRY_M 0x /* reset exception entry if RPCn=1 */ +#define REIM_ENTRY_M 0xf000 /* reset exception entry if RPCn=1 */ #define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ +#define CP0_CORE0_MBOX _(20), 0 +#define CP0_CORE1_MBOX _(20), 1 + + + /* power management */ #define JZ_CPCCR 0x1000 /* Clock Control Register */ #define JZ_PDIV_M 0x000f /* PCLK divider mask */ #define JZ_PDIV_S 16 /* PCLK divider shift */ #define JZ_CDIV_M 0x000f /* CPU clock divider mask */ #define JZ_CDIV_S 0 /* CPU clock divider shift */ -#define JZ_CPMPCR 0x0014 /* MPLL */ +#define JZ_LPCR 0x1004 /* Low Power Control Register */ + #define JZ_PD_SCPU 0x8000 /* power down 2nd CPU */ + #define JZ_SCPUS 0x0800 /* CPU is powered down */ +#define JZ_CPMPCR 0x1014 /* MPLL */ #define JZ_PLLM_S 19 /* PLL multiplier shift */ #define JZ_PLLM_M 0xfff8 /* PLL multiplier mask */ #define JZ_PLLN_S 13 /* PLL divider shift */ @@ -182,6 +190,7 @@ MFC0(uint32_t r, uint32_t s) #define JZ_PLLON 0x0010 /* PLL is on and stable */ #define JZ_PLLBP 0x0002 /* PLL bypass */ #define JZ_PLLEN 0x0001 /* PLL enable */ +#define JZ_CPVPCR 0x101c /* VPLL */ #define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */ #define CLK_NEMC (1 << 0) #define CLK_BCH (1 << 1) Added files: Index: src/sys/arch/mips/ingenic/jzfb_regs.h diff -u /dev/null src/sys/arch/mips/ingenic/jzfb_regs.h:1.1 --- /dev/null Thu Apr 7 01:00:05 2016 +++ src/sys/arch/mips/ingenic/jzfb_regs.h Thu Apr 7 01:00:05 2016 @@ -0,0 +1,89 @@ +/* $NetBSD: jzfb_regs.h,v 1.1 2016/04/07 01:00:05 macallan Exp $ */ + +/*- + * Copyright (c) 2015 Michael Lorenz + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef JZFB_REGS_H +#define JZFB_REGS_H + +#define JZ_LCDCFG 0x +#define JZ_LCDCTRL 0x0030 +#define JZ_LCDSTATE 0x0034 +#define JZ_LCDOSDC 0x0100 +#define JZ_LCDOSDCTRL 0x0104 +#define JZ_LCDOSDS 0x0108 +#define JZ_LCDBGC0 0x010C +#define JZ_LCDBGC1 0x02C4 +#define JZ_LCDKEY0 0x0110 +#define JZ_LCDKEY1 0x0114 +#define JZ_LCDALPHA 0x0118 +#define JZ_LCDIPUR 0x011C +#define JZ_LCDRGBC 0x0090 +#define JZ_LCDVAT 0x000C +#define JZ_LCDDAH 0x0010 +#define JZ_LCDDAV 0x0014 +#define JZ_LCDXYP0 0x0120 +#define JZ_LCDXYP1 0x0124 +#define JZ_LCDSIZE0 0x0128 +#define JZ_LCDSIZE1 0x012C +#define JZ_LCDVSYNC
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Wed Feb 17 20:12:42 UTC 2016
Modified Files:
src/sys/arch/mips/ingenic: ingenic_rng.c
Log Message:
Adapt CI20 HWRNG to synchronous on-demand callback.
Omit needless softint/locking dance.
from riastradh@
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_rng.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_rng.c
diff -u src/sys/arch/mips/ingenic/ingenic_rng.c:1.3 src/sys/arch/mips/ingenic/ingenic_rng.c:1.4
--- src/sys/arch/mips/ingenic/ingenic_rng.c:1.3 Tue Nov 17 16:53:21 2015
+++ src/sys/arch/mips/ingenic/ingenic_rng.c Wed Feb 17 20:12:42 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_rng.c,v 1.3 2015/11/17 16:53:21 macallan Exp $ */
+/* $NetBSD: ingenic_rng.c,v 1.4 2016/02/17 20:12:42 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael McConville
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_rng.c,v 1.3 2015/11/17 16:53:21 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_rng.c,v 1.4 2016/02/17 20:12:42 macallan Exp $");
/*
* adapted from Jared McNeill's amlogic_rng.c
@@ -39,9 +39,7 @@ __KERNEL_RCSID(0, "$NetBSD: ingenic_rng.
#include
#include
#include
-#include
#include
-#include
#include
#include
@@ -55,22 +53,15 @@ struct ingenic_rng_softc;
static int ingenic_rng_match(device_t, cfdata_t, void *);
static void ingenic_rng_attach(device_t, device_t, void *);
-static void ingenic_rng_get(struct ingenic_rng_softc *);
-static void ingenic_rng_get_intr(void *);
-static void ingenic_rng_get_cb(size_t, void *);
+static void ingenic_rng_get(size_t, void *);
struct ingenic_rng_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
- void * sc_sih;
-
+ kmutex_t sc_lock;
krndsource_t sc_rndsource;
- size_t sc_bytes_wanted;
-
- kmutex_t sc_intr_lock;
- kmutex_t sc_rnd_lock;
};
CFATTACH_DECL_NEW(ingenic_rng, sizeof(struct ingenic_rng_softc),
@@ -104,67 +95,32 @@ ingenic_rng_attach(device_t parent, devi
return;
}
- mutex_init(>sc_intr_lock, MUTEX_DEFAULT, IPL_SERIAL);
- mutex_init(>sc_rnd_lock, MUTEX_DEFAULT, IPL_SERIAL);
-
+ mutex_init(>sc_lock, MUTEX_DEFAULT, IPL_VM);
+
aprint_naive(": Ingenic random number generator\n");
aprint_normal(": Ingenic random number generator\n");
- sc->sc_sih = softint_establish(SOFTINT_SERIAL|SOFTINT_MPSAFE,
- ingenic_rng_get_intr, sc);
- if (sc->sc_sih == NULL) {
- aprint_error_dev(self, "couldn't establish softint\n");
- return;
- }
-
- rndsource_setcb(>sc_rndsource, ingenic_rng_get_cb, sc);
+ rndsource_setcb(>sc_rndsource, ingenic_rng_get, sc);
rnd_attach_source(>sc_rndsource, device_xname(self), RND_TYPE_RNG,
RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
- ingenic_rng_get_cb(RND_POOLBITS / NBBY, sc);
+ ingenic_rng_get(RND_POOLBITS / NBBY, sc);
}
static void
-ingenic_rng_get(struct ingenic_rng_softc *sc)
+ingenic_rng_get(size_t bytes_wanted, void *priv)
{
+ struct ingenic_rng_softc * const sc = priv;
uint32_t data;
- mutex_spin_enter(>sc_intr_lock);
- while (sc->sc_bytes_wanted) {
+ mutex_spin_enter(>sc_lock);
+ while (bytes_wanted) {
data = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 0);
- mutex_spin_exit(>sc_intr_lock);
- mutex_spin_enter(>sc_rnd_lock);
- rnd_add_data(>sc_rndsource, , sizeof(data),
+ delay(1);
+ rnd_add_data_sync(>sc_rndsource, , sizeof(data),
sizeof(data) * NBBY);
- mutex_spin_exit(>sc_rnd_lock);
- mutex_spin_enter(>sc_intr_lock);
- sc->sc_bytes_wanted -= MIN(sc->sc_bytes_wanted, sizeof(data));
+ bytes_wanted -= MIN(bytes_wanted, sizeof(data));
}
explicit_memset(, 0, sizeof(data));
- mutex_spin_exit(>sc_intr_lock);
-}
-
-static void
-ingenic_rng_get_cb(size_t bytes_wanted, void *priv)
-{
- struct ingenic_rng_softc * const sc = priv;
-
- mutex_spin_enter(>sc_intr_lock);
- if (sc->sc_bytes_wanted == 0)
- softint_schedule(sc->sc_sih);
-
- if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted))
- sc->sc_bytes_wanted = UINT_MAX;
- else
- sc->sc_bytes_wanted += bytes_wanted;
-
- mutex_spin_exit(>sc_intr_lock);
-}
-
-static void
-ingenic_rng_get_intr(void *priv)
-{
- struct ingenic_rng_softc * const sc = priv;
-
- ingenic_rng_get(sc);
+ mutex_spin_exit(>sc_lock);
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Sat Jan 2 16:50:52 UTC 2016
Modified Files:
src/sys/arch/mips/ingenic: ingenic_ehci.c
Log Message:
properly initialize the EHCI
from Alexander Kabaev ( kan at freebsd.org )
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_ehci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_ehci.c
diff -u src/sys/arch/mips/ingenic/ingenic_ehci.c:1.3 src/sys/arch/mips/ingenic/ingenic_ehci.c:1.4
--- src/sys/arch/mips/ingenic/ingenic_ehci.c:1.3 Tue Mar 17 09:27:09 2015
+++ src/sys/arch/mips/ingenic/ingenic_ehci.c Sat Jan 2 16:50:52 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $ */
+/* $NetBSD: ingenic_ehci.c,v 1.4 2016/01/02 16:50:52 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_ehci.c,v 1.4 2016/01/02 16:50:52 macallan Exp $");
#include
#include
@@ -74,6 +74,79 @@ ingenic_ehci_match(device_t parent, stru
return 1;
}
+static int
+ingenic_ehci_enable(struct ehci_softc *sc)
+{
+ uint32_t reg;
+
+ /* Togle VBUS pin */
+ gpio_set(5, 15, 0);
+ delay(25);
+ gpio_set(5, 15, 1);
+ delay(25);
+
+ /* Enable OTG, should not be necessary since we use PLL clock */
+ reg = readreg(JZ_USBPCR);
+ reg &= ~(PCR_OTG_DISABLE);
+ writereg(JZ_USBPCR, reg);
+
+ /* Select CORE as PLL reference */
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_REFCLK_CORE;
+ writereg(JZ_USBPCR1, reg);
+
+ /* Configure OTG PHY clock frequency */
+ reg = readreg(JZ_USBPCR1);
+ reg &= ~PCR_CLK_M;
+ reg |= PCR_CLK_48;
+ writereg(JZ_USBPCR1, reg);
+
+ /* Do not force port1 to suspend mode */
+ reg = readreg(JZ_OPCR);
+ reg |= OPCR_SPENDN1;
+ writereg(JZ_OPCR, reg);
+
+ /* D- pulldown */
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_DMPD1;
+ writereg(JZ_USBPCR1, reg);
+
+ /* D+ pulldown */
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_DPPD1;
+ writereg(JZ_USBPCR1, reg);
+
+ /* 16 bit bus witdth for port 1 (and 0) */
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_WORD_I_F1 | PCR_WORD_I_F0;
+ writereg(JZ_USBPCR1, reg);
+
+ /* Reset USB */
+ reg = readreg(JZ_USBPCR);
+ reg |= PCR_POR;
+ writereg(JZ_USBPCR, reg);
+ delay(1);
+ reg = readreg(JZ_USBPCR);
+ reg &= ~(PCR_POR);
+ writereg(JZ_USBPCR, reg);
+
+ /* Soft-reset USB */
+ reg = readreg(JZ_SRBC);
+ reg |= (1 << 14);
+ writereg(JZ_SRBC, reg);
+ /* 300ms */
+ delay(30);
+
+ reg = readreg(JZ_SRBC);
+ reg &= ~(1 << 14);
+ writereg(JZ_SRBC, reg);
+
+ /* 300ms */
+ delay(30);
+
+ return (0);
+}
+
/* ARGSUSED */
static void
ingenic_ehci_attach(device_t parent, device_t self, void *aux)
@@ -105,19 +178,13 @@ ingenic_ehci_attach(device_t parent, dev
aprint_naive(": EHCI USB controller\n");
aprint_normal(": EHCI USB controller\n");
- /*
- * voodoo from the linux driver:
- * select utmi data bus width of controller to 16bit
- */
- reg = bus_space_read_4(sc->iot, sc->ioh, 0xb0);
- reg |= 1 << 6;
- bus_space_write_4(sc->iot, sc->ioh, 0xb0, reg);
+ ingenic_ehci_enable(sc);
/* Disable EHCI interrupts */
bus_space_write_4(sc->iot, sc->ioh, EHCI_USBINTR, 0);
ih = evbmips_intr_establish(aa->aa_irq, ehci_intr, sc);
-
+
if (ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
aa->aa_irq);
@@ -132,6 +199,7 @@ ingenic_ehci_attach(device_t parent, dev
sc->sc_ncomp = 0;
#else
sc->sc_ncomp = 0;
+ sc->sc_npcomp = 0;
#endif
sc->sc_id_vendor = USB_VENDOR_INGENIC;
strlcpy(sc->sc_vendor, "Ingenic", sizeof(sc->sc_vendor));
@@ -142,6 +210,14 @@ ingenic_ehci_attach(device_t parent, dev
goto fail;
}
+ /*
+ * voodoo from the linux driver:
+ * select utmi data bus width of controller to 16bit
+ */
+ reg = bus_space_read_4(sc->iot, sc->ioh, 0xb0);
+ reg |= 1 << 6;
+ bus_space_write_4(sc->iot, sc->ioh, 0xb0, reg);
+
/* Attach USB device */
sc->sc_child = config_found(self, >sc_bus, usbctlprint);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Mon Dec 14 23:21:23 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: jziic.c Log Message: zero out struct i2cbus_attach_args before messing with it To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/jziic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/jziic.c diff -u src/sys/arch/mips/ingenic/jziic.c:1.2 src/sys/arch/mips/ingenic/jziic.c:1.3 --- src/sys/arch/mips/ingenic/jziic.c:1.2 Tue Apr 21 06:12:41 2015 +++ src/sys/arch/mips/ingenic/jziic.c Mon Dec 14 23:21:23 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: jziic.c,v 1.2 2015/04/21 06:12:41 macallan Exp $ */ +/* $NetBSD: jziic.c,v 1.3 2015/12/14 23:21:23 macallan Exp $ */ /*- * Copyright (c) 2015 Michael Lorenz @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: jziic.c,v 1.2 2015/04/21 06:12:41 macallan Exp $"); +__KERNEL_RCSID(0, "$NetBSD: jziic.c,v 1.3 2015/12/14 23:21:23 macallan Exp $"); /* * a preliminary driver for JZ4780's on-chip SMBus controllers @@ -185,6 +185,7 @@ jziic_attach(device_t parent, device_t s sc->sc_i2c.ic_write_byte = NULL; sc->sc_i2c.ic_exec = jziic_i2c_exec; + memset(, 0, sizeof(iba)); iba.iba_tag = >sc_i2c; (void) config_found_ia(sc->sc_dev, "i2cbus", , iicbus_print);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Nov 17 16:53:21 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_rng.c
Log Message:
Long overdue suggestions from Taylor Campbell and a few syntax/style
tweaks from myself.
>From Michael McConville
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_rng.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_rng.c
diff -u src/sys/arch/mips/ingenic/ingenic_rng.c:1.2 src/sys/arch/mips/ingenic/ingenic_rng.c:1.3
--- src/sys/arch/mips/ingenic/ingenic_rng.c:1.2 Sun Aug 30 05:09:16 2015
+++ src/sys/arch/mips/ingenic/ingenic_rng.c Tue Nov 17 16:53:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_rng.c,v 1.2 2015/08/30 05:09:16 macallan Exp $ */
+/* $NetBSD: ingenic_rng.c,v 1.3 2015/11/17 16:53:21 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael McConville
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_rng.c,v 1.2 2015/08/30 05:09:16 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_rng.c,v 1.3 2015/11/17 16:53:21 macallan Exp $");
/*
* adapted from Jared McNeill's amlogic_rng.c
@@ -79,32 +79,28 @@ CFATTACH_DECL_NEW(ingenic_rng, sizeof(st
static int
ingenic_rng_match(device_t parent, cfdata_t cf, void *aux)
{
- struct apbus_attach_args *aa = aux;
+ const struct apbus_attach_args *aa = aux;
- if (strcmp(aa->aa_name, "jzrng") == 0) {
- return 1;
- } else {
- return 0;
- }
+ return !(strcmp(aa->aa_name, "jzrng"));
}
static void
ingenic_rng_attach(device_t parent, device_t self, void *aux)
{
struct ingenic_rng_softc * const sc = device_private(self);
- struct apbus_attach_args * const aa = aux;
+ const struct apbus_attach_args * const aa = aux;
+ bus_addr_t addr = aa->aa_addr;
int error;
sc->sc_dev = self;
sc->sc_bst = aa->aa_bst;
- if (aa->aa_addr == 0) {
- aa->aa_addr = JZ_RNG;
- }
+ if (addr == 0)
+ addr = JZ_RNG;
- error = bus_space_map(aa->aa_bst, aa->aa_addr, 4, 0, >sc_bsh);
+ error = bus_space_map(aa->aa_bst, addr, 4, 0, >sc_bsh);
if (error) {
aprint_error_dev(self,
- "can't map registers for %s: %d\n", aa->aa_name, error);
+ "can't map registers for %s: %d\n", aa->aa_name, error);
return;
}
@@ -135,10 +131,7 @@ ingenic_rng_get(struct ingenic_rng_softc
mutex_spin_enter(>sc_intr_lock);
while (sc->sc_bytes_wanted) {
- bus_space_read_region_4(sc->sc_bst, sc->sc_bsh, 0, , 1);
-#if 0
- device_printf(sc->sc_dev, "random output: %x\n", data);
-#endif
+ data = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 0);
mutex_spin_exit(>sc_intr_lock);
mutex_spin_enter(>sc_rnd_lock);
rnd_add_data(>sc_rndsource, , sizeof(data),
@@ -157,14 +150,14 @@ ingenic_rng_get_cb(size_t bytes_wanted,
struct ingenic_rng_softc * const sc = priv;
mutex_spin_enter(>sc_intr_lock);
- if (sc->sc_bytes_wanted == 0) {
+ if (sc->sc_bytes_wanted == 0)
softint_schedule(sc->sc_sih);
- }
- if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted)) {
+
+ if (bytes_wanted > (UINT_MAX - sc->sc_bytes_wanted))
sc->sc_bytes_wanted = UINT_MAX;
- } else {
+ else
sc->sc_bytes_wanted += bytes_wanted;
- }
+
mutex_spin_exit(>sc_intr_lock);
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Wed Oct 14 15:44:57 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_efuse.c Log Message: add some comments To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_efuse.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_efuse.c diff -u src/sys/arch/mips/ingenic/ingenic_efuse.c:1.2 src/sys/arch/mips/ingenic/ingenic_efuse.c:1.3 --- src/sys/arch/mips/ingenic/ingenic_efuse.c:1.2 Thu Oct 8 18:20:31 2015 +++ src/sys/arch/mips/ingenic/ingenic_efuse.c Wed Oct 14 15:44:57 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_efuse.c,v 1.2 2015/10/08 18:20:31 macallan Exp $ */ +/* $NetBSD: ingenic_efuse.c,v 1.3 2015/10/14 15:44:57 macallan Exp $ */ /*- * Copyright (c) 2015 Michael Lorenz @@ -26,8 +26,15 @@ * POSSIBILITY OF SUCH DAMAGE. */ +/* + * a driver for the 'EFUSE Slave Interface' found on JZ4780 + * more or less 8kBit of non-volatile storage containing things like MAC + * address, various encryption keys, boot code, serial numbers and parameters. + * Using it only to get the MAC address for now. + */ + #include -__KERNEL_RCSID(0, "$NetBSD: ingenic_efuse.c,v 1.2 2015/10/08 18:20:31 macallan Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ingenic_efuse.c,v 1.3 2015/10/14 15:44:57 macallan Exp $"); #include #include @@ -114,6 +121,7 @@ ingenic_efuse_read(struct efuse_softc *s uint32_t abuf; int i; + /* default, just in case */ bus_space_write_4(sc->sc_iot, sc->sc_ioh, JZ_EFUCFG, 0x0004); bus_space_write_4(sc->sc_iot, sc->sc_ioh, JZ_EFUCTRL, JZ_EFUSE_READ | @@ -127,4 +135,4 @@ ingenic_efuse_read(struct efuse_softc *s memcpy(buf, , 4); buf += 4; } -} \ No newline at end of file +}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Thu Oct 8 17:55:58 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dme.c
Log Message:
use the MAC address passed as a property if available instead of relying on
u-boot to program it into the chip for us ( which it may not do if we're not
netbooting )
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_dme.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dme.c
diff -u src/sys/arch/mips/ingenic/ingenic_dme.c:1.1 src/sys/arch/mips/ingenic/ingenic_dme.c:1.2
--- src/sys/arch/mips/ingenic/ingenic_dme.c:1.1 Tue Mar 10 18:15:47 2015
+++ src/sys/arch/mips/ingenic/ingenic_dme.c Thu Oct 8 17:55:58 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $ */
+/* $NetBSD: ingenic_dme.c,v 1.2 2015/10/08 17:55:58 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dme.c,v 1.2 2015/10/08 17:55:58 macallan Exp $");
#include
#include
@@ -76,6 +76,7 @@ ingenic_dme_attach(device_t parent, devi
{
struct dme_softc *sc = device_private(self);
struct apbus_attach_args *aa = aux;
+ prop_data_t eaddrprop;
void *ih;
static uint8_t enaddr[ETHER_ADDR_LEN];
int error;
@@ -132,12 +133,21 @@ ingenic_dme_attach(device_t parent, devi
goto fail;
}
- /*
- * XXX grab MAC address set by uboot
- * I'm not sure uboot will program the MAC address into the chip when
- * not netbooting, so this needs to go away
- */
- dme_read_c(sc, DM9000_PAB0, enaddr, 6);
+ eaddrprop = prop_dictionary_get(device_properties(self), "mac-address");
+
+ if (eaddrprop != NULL && prop_data_size(eaddrprop) == ETHER_ADDR_LEN) {
+ memcpy(enaddr, prop_data_data_nocopy(eaddrprop),
+ ETHER_ADDR_LEN);
+ aprint_debug_dev(self, "got MAC address!\n");
+ } else {
+ /*
+ * XXX
+ * if we don't get the MAC address as a property we hope like
+ * hell that uboot programmed it into the network chip
+ */
+ aprint_error_dev(self, "reading MAC address from chip\n");
+ dme_read_c(sc, DM9000_PAB0, enaddr, 6);
+ }
dme_attach(sc, enaddr);
return;
fail:
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Thu Oct 8 18:20:31 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_efuse.c
Log Message:
fix build with INGENIC_DEBUG
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_efuse.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_efuse.c
diff -u src/sys/arch/mips/ingenic/ingenic_efuse.c:1.1 src/sys/arch/mips/ingenic/ingenic_efuse.c:1.2
--- src/sys/arch/mips/ingenic/ingenic_efuse.c:1.1 Thu Oct 8 17:54:30 2015
+++ src/sys/arch/mips/ingenic/ingenic_efuse.c Thu Oct 8 18:20:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_efuse.c,v 1.1 2015/10/08 17:54:30 macallan Exp $ */
+/* $NetBSD: ingenic_efuse.c,v 1.2 2015/10/08 18:20:31 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: ingenic_efuse.c,v 1.1 2015/10/08 17:54:30 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_efuse.c,v 1.2 2015/10/08 18:20:31 macallan Exp $");
#include
#include
@@ -97,7 +97,7 @@ ingenic_efuse_attach(device_t parent, de
ingenic_set_enaddr(>sc_data[0x1a]);
#ifdef INGENIC_DEBUG
{
- int i. j;
+ int i, j;
for (i = 0; i < 0x20; i += 8) {
printf("%02x:", i);
for (j = 0; j < 8; j++)
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Sun Aug 30 05:09:16 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_rng.c Log Message: add attribution, no functional change. from Michael McConville To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_rng.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_rng.c diff -u src/sys/arch/mips/ingenic/ingenic_rng.c:1.1 src/sys/arch/mips/ingenic/ingenic_rng.c:1.2 --- src/sys/arch/mips/ingenic/ingenic_rng.c:1.1 Fri Aug 7 17:39:58 2015 +++ src/sys/arch/mips/ingenic/ingenic_rng.c Sun Aug 30 05:09:16 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_rng.c,v 1.1 2015/08/07 17:39:58 macallan Exp $ */ +/* $NetBSD: ingenic_rng.c,v 1.2 2015/08/30 05:09:16 macallan Exp $ */ /*- * Copyright (c) 2015 Michael McConville @@ -27,7 +27,11 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_rng.c,v 1.1 2015/08/07 17:39:58 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_rng.c,v 1.2 2015/08/30 05:09:16 macallan Exp $); + +/* + * adapted from Jared McNeill's amlogic_rng.c + */ #include sys/param.h #include sys/systm.h
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Fri Aug 7 17:37:54 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
- sprinkle volatile
- add RNG registers
- fix some comments
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.20 src/sys/arch/mips/ingenic/ingenic_regs.h:1.21
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.20 Sat Jul 11 18:54:03 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Fri Aug 7 17:37:54 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.20 2015/07/11 18:54:03 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.21 2015/08/07 17:37:54 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -118,7 +118,7 @@
static inline void
writereg(uint32_t reg, uint32_t val)
{
- *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
+ *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
wbflush();
}
@@ -126,7 +126,7 @@ static inline uint32_t
readreg(uint32_t reg)
{
wbflush();
- return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
+ return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
}
/* extra CP0 registers */
@@ -223,8 +223,8 @@ MFC0(uint32_t r, uint32_t s)
#define OPCR_L2CM_ON 0x /* L2 stays on in sleep */
#define OPCR_L2CM_RET 0x0400 /* L2 retention mode in sleep */
#define OPCR_L2CM_OFF 0x0800 /* L2 powers down in sleep */
- #define OPCR_SPENDN0 0x0080 /* OTG port forced down */
- #define OPCR_SPENDN1 0x0040 /* UHC port forced down */
+ #define OPCR_SPENDN0 0x0080 /* 0 - OTG port forced down */
+ #define OPCR_SPENDN1 0x0040 /* 0 - UHC port forced down */
#define OPCR_BUS_MODE 0x0020 /* 1 - bursts */
#define OPCR_O1SE 0x0010 /* EXTCLK on in sleep */
#define OPCR_PD 0x0008 /* P0 down in sleep */
@@ -320,6 +320,15 @@ MFC0(uint32_t r, uint32_t s)
#define JZ_MSC1CDR 0x10a4
#define JZ_MSC2CDR 0x10a8
+/*
+ * random number generator
+ *
+ * Its function currently isn't documented by Ingenic.
+ * However, testing suggests that it works as expected.
+ */
+#define JZ_ERNG 0x10d8
+#define JZ_RNG 0x10dc
+
/* interrupt controller */
#define JZ_ICSR0 0x10001000 /* raw IRQ line status */
#define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Sat Jul 11 18:54:03 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: fix tpyos To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.19 src/sys/arch/mips/ingenic/ingenic_regs.h:1.20 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.19 Fri May 29 18:47:13 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Jul 11 18:54:03 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.19 2015/05/29 18:47:13 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.20 2015/07/11 18:54:03 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -144,7 +144,7 @@ MFC0(uint32_t r, uint32_t s) #define CP0_CORE_CTRL 12 /* select 2 */ #define CC_SW_RST0 1 /* reset core 0 */ #define CC_SW_RST1 2 /* reset core 1 */ - #define CC_RPC0 0x100 /* dedicater reset entry core 0 */ + #define CC_RPC0 0x100 /* dedicated reset entry core 0 */ #define CC_RPC1 0x200 /* -- || -- core 1 */ #define CC_SLEEP0M 0x1 /* mask sleep core 0 */ #define CC_SLEEP1M 0x2 /* mask sleep core 1 */ @@ -316,14 +316,6 @@ MFC0(uint32_t r, uint32_t s) #define MSCCDR_STOP 0x0800 #define MSCCDR_PHASE 0x8000 /* 0 - 90deg phase, 1 - 180 */ #define MSCCDR_DIV_M 0x00ff /* src / ((div + 1) * 2) */ -#define JZ_UHCCDR 0x106c /* UHC Clock Divider Register */ - #define UHCCDR_SCLK_A 0x - #define UHCCDR_MPLL 0x4000 - #define UHCCDR_EPLL 0x8000 - #define UHCCDR_OTG_PHY 0xc000 - #define UHCCDR_CE 0x2000 - #define UHCCDR_BUSY 0x1000 - #define UHCCDR_STOP 0x0800 #define UHCCDR_DIV_M 0x00ff #define JZ_MSC1CDR 0x10a4 #define JZ_MSC2CDR 0x10a8
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Fri May 29 18:47:13 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: fix pasto To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.18 src/sys/arch/mips/ingenic/ingenic_regs.h:1.19 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.18 Mon May 18 15:03:16 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Fri May 29 18:47:13 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.18 2015/05/18 15:03:16 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.19 2015/05/29 18:47:13 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -706,7 +706,7 @@ gpio_as_input(uint32_t g, int pin) #define JZ_MSC_RESTO 0x10 /* 16bit response timeout in MSC_CLK */ #define JZ_MSC_RDTO RW 0x14 /* 32bit read timeout in MSC_CLK */ #define JZ_MSC_BLKLEN 0x18 /* 16bit block length */ -#define JZ_MSC_NOB RW 0x1c /* 16bit block counter */ +#define JZ_MSC_NOB 0x1c /* 16bit block counter */ #define JZ_MSC_SNOB 0x20 /* 16bit successful block counter */ #define JZ_MSC_IMASK 0x24 /* interrupt mask */ #define JZ_INT_AUTO_CMD23_DONE 0x4000
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Mon May 18 15:11:47 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dwctwo.c
Log Message:
explicitly un-suspend the OTG port after PHY reset
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.10 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.11
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.10 Tue Apr 28 15:07:07 2015
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Mon May 18 15:11:47 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.11 2015/05/18 15:11:47 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.11 2015/05/18 15:11:47 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -154,6 +154,10 @@ ingenic_dwc2_attach(device_t parent, dev
#endif
reg = readreg(JZ_USBPCR1);
+#ifdef INGENIC_DEBUG
+ printf(JZ_USBPCR1 %08x\n, reg);
+#endif
+ reg = ~0xf000;
reg |= PCR_SYNOPSYS;
reg |= PCR_REFCLK_CORE;
reg = ~PCR_CLK_M;
@@ -166,6 +170,7 @@ ingenic_dwc2_attach(device_t parent, dev
printf(JZ_USBRDT %08x\n, readreg(JZ_USBRDT));
#endif
+ writereg(JZ_USBVBFIL, 0);
delay(1);
reg = readreg(JZ_USBPCR);
@@ -177,6 +182,11 @@ ingenic_dwc2_attach(device_t parent, dev
delay(1);
+ /* wake up the USB part */
+ reg = readreg(JZ_OPCR);
+ reg |= OPCR_SPENDN0;
+ writereg(JZ_OPCR, reg);
+
sc-sc_ih = evbmips_intr_establish(aa-aa_irq, dwc2_intr, sc-sc_dwc2);
if (sc-sc_ih == NULL) {
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Mon May 18 15:03:16 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: add some clock divider registers To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.17 src/sys/arch/mips/ingenic/ingenic_regs.h:1.18 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.17 Mon May 4 12:16:24 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Mon May 18 15:03:16 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.17 2015/05/04 12:16:24 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.18 2015/05/18 15:03:16 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -269,6 +269,7 @@ MFC0(uint32_t r, uint32_t s) #define PCR_TXHSXVTUNE 0x0030 #define PCR_TXVREFTUNE 0x000f #define JZ_USBRDT 0x1040 /* Reset Detect Timer Register */ +#define JZ_USBVBFIL 0x1044 #define JZ_USBPCR1 0x1048 #define PCR_SYNOPSYS 0x1000 /* Mentor mode otherwise */ #define PCR_REFCLK_CORE 0x0c00 @@ -306,6 +307,27 @@ MFC0(uint32_t r, uint32_t s) #define JZ_SPCR1 0x10bc #define JZ_SRBC 0x10c4 /* Soft Reset Bus Control */ +/* clock divider registers */ +#define JZ_MSC0CDR 0x1068 + #define MSCCDR_SCLK_A 0x4000 + #define MSCCDR_MPLL 0x8000 + #define MSCCDR_CE 0x2000 + #define MSCCDR_BUSY 0x1000 + #define MSCCDR_STOP 0x0800 + #define MSCCDR_PHASE 0x8000 /* 0 - 90deg phase, 1 - 180 */ + #define MSCCDR_DIV_M 0x00ff /* src / ((div + 1) * 2) */ +#define JZ_UHCCDR 0x106c /* UHC Clock Divider Register */ + #define UHCCDR_SCLK_A 0x + #define UHCCDR_MPLL 0x4000 + #define UHCCDR_EPLL 0x8000 + #define UHCCDR_OTG_PHY 0xc000 + #define UHCCDR_CE 0x2000 + #define UHCCDR_BUSY 0x1000 + #define UHCCDR_STOP 0x0800 + #define UHCCDR_DIV_M 0x00ff +#define JZ_MSC1CDR 0x10a4 +#define JZ_MSC2CDR 0x10a8 + /* interrupt controller */ #define JZ_ICSR0 0x10001000 /* raw IRQ line status */ #define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Mon May 18 15:07:53 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_var.h
Log Message:
pass the appropriate clock register to devices so different instances of the
same driver don't have to guess
also wire the ddc2 part to iic4 for now so we can see the monitor
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ingenic/ingenic_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.14 src/sys/arch/mips/ingenic/apbus.c:1.15
--- src/sys/arch/mips/ingenic/apbus.c:1.14 Mon May 4 12:23:15 2015
+++ src/sys/arch/mips/ingenic/apbus.c Mon May 18 15:07:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.15 2015/05/18 15:07:52 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.15 2015/05/18 15:07:52 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -68,29 +68,30 @@ typedef struct apbus_dev {
uint32_t irq; /* interrupt */
uint32_t clk0; /* bit(s) in CLKGR0 */
uint32_t clk1; /* bit(s) in CLKGR1 */
+ uint32_t clkreg; /* CGU register */
} apbus_dev_t;
static const apbus_dev_t apbus_devs[] = {
- { dwctwo, JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1},
- { ohci, JZ_OHCI_BASE,5, CLK_UHC, 0},
- { ehci, JZ_EHCI_BASE, 20, CLK_UHC, 0},
- { dme, JZ_DME_BASE,-1, 0, 0},
- { jzgpio, JZ_GPIO_A_BASE, 17, 0, 0},
- { jzgpio, JZ_GPIO_B_BASE, 16, 0, 0},
- { jzgpio, JZ_GPIO_C_BASE, 15, 0, 0},
- { jzgpio, JZ_GPIO_D_BASE, 14, 0, 0},
- { jzgpio, JZ_GPIO_E_BASE, 13, 0, 0},
- { jzgpio, JZ_GPIO_F_BASE, 12, 0, 0},
- { jziic, JZ_SMB0_BASE, 60, CLK_SMB0, 0},
- { jziic, JZ_SMB1_BASE, 59, CLK_SMB1, 0},
- { jziic, JZ_SMB2_BASE, 58, CLK_SMB2, 0},
- { jziic, JZ_SMB3_BASE, 57, 0, CLK_SMB3},
- { jziic, JZ_SMB4_BASE, 56, 0, CLK_SMB4},
- { jzmmc, JZ_MSC0_BASE, 37, CLK_MSC0, 0},
- { jzmmc, JZ_MSC1_BASE, 36, CLK_MSC1, 0},
- { jzmmc, JZ_MSC2_BASE, 35, CLK_MSC2, 0},
- { jzfb, JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI},
- { NULL, -1, -1, 0, 0}
+ { dwctwo, JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1, 0},
+ { ohci, JZ_OHCI_BASE,5, CLK_UHC, 0, 0},
+ { ehci, JZ_EHCI_BASE, 20, CLK_UHC, 0, 0},
+ { dme, JZ_DME_BASE,-1, 0, 0, 0},
+ { jzgpio, JZ_GPIO_A_BASE, 17, 0, 0, 0},
+ { jzgpio, JZ_GPIO_B_BASE, 16, 0, 0, 0},
+ { jzgpio, JZ_GPIO_C_BASE, 15, 0, 0, 0},
+ { jzgpio, JZ_GPIO_D_BASE, 14, 0, 0, 0},
+ { jzgpio, JZ_GPIO_E_BASE, 13, 0, 0, 0},
+ { jzgpio, JZ_GPIO_F_BASE, 12, 0, 0, 0},
+ { jziic, JZ_SMB0_BASE, 60, CLK_SMB0, 0, 0},
+ { jziic, JZ_SMB1_BASE, 59, CLK_SMB1, 0, 0},
+ { jziic, JZ_SMB2_BASE, 58, CLK_SMB2, 0, 0},
+ { jziic, JZ_SMB3_BASE, 57, 0, CLK_SMB3, 0},
+ { jziic, JZ_SMB4_BASE, 56, 0, CLK_SMB4, 0},
+ { jzmmc, JZ_MSC0_BASE, 37, CLK_MSC0, 0, JZ_MSC0CDR},
+ { jzmmc, JZ_MSC1_BASE, 36, CLK_MSC1, 0, JZ_MSC1CDR},
+ { jzmmc, JZ_MSC2_BASE, 35, CLK_MSC2, 0, JZ_MSC2CDR},
+ { jzfb, JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI, 0},
+ { NULL, -1, -1, 0, 0, 0}
};
void
@@ -179,10 +180,15 @@ apbus_attach(device_t parent, device_t s
/* these are supposed to be connected to the RTC */
gpio_as_dev1(4, 12);
gpio_as_dev1(4, 13);
- /* these can be DDC2 or SMB4, set them to DDC2 */
+ /* these can be DDC2 or SMB4 */
+#if 1
+ /* DDC2 devices show up at SMB4 */
+ gpio_as_dev1(5, 24);
+ gpio_as_dev1(5, 25);
+#else
gpio_as_dev0(5, 24);
gpio_as_dev0(5, 25);
-
+#endif
/* MSC0 */
gpio_as_dev1(0, 4);
gpio_as_dev1(0, 5);
@@ -232,6 +238,7 @@ apbus_attach(device_t parent, device_t s
aa.aa_bst = apbus_memt;
aa.aa_pclk = pclk;
aa.aa_mclk = mclk;
+ aa.aa_clockreg = adv-clkreg;
/* enable clocks as needed */
if (adv-clk0 != 0) {
Index: src/sys/arch/mips/ingenic/ingenic_var.h
diff -u src/sys/arch/mips/ingenic/ingenic_var.h:1.4 src/sys/arch/mips/ingenic/ingenic_var.h:1.5
--- src/sys/arch/mips/ingenic/ingenic_var.h:1.4 Mon May 4 12:23:15 2015
+++ src/sys/arch/mips/ingenic/ingenic_var.h Mon May 18 15:07:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_var.h,v 1.4 2015/05/04 12:23:15 macallan Exp $ */
+/* $NetBSD: ingenic_var.h,v 1.5 2015/05/18 15:07:52 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -39,6 +39,7 @@ struct apbus_attach_args {
uint32_t aa_irq;
uint32_t aa_pclk; /* PCLK in kHz */
uint32_t aa_mclk; /* MCLK in kHz */
+ uint32_t aa_clockreg;
};
extern bus_space_tag_t ingenic_memt;
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Mon May 4 12:16:24 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
moar registers
( clock and gpio related )
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.16 src/sys/arch/mips/ingenic/ingenic_regs.h:1.17
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.16 Tue Apr 28 15:05:45 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Mon May 4 12:16:24 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.16 2015/04/28 15:05:45 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.17 2015/05/04 12:16:24 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -170,6 +170,8 @@ MFC0(uint32_t r, uint32_t s)
#define JZ_CPCCR 0x1000 /* Clock Control Register */
#define JZ_PDIV_M 0x000f /* PCLK divider mask */
#define JZ_PDIV_S 16 /* PCLK divider shift */
+ #define JZ_CDIV_M 0x000f /* CPU clock divider mask */
+ #define JZ_CDIV_S 0 /* CPU clock divider shift */
#define JZ_CPMPCR 0x0014 /* MPLL */
#define JZ_PLLM_S 19 /* PLL multiplier shift */
#define JZ_PLLM_M 0xfff8 /* PLL multiplier mask */
@@ -292,6 +294,14 @@ MFC0(uint32_t r, uint32_t s)
#define PCR_TXRISETUNE1 0x0001 /* rise/fall wave adj. */
#define JZ_UHCCDR 0x106c /* UHC Clock Divider Register */
+ #define UHCCDR_SCLK_A 0x
+ #define UHCCDR_MPLL 0x4000
+ #define UHCCDR_EPLL 0x8000
+ #define UHCCDR_OTG_PHY 0xc000
+ #define UHCCDR_CE 0x2000
+ #define UHCCDR_BUSY 0x1000
+ #define UHCCDR_STOP 0x0800
+ #define UHCCDR_DIV_M 0x00ff
#define JZ_SPCR0 0x10b8 /* SRAM Power Control Registers */
#define JZ_SPCR1 0x10bc
#define JZ_SRBC 0x10c4 /* Soft Reset Bus Control */
@@ -477,6 +487,32 @@ gpio_as_intr_level(uint32_t g, int pin)
writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */
}
+static inline void
+gpio_as_intr_level_low(uint32_t g, int pin)
+{
+ uint32_t mask = 1 pin;
+ uint32_t reg = JZ_GPIO_A_BASE + (g 8);
+
+ writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */
+ writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */
+ writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */
+ writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */
+ writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */
+ writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */
+}
+
+static inline void
+gpio_as_input(uint32_t g, int pin)
+{
+ uint32_t mask = 1 pin;
+ uint32_t reg = JZ_GPIO_A_BASE + (g 8);
+
+ writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */
+ writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */
+ writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */
+ writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */
+}
+
/* I2C / SMBus */
#define JZ_SMB0_BASE 0x1005
#define JZ_SMB1_BASE 0x10051000
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Mon May 4 12:23:15 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_var.h
Log Message:
- fix pclk calculation
- report CPU clock
- pass mclk to child devices
- wire up pins for MSC / sdmmc
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.13 src/sys/arch/mips/ingenic/apbus.c:1.14
--- src/sys/arch/mips/ingenic/apbus.c:1.13 Tue Apr 28 15:08:07 2015
+++ src/sys/arch/mips/ingenic/apbus.c Mon May 4 12:23:15 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.13 2015/04/28 15:08:07 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.13 2015/04/28 15:08:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.14 2015/05/04 12:23:15 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -118,7 +118,7 @@ apbus_match(device_t parent, cfdata_t ma
void
apbus_attach(device_t parent, device_t self, void *aux)
{
- uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv;
+ uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv;
aprint_normal(\n);
/* should have been called early on */
@@ -140,12 +140,14 @@ apbus_attach(device_t parent, device_t s
mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
reg = readreg(JZ_CPCCR);
- pdiv = (reg JZ_PDIV_M) JZ_PDIV_S;
+ pdiv = ((reg JZ_PDIV_M) JZ_PDIV_S) + 1;
pclk = mclk / pdiv;
-#ifdef INGENIC_DEBUG
- printf(mclk %d kHz\n, mclk);
- printf(pclk %d kHz\n, pclk);
-#endif
+ cdiv = (reg JZ_CDIV_M) + 1;
+ cclk = mclk / cdiv;
+
+ aprint_debug_dev(self, mclk %d kHz\n, mclk);
+ aprint_debug_dev(self, pclk %d kHz\n, pclk);
+ aprint_debug_dev(self, CPU clock %d kHz\n, cclk);
/* enable clocks */
reg = readreg(JZ_CLKGR1);
@@ -157,7 +159,7 @@ apbus_attach(device_t parent, device_t s
reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
writereg(JZ_OPCR, reg);
- /* setup GPIOs for I2C buses */
+ /* wire up GPIOs */
/* iic0 */
gpio_as_dev0(3, 30);
gpio_as_dev0(3, 31);
@@ -181,6 +183,36 @@ apbus_attach(device_t parent, device_t s
gpio_as_dev0(5, 24);
gpio_as_dev0(5, 25);
+ /* MSC0 */
+ gpio_as_dev1(0, 4);
+ gpio_as_dev1(0, 5);
+ gpio_as_dev1(0, 6);
+ gpio_as_dev1(0, 7);
+ gpio_as_dev1(0, 18);
+ gpio_as_dev1(0, 19);
+ gpio_as_dev1(0, 20);
+ gpio_as_dev1(0, 21);
+ gpio_as_dev1(0, 22);
+ gpio_as_dev1(0, 23);
+ gpio_as_dev1(0, 24);
+ gpio_as_intr_level_low(5, 20); /* card detect */
+
+ /* MSC1, for wifi/bt */
+ gpio_as_dev0(3, 20);
+ gpio_as_dev0(3, 21);
+ gpio_as_dev0(3, 22);
+ gpio_as_dev0(3, 23);
+ gpio_as_dev0(3, 24);
+ gpio_as_dev0(3, 25);
+
+ /* MSC2, on expansion header */
+ gpio_as_dev0(1, 20);
+ gpio_as_dev0(1, 21);
+ gpio_as_dev0(1, 28);
+ gpio_as_dev0(1, 29);
+ gpio_as_dev0(1, 30);
+ gpio_as_dev0(1, 31);
+
#ifdef INGENIC_DEBUG
printf(JZ_CLKGR0 %08x\n, readreg(JZ_CLKGR0));
printf(JZ_CLKGR1 %08x\n, readreg(JZ_CLKGR1));
@@ -199,6 +231,7 @@ apbus_attach(device_t parent, device_t s
aa.aa_dmat = apbus_dmat;
aa.aa_bst = apbus_memt;
aa.aa_pclk = pclk;
+ aa.aa_mclk = mclk;
/* enable clocks as needed */
if (adv-clk0 != 0) {
Index: src/sys/arch/mips/ingenic/ingenic_var.h
diff -u src/sys/arch/mips/ingenic/ingenic_var.h:1.3 src/sys/arch/mips/ingenic/ingenic_var.h:1.4
--- src/sys/arch/mips/ingenic/ingenic_var.h:1.3 Wed Mar 25 11:25:10 2015
+++ src/sys/arch/mips/ingenic/ingenic_var.h Mon May 4 12:23:15 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_var.h,v 1.3 2015/03/25 11:25:10 macallan Exp $ */
+/* $NetBSD: ingenic_var.h,v 1.4 2015/05/04 12:23:15 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -38,6 +38,7 @@ struct apbus_attach_args {
bus_addr_t aa_addr;
uint32_t aa_irq;
uint32_t aa_pclk; /* PCLK in kHz */
+ uint32_t aa_mclk; /* MCLK in kHz */
};
extern bus_space_tag_t ingenic_memt;
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Apr 28 15:05:45 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
add sdmmc ('MSC') registers
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.15 src/sys/arch/mips/ingenic/ingenic_regs.h:1.16
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.15 Thu Apr 23 01:20:20 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Apr 28 15:05:45 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.15 2015/04/23 01:20:20 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.16 2015/04/28 15:05:45 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -557,4 +557,166 @@ gpio_as_intr_level(uint32_t g, int pin)
#define JZ_MSC1_BASE 0x1346
#define JZ_MSC2_BASE 0x1347
+#define JZ_MSC_CTRL 0x00
+ #define JZ_SEND_CCSD 0x8000
+ #define JZ_SEND_AS_CCSD 0x4000
+ #define JZ_EXIT_MULTIPLE 0x0080
+ #define JZ_EXIT_TRANSFER 0x0040
+ #define JZ_START_READWAIT 0x0020
+ #define JZ_STOP_READWAIT 0x0010
+ #define JZ_RESET 0x0008
+ #define JZ_START_OP 0x0004
+ #define JZ_CLOCK_CTRL_M 0x0003
+ #define JZ_CLOCK_START 0x0002
+ #define JZ_CLOCK_STOP 0x0001
+#define JZ_MSC_STAT 0x04
+ #define JZ_AUTO_CMD12_DONE 0x8000
+ #define JZ_AUTO_CMD23_DONE 0x4000
+ #define JZ_SVS 0x2000
+ #define JZ_PIN_LEVEL_M 0x1f00
+ #define JZ_BCE 0x0010 /* boot CRC error */
+ #define JZ_BDE 0x0008 /* boot data end */
+ #define JZ_BAE 0x0004 /* boot acknowledge error */
+ #define JZ_BAR 0x0002 /* boot ack. received */
+ #define JZ_DMAEND 0x0001
+ #define JZ_IS_RESETTING 0x8000
+ #define JZ_SDIO_INT_ACTIVE 0x4000
+ #define JZ_PRG_DONE 0x2000
+ #define JZ_DATA_TRAN_DONE 0x1000
+ #define JZ_END_CMD_RES 0x0800
+ #define JZ_DATA_FIFO_AFULL 0x0400
+ #define JZ_IS_READWAIT 0x0200
+ #define JZ_CLK_EN 0x0100
+ #define JZ_DATA_FIFO_FULL 0x0080
+ #define JZ_DATA_FIFO_EMPTY 0x0040
+ #define JZ_CRC_RES_ERR 0x0020
+ #define JZ_CRC_READ_ERR 0x0010
+ #define JZ_CRC_WRITE_ERR_M 0x000c
+ #define JZ_CRC_WRITE_OK 0x
+ #define JZ_CRC_CARD_ERR 0x0004
+ #define JZ_CRC_NO_STATUS 0x0008
+ #define JZ_TIME_OUT_RES 0x0002
+ #define JZ_TIME_OUT_READ 0x0001
+#define JZ_MSC_CLKRT 0x08
+ #define JZ_DEV_CLK 0x0
+ #define JZ_DEV_CLK_2 0x1 /* DEV_CLK / 2 */
+ #define JZ_DEV_CLK_4 0x2 /* DEV_CLK / 4 */
+ #define JZ_DEV_CLK_8 0x3 /* DEV_CLK / 8 */
+ #define JZ_DEV_CLK_16 0x4 /* DEV_CLK / 16 */
+ #define JZ_DEV_CLK_32 0x5 /* DEV_CLK / 32 */
+ #define JZ_DEV_CLK_64 0x6 /* DEV_CLK / 64 */
+ #define JZ_DEV_CLK_128 0x7 /* DEV_CLK / 128 */
+#define JZ_MSC_CMDAT 0x0c
+ #define JZ_CCS_EXPECTED 0x8000
+ #define JZ_READ_CEATA 0x4000
+ #define JZ_DIS_BOOT 0x0800
+ #define JZ_ENA_BOOT 0x0400
+ #define JZ_EXP_BOOT_ACK 0x0200
+ #define JZ_BOOT_MODE 0x0100
+ #define JZ_AUTO_CMD23 0x0004
+ #define JZ_SDIO_PRDT 0x0002
+ #define JZ_AUTO_CMD12 0x0001
+ #define JZ_RTRG_M 0xc000 /* receive FIFO trigger */
+ #define JZ_RTRG_16 0x /* = 16 */
+ #define JZ_RTRG_32 0x4000 /* = 32 */
+ #define JZ_RTRG_64 0x8000 /* = 64 */
+ #define JZ_RTRG_96 0xc000 /* = 96 */
+ #define JZ_TTRG_M 0x3000 /* transmit FIFO trigger */
+ #define JZ_TTRG_16 0x /* = 16 */
+ #define JZ_TTRG_32 0x1000 /* = 32 */
+ #define JZ_TTRG_64 0x2000 /* = 64 */
+ #define JZ_TTRG_96 0x3000 /* = 96 */
+ #define JZ_IO_ABORT 0x0800
+ #define JZ_BUS_WIDTH_M 0x0600
+ #define JZ_BUS_1BIT 0x
+ #define JZ_BUS_4BIT 0x0200
+ #define JZ_BUS_8BIT 0x0300
+ #define JZ_INIT 0x0080 /* send 80 clk init before cmd */
+ #define JZ_BUSY 0x0040
+ #define JZ_STREAM 0x0020
+ #define JZ_WRITE 0x0010 /* read otherwise */
+ #define JZ_DATA_EN 0x0008
+ #define JZ_RESPONSE_M 0x0007 /* response format */
+ #define JZ_RES_NONE 0x
+ #define JZ_RES_R1 0x0001 /* R1 and R1b */
+ #define JZ_RES_R2 0x0002
+ #define JZ_RES_R3 0x0003
+ #define JZ_RES_R4 0x0004
+ #define JZ_RES_R5 0x0005
+ #define JZ_RES_R6 0x0006
+ #define JZ_RES_R7 0x0007
+#define JZ_MSC_RESTO 0x10 /* 16bit response timeout in MSC_CLK */
+#define JZ_MSC_RDTO RW 0x14 /* 32bit read timeout in MSC_CLK */
+#define JZ_MSC_BLKLEN 0x18 /* 16bit block length */
+#define JZ_MSC_NOB RW 0x1c /* 16bit block counter */
+#define JZ_MSC_SNOB 0x20 /* 16bit successful block counter */
+#define JZ_MSC_IMASK 0x24 /* interrupt mask */
+ #define JZ_INT_AUTO_CMD23_DONE 0x4000
+ #define JZ_INT_SVS 0x2000
+ #define JZ_INT_PIN_LEVEL_M 0x1f00
+ #define JZ_INT_BCE 0x0010
+ #define JZ_INT_BDE 0x0008
+ #define JZ_INT_BAE 0x0004
+
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Apr 28 15:08:07 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
add entries for sdmmc hosts, no driver yet
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.12 src/sys/arch/mips/ingenic/apbus.c:1.13
--- src/sys/arch/mips/ingenic/apbus.c:1.12 Tue Apr 21 19:57:41 2015
+++ src/sys/arch/mips/ingenic/apbus.c Tue Apr 28 15:08:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.12 2015/04/21 19:57:41 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.13 2015/04/28 15:08:07 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.12 2015/04/21 19:57:41 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.13 2015/04/28 15:08:07 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -86,6 +86,9 @@ static const apbus_dev_t apbus_devs[] =
{ jziic, JZ_SMB2_BASE, 58, CLK_SMB2, 0},
{ jziic, JZ_SMB3_BASE, 57, 0, CLK_SMB3},
{ jziic, JZ_SMB4_BASE, 56, 0, CLK_SMB4},
+ { jzmmc, JZ_MSC0_BASE, 37, CLK_MSC0, 0},
+ { jzmmc, JZ_MSC1_BASE, 36, CLK_MSC1, 0},
+ { jzmmc, JZ_MSC2_BASE, 35, CLK_MSC2, 0},
{ jzfb, JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI},
{ NULL, -1, -1, 0, 0}
};
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Apr 28 15:07:07 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_dwctwo.c Log Message: 'USB' - 'USB OTG' to distinguish this one from the other USB hosts To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/ingenic/ingenic_dwctwo.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.9 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.10 --- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.9 Tue Mar 17 09:27:09 2015 +++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Apr 28 15:07:07 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_dwctwo.c,v 1.9 2015/03/17 09:27:09 macallan Exp $ */ +/* $NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.9 2015/03/17 09:27:09 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.10 2015/04/28 15:07:07 macallan Exp $); /* * adapted from bcm2835_dwctwo.c @@ -134,9 +134,10 @@ ingenic_dwc2_attach(device_t parent, dev return; } - aprint_naive(: USB controller\n); - aprint_normal(: USB controller\n); + aprint_naive(: USB OTG controller\n); + aprint_normal(: USB OTG controller\n); + /* reset PHY, flash LED */ gpio_set(5, 15, 0); delay(25); gpio_set(5, 15, 1);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Thu Apr 23 01:20:20 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: more bits registers To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.14 src/sys/arch/mips/ingenic/ingenic_regs.h:1.15 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.14 Tue Apr 21 19:56:01 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Thu Apr 23 01:20:20 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.14 2015/04/21 19:56:01 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.15 2015/04/23 01:20:20 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -181,12 +181,39 @@ MFC0(uint32_t r, uint32_t s) #define JZ_PLLBP 0x0002 /* PLL bypass */ #define JZ_PLLEN 0x0001 /* PLL enable */ #define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */ + #define CLK_NEMC (1 0) + #define CLK_BCH (1 1) #define CLK_OTG0 (1 2) + #define CLK_MSC0 (1 3) + #define CLK_SSI0 (1 4) #define CLK_SMB0 (1 5) #define CLK_SMB1 (1 6) + #define CLK_SCC (1 7) + #define CLK_AIC (1 8) + #define CLK_TSSI0 (1 9) + #define CLK_OWI (1 10) + #define CLK_MSC1 (1 11) + #define CLK_MSC2 (1 12) + #define CLK_KBC (1 13) + #define CLK_SADC (1 14) + #define CLK_UART0 (1 15) + #define CLK_UART1 (1 16) + #define CLK_UART2 (1 17) + #define CLK_UART3 (1 18) + #define CLK_SSI1 (1 19) + #define CLK_SSI2 (1 20) + #define CLK_PDMA (1 21) + #define CLK_GPS (1 22) + #define CLK_MAC (1 23) #define CLK_UHC (1 24) #define CLK_SMB2 (1 25) + #define CLK_CIM (1 26) + #define CLK_TVE (1 27) #define CLK_LCD (1 28) + #define CLK_IPU (1 29) + #define CLK_DDR0 (1 30) + #define CLK_DDR1 (1 31) + #define JZ_OPCR 0x1024 /* Oscillator Power Control Reg. */ #define OPCR_IDLE_DIS 0x8000 /* don't stop CPU clk on idle */ #define OPCR_GPU_CLK_ST 0x4000 /* stop GPU clock */ @@ -204,10 +231,21 @@ MFC0(uint32_t r, uint32_t s) #define OPCR_OSE 0x0001 /* disable EXTCLK */ #define JZ_CLKGR1 0x1028 /* CLocK Gating Registers */ #define CLK_SMB3 (1 0) + #define CLK_TSSI1 (1 1) + #define CLK_VPU (1 2) + #define CLK_PCM (1 3) + #define CLK_GPU (1 4) + #define CLK_COMPRESS (1 5) + #define CLK_AIC1 (1 6) + #define CLK_GPVLC (1 7) #define CLK_OTG1 (1 8) #define CLK_HDMI (1 9) + #define CLK_UART4 (1 10) #define CLK_AHB_MON (1 11) #define CLK_SMB4 (1 12) + #define CLK_DES (1 13) + #define CLK_X2D (1 14) + #define CLK_P1 (1 15) #define JZ_USBPCR 0x103c #define PCR_USB_MODE 0x8000 /* 1 - otg */ @@ -514,4 +552,9 @@ gpio_as_intr_level(uint32_t g, int pin) #define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ #define JZ_HDENB 0x100 /* enable hold time */ +/* SD/MMC hosts */ +#define JZ_MSC0_BASE 0x1345 +#define JZ_MSC1_BASE 0x1346 +#define JZ_MSC2_BASE 0x1347 + #endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Apr 21 06:12:41 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: jziic.c
Log Message:
support interrupt-driven transfers
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/jziic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/jziic.c
diff -u src/sys/arch/mips/ingenic/jziic.c:1.1 src/sys/arch/mips/ingenic/jziic.c:1.2
--- src/sys/arch/mips/ingenic/jziic.c:1.1 Sat Apr 4 12:28:52 2015
+++ src/sys/arch/mips/ingenic/jziic.c Tue Apr 21 06:12:41 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: jziic.c,v 1.1 2015/04/04 12:28:52 macallan Exp $ */
+/* $NetBSD: jziic.c,v 1.2 2015/04/21 06:12:41 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: jziic.c,v 1.1 2015/04/04 12:28:52 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: jziic.c,v 1.2 2015/04/21 06:12:41 macallan Exp $);
/*
* a preliminary driver for JZ4780's on-chip SMBus controllers
@@ -39,10 +39,12 @@ __KERNEL_RCSID(0, $NetBSD: jziic.c,v 1.
#include sys/param.h
#include sys/systm.h
+#include sys/kernel.h
#include sys/device.h
#include sys/mutex.h
#include sys/bus.h
#include sys/mutex.h
+#include sys/condvar.h
#include mips/ingenic/ingenic_var.h
#include mips/ingenic/ingenic_regs.h
@@ -53,34 +55,54 @@ __KERNEL_RCSID(0, $NetBSD: jziic.c,v 1.
#ifdef JZIIC_DEBUG
#define DPRINTF aprint_error
+#define STATIC /* */
#else
#define DPRINTF while (0) printf
+#define STATIC static
#endif
-static int jziic_match(device_t, struct cfdata *, void *);
-static void jziic_attach(device_t, device_t, void *);
+
+STATIC int jziic_match(device_t, struct cfdata *, void *);
+STATIC void jziic_attach(device_t, device_t, void *);
struct jziic_softc {
device_t sc_dev;
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
struct i2c_controller sc_i2c;
- kmutex_t sc_buslock;
+ kmutex_t sc_buslock, sc_cvlock;
uint32_t sc_pclk;
+ /* stuff used for interrupt-driven transfers */
+ const uint8_t *sc_cmd;
+ uint8_t *sc_buf;
+ uint32_t sc_cmdlen, sc_buflen;
+ uint32_t sc_cmdptr, sc_bufptr, sc_rds;
+ uint32_t sc_abort;
+ kcondvar_t sc_ping;
+ uint8_t sc_txbuf[256];
+ boolean_t sc_reading;
};
CFATTACH_DECL_NEW(jziic, sizeof(struct jziic_softc),
jziic_match, jziic_attach, NULL, NULL);
-static int jziic_enable(struct jziic_softc *);
-static void jziic_disable(struct jziic_softc *);
-static int jziic_i2c_acquire_bus(void *, int);
-static void jziic_i2c_release_bus(void *, int);
-static int jziic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
+STATIC int jziic_enable(struct jziic_softc *);
+STATIC void jziic_disable(struct jziic_softc *);
+STATIC int jziic_wait(struct jziic_softc *);
+STATIC void jziic_set_speed(struct jziic_softc *);
+STATIC int jziic_i2c_acquire_bus(void *, int);
+STATIC void jziic_i2c_release_bus(void *, int);
+STATIC int jziic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
void *, size_t, int);
+STATIC int jziic_i2c_exec_poll(struct jziic_softc *, i2c_op_t, i2c_addr_t,
+const void *, size_t, void *, size_t, int);
+STATIC int jziic_i2c_exec_intr(struct jziic_softc *, i2c_op_t, i2c_addr_t,
+const void *, size_t, void *, size_t, int);
+
+STATIC int jziic_intr(void *);
/* ARGSUSED */
-static int
+STATIC int
jziic_match(device_t parent, struct cfdata *match, void *aux)
{
struct apbus_attach_args *aa = aux;
@@ -92,13 +114,14 @@ jziic_match(device_t parent, struct cfda
}
/* ARGSUSED */
-static void
+STATIC void
jziic_attach(device_t parent, device_t self, void *aux)
{
struct jziic_softc *sc = device_private(self);
struct apbus_attach_args *aa = aux;
struct i2cbus_attach_args iba;
int error;
+ void *ih;
#ifdef JZIIC_DEBUG
int i;
uint8_t in[1] = {0}, out[16];
@@ -116,19 +139,19 @@ jziic_attach(device_t parent, device_t s
}
mutex_init(sc-sc_buslock, MUTEX_DEFAULT, IPL_NONE);
+ mutex_init(sc-sc_cvlock, MUTEX_DEFAULT, IPL_NONE);
+ cv_init(sc-sc_ping, device_xname(self));
aprint_naive(: SMBus controller\n);
aprint_normal(: SMBus controller\n);
-#if notyet
- ih = evbmips_intr_establish(aa-aa_irq, ohci_intr, sc);
+ ih = evbmips_intr_establish(aa-aa_irq, jziic_intr, sc);
if (ih == NULL) {
aprint_error_dev(self, failed to establish interrupt %d\n,
aa-aa_irq);
goto fail;
}
-#endif
#ifdef JZIIC_DEBUG
if (jziic_i2c_exec(sc, I2C_OP_READ_WITH_STOP, 0x51, in, 1, out, 9, 0)
@@ -168,16 +191,14 @@ jziic_attach(device_t parent, device_t s
return;
-#if notyet
fail:
if (ih) {
evbmips_intr_disestablish(ih);
}
bus_space_unmap(sc-sc_memt, sc-sc_memh, 0x100);
-#endif
}
-static int
+STATIC int
jziic_enable(struct jziic_softc *sc)
{
int bail = 10;
@@ -194,7 +215,7 @@ jziic_enable(struct jziic_softc *sc)
return (reg !=
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Apr 21 19:19:31 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: fix comments, add LCDC*_BASEs To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.12 src/sys/arch/mips/ingenic/ingenic_regs.h:1.13 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.12 Wed Mar 25 11:23:26 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Apr 21 19:19:31 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.12 2015/03/25 11:23:26 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.13 2015/04/21 19:19:31 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -26,11 +26,12 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include mips/locore.h - #ifndef INGENIC_REGS_H #define INGENIC_REGS_H +/* for wbflush() */ +#include mips/locore.h + /* UARTs, mostly 16550 compatible with 32bit spaced registers */ #define JZ_UART0 0x1003 #define JZ_UART1 0x10031000 @@ -38,6 +39,10 @@ #define JZ_UART3 0x10033000 #define JZ_UART4 0x10034000 +/* LCD controller base addresses, registers are in jzfb_regs.h */ +#define JZ_LCDC0_BASE 0x1305 +#define JZ_LCDC1_BASE 0x130a + /* watchdog */ #define JZ_WDOG_TDR 0x10002000 /* compare */ #define JZ_WDOG_TCER 0x10002004 @@ -459,7 +464,7 @@ gpio_as_intr_level(uint32_t g, int pin) #define JZ_TXABT 0x40 /* ABORT occured */ #define JZ_TXEMP 0x10 /* TX FIFO is low */ #define JZ_TXOF 0x08 /* TX FIFO is high */ - #define JZ_RXFL 0x04 /* RX FIFO is low */ + #define JZ_RXFL 0x04 /* RX FIFO is at JZ_SMBRXTL*/ #define JZ_RXOF 0x02 /* RX FIFO is high */ #define JZ_RXUF 0x01 /* RX FIFO underflow */ #define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Apr 21 19:57:41 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
enable clocks as needed
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.11 src/sys/arch/mips/ingenic/apbus.c:1.12
--- src/sys/arch/mips/ingenic/apbus.c:1.11 Wed Mar 25 11:25:10 2015
+++ src/sys/arch/mips/ingenic/apbus.c Tue Apr 21 19:57:41 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.12 2015/04/21 19:57:41 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.12 2015/04/21 19:57:41 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -63,29 +63,31 @@ struct mips_bus_dma_tag apbus_dmat = {
};
typedef struct apbus_dev {
- const char *name;
- bus_addr_t addr;
- uint32_t irq;
+ const char *name; /* driver name */
+ bus_addr_t addr; /* base address */
+ uint32_t irq; /* interrupt */
+ uint32_t clk0; /* bit(s) in CLKGR0 */
+ uint32_t clk1; /* bit(s) in CLKGR1 */
} apbus_dev_t;
static const apbus_dev_t apbus_devs[] = {
- { dwctwo, JZ_DWC2_BASE, 21},
- { ohci, JZ_OHCI_BASE,5 },
- { ehci, JZ_EHCI_BASE, 20},
- { dme, JZ_DME_BASE,-1}, /* irq via gpio abuse */
- { jzgpio, JZ_GPIO_A_BASE, 17},
- { jzgpio, JZ_GPIO_B_BASE, 16},
- { jzgpio, JZ_GPIO_C_BASE, 15},
- { jzgpio, JZ_GPIO_D_BASE, 14},
- { jzgpio, JZ_GPIO_E_BASE, 13},
- { jzgpio, JZ_GPIO_F_BASE, 12},
- { jziic, JZ_SMB0_BASE, 60},
- { jziic, JZ_SMB1_BASE, 59},
- { jziic, JZ_SMB2_BASE, 58},
- { jziic, JZ_SMB3_BASE, 57},
- { jziic, JZ_SMB4_BASE, 56},
- { jzfb, -1, -1},
- { NULL, -1, -1}
+ { dwctwo, JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1},
+ { ohci, JZ_OHCI_BASE,5, CLK_UHC, 0},
+ { ehci, JZ_EHCI_BASE, 20, CLK_UHC, 0},
+ { dme, JZ_DME_BASE,-1, 0, 0},
+ { jzgpio, JZ_GPIO_A_BASE, 17, 0, 0},
+ { jzgpio, JZ_GPIO_B_BASE, 16, 0, 0},
+ { jzgpio, JZ_GPIO_C_BASE, 15, 0, 0},
+ { jzgpio, JZ_GPIO_D_BASE, 14, 0, 0},
+ { jzgpio, JZ_GPIO_E_BASE, 13, 0, 0},
+ { jzgpio, JZ_GPIO_F_BASE, 12, 0, 0},
+ { jziic, JZ_SMB0_BASE, 60, CLK_SMB0, 0},
+ { jziic, JZ_SMB1_BASE, 59, CLK_SMB1, 0},
+ { jziic, JZ_SMB2_BASE, 58, CLK_SMB2, 0},
+ { jziic, JZ_SMB3_BASE, 57, 0, CLK_SMB3},
+ { jziic, JZ_SMB4_BASE, 56, 0, CLK_SMB4},
+ { jzfb, JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI},
+ { NULL, -1, -1, 0, 0}
};
void
@@ -144,20 +146,9 @@ apbus_attach(device_t parent, device_t s
/* enable clocks */
reg = readreg(JZ_CLKGR1);
- reg = ~(1 0); /* SMB3 clock */
- reg = ~(1 8); /* OTG1 clock */
- reg = ~(1 11); /* AHB_MON clock */
- reg = ~(1 12); /* SMB4 clock */
+ reg = ~CLK_AHB_MON; /* AHB_MON clock */
writereg(JZ_CLKGR1, reg);
- reg = readreg(JZ_CLKGR0);
- reg = ~(1 2); /* OTG0 clock */
- reg = ~(1 5); /* SMB0 clock */
- reg = ~(1 6); /* SMB1 clock */
- reg = ~(1 24); /* UHC clock */
- reg = ~(1 25); /* SMB2 clock */
- writereg(JZ_CLKGR0, reg);
-
/* wake up the USB part */
reg = readreg(JZ_OPCR);
reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
@@ -206,6 +197,19 @@ apbus_attach(device_t parent, device_t s
aa.aa_bst = apbus_memt;
aa.aa_pclk = pclk;
+ /* enable clocks as needed */
+ if (adv-clk0 != 0) {
+ reg = readreg(JZ_CLKGR0);
+ reg = ~adv-clk0;
+ writereg(JZ_CLKGR0, reg);
+ }
+
+ if (adv-clk1 != 0) {
+ reg = readreg(JZ_CLKGR1);
+ reg = ~adv-clk1;
+ writereg(JZ_CLKGR1, reg);
+ }
+
(void) config_found_ia(self, apbus, aa, apbus_print);
}
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Wed Mar 25 11:25:10 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_var.h
Log Message:
- determine bus clock, pass it to devices
- more clock enabling / gpio setup
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.10 src/sys/arch/mips/ingenic/apbus.c:1.11
--- src/sys/arch/mips/ingenic/apbus.c:1.10 Thu Mar 19 12:22:00 2015
+++ src/sys/arch/mips/ingenic/apbus.c Wed Mar 25 11:25:10 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.10 2015/03/19 12:22:00 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.10 2015/03/19 12:22:00 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.11 2015/03/25 11:25:10 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -113,7 +113,7 @@ apbus_match(device_t parent, cfdata_t ma
void
apbus_attach(device_t parent, device_t self, void *aux)
{
- uint32_t reg;
+ uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv;
aprint_normal(\n);
/* should have been called early on */
@@ -125,8 +125,24 @@ apbus_attach(device_t parent, device_t s
printf(REIM: %08x\n, MFC0(12, 4));
printf(ID: %08x\n, MFC0(15, 1));
#endif
+ /* assuming we're using MPLL */
+ mpll = readreg(JZ_CPMPCR);
+ m = (mpll JZ_PLLM_M) JZ_PLLM_S;
+ n = (mpll JZ_PLLN_M) JZ_PLLN_S;
+ p = (mpll JZ_PLLP_M) JZ_PLLP_S;
+
+ /* assuming 48MHz EXTCLK */
+ mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
+
+ reg = readreg(JZ_CPCCR);
+ pdiv = (reg JZ_PDIV_M) JZ_PDIV_S;
+ pclk = mclk / pdiv;
+#ifdef INGENIC_DEBUG
+ printf(mclk %d kHz\n, mclk);
+ printf(pclk %d kHz\n, pclk);
+#endif
- /* enable USB clocks */
+ /* enable clocks */
reg = readreg(JZ_CLKGR1);
reg = ~(1 0); /* SMB3 clock */
reg = ~(1 8); /* OTG1 clock */
@@ -135,6 +151,7 @@ apbus_attach(device_t parent, device_t s
writereg(JZ_CLKGR1, reg);
reg = readreg(JZ_CLKGR0);
+ reg = ~(1 2); /* OTG0 clock */
reg = ~(1 5); /* SMB0 clock */
reg = ~(1 6); /* SMB1 clock */
reg = ~(1 24); /* UHC clock */
@@ -146,6 +163,30 @@ apbus_attach(device_t parent, device_t s
reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
writereg(JZ_OPCR, reg);
+ /* setup GPIOs for I2C buses */
+ /* iic0 */
+ gpio_as_dev0(3, 30);
+ gpio_as_dev0(3, 31);
+ /* iic1 */
+ gpio_as_dev0(4, 30);
+ gpio_as_dev0(4, 31);
+ /* iic2 */
+ gpio_as_dev2(5, 16);
+ gpio_as_dev2(5, 17);
+ /* iic3 */
+ gpio_as_dev1(3, 10);
+ gpio_as_dev1(3, 11);
+ /* iic4 */
+ /* make sure these aren't SMB4 */
+ gpio_as_dev3(4, 3);
+ gpio_as_dev3(4, 4);
+ /* these are supposed to be connected to the RTC */
+ gpio_as_dev1(4, 12);
+ gpio_as_dev1(4, 13);
+ /* these can be DDC2 or SMB4, set them to DDC2 */
+ gpio_as_dev0(5, 24);
+ gpio_as_dev0(5, 25);
+
#ifdef INGENIC_DEBUG
printf(JZ_CLKGR0 %08x\n, readreg(JZ_CLKGR0));
printf(JZ_CLKGR1 %08x\n, readreg(JZ_CLKGR1));
@@ -163,6 +204,7 @@ apbus_attach(device_t parent, device_t s
aa.aa_irq = adv-irq;
aa.aa_dmat = apbus_dmat;
aa.aa_bst = apbus_memt;
+ aa.aa_pclk = pclk;
(void) config_found_ia(self, apbus, aa, apbus_print);
}
Index: src/sys/arch/mips/ingenic/ingenic_var.h
diff -u src/sys/arch/mips/ingenic/ingenic_var.h:1.2 src/sys/arch/mips/ingenic/ingenic_var.h:1.3
--- src/sys/arch/mips/ingenic/ingenic_var.h:1.2 Tue Mar 17 07:25:07 2015
+++ src/sys/arch/mips/ingenic/ingenic_var.h Wed Mar 25 11:25:10 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_var.h,v 1.2 2015/03/17 07:25:07 macallan Exp $ */
+/* $NetBSD: ingenic_var.h,v 1.3 2015/03/25 11:25:10 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -37,6 +37,7 @@ struct apbus_attach_args {
bus_dma_tag_t aa_dmat;
bus_addr_t aa_addr;
uint32_t aa_irq;
+ uint32_t aa_pclk; /* PCLK in kHz */
};
extern bus_space_tag_t ingenic_memt;
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Wed Mar 25 11:23:26 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
more clock and gpio stuff
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.11 src/sys/arch/mips/ingenic/ingenic_regs.h:1.12
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.11 Thu Mar 19 12:22:36 2015
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Wed Mar 25 11:23:26 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.11 2015/03/19 12:22:36 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.12 2015/03/25 11:23:26 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -162,6 +162,19 @@ MFC0(uint32_t r, uint32_t s)
#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
/* power management */
+#define JZ_CPCCR 0x1000 /* Clock Control Register */
+ #define JZ_PDIV_M 0x000f /* PCLK divider mask */
+ #define JZ_PDIV_S 16 /* PCLK divider shift */
+#define JZ_CPMPCR 0x0014 /* MPLL */
+ #define JZ_PLLM_S 19 /* PLL multiplier shift */
+ #define JZ_PLLM_M 0xfff8 /* PLL multiplier mask */
+ #define JZ_PLLN_S 13 /* PLL divider shift */
+ #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */
+ #define JZ_PLLP_S 9 /* PLL postdivider shift */
+ #define JZ_PLLP_M 0x1700 /* PLL postdivider mask */
+ #define JZ_PLLON 0x0010 /* PLL is on and stable */
+ #define JZ_PLLBP 0x0002 /* PLL bypass */
+ #define JZ_PLLEN 0x0001 /* PLL enable */
#define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */
#define JZ_OPCR 0x1024 /* Oscillator Power Control Reg. */
#define OPCR_IDLE_DIS 0x8000 /* don't stop CPU clk on idle */
@@ -360,6 +373,42 @@ gpio_as_dev0(uint32_t g, int pin)
}
static inline void
+gpio_as_dev1(uint32_t g, int pin)
+{
+ uint32_t mask = 1 pin;
+ uint32_t reg = JZ_GPIO_A_BASE + (g 8);
+
+ writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
+ writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
+ writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */
+ writereg(reg + JZ_GPIO_PAT0S, mask);
+}
+
+static inline void
+gpio_as_dev2(uint32_t g, int pin)
+{
+ uint32_t mask = 1 pin;
+ uint32_t reg = JZ_GPIO_A_BASE + (g 8);
+
+ writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
+ writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
+ writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */
+ writereg(reg + JZ_GPIO_PAT0C, mask);
+}
+
+static inline void
+gpio_as_dev3(uint32_t g, int pin)
+{
+ uint32_t mask = 1 pin;
+ uint32_t reg = JZ_GPIO_A_BASE + (g 8);
+
+ writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
+ writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
+ writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */
+ writereg(reg + JZ_GPIO_PAT0S, mask);
+}
+
+static inline void
gpio_as_intr_level(uint32_t g, int pin)
{
uint32_t mask = 1 pin;
@@ -446,5 +495,6 @@ gpio_as_intr_level(uint32_t g, int pin)
#define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */
#define JZ_SMBENBST 0x9C /* SMB Enable Status Register */
#define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */
+ #define JZ_HDENB 0x100 /* enable hold time */
#endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Thu Mar 19 12:22:00 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: apbus.c Log Message: spin up SMBus clocks before attaching drivers TODO: only enable clocks for drivers that actually attach To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/ingenic/apbus.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/apbus.c diff -u src/sys/arch/mips/ingenic/apbus.c:1.9 src/sys/arch/mips/ingenic/apbus.c:1.10 --- src/sys/arch/mips/ingenic/apbus.c:1.9 Tue Mar 17 09:26:31 2015 +++ src/sys/arch/mips/ingenic/apbus.c Thu Mar 19 12:22:00 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: apbus.c,v 1.9 2015/03/17 09:26:31 macallan Exp $ */ +/* $NetBSD: apbus.c,v 1.10 2015/03/19 12:22:00 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -29,7 +29,7 @@ /* catch-all for on-chip peripherals */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.9 2015/03/17 09:26:31 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.10 2015/03/19 12:22:00 macallan Exp $); #include locators.h #define _MIPS_BUS_DMA_PRIVATE @@ -128,12 +128,17 @@ apbus_attach(device_t parent, device_t s /* enable USB clocks */ reg = readreg(JZ_CLKGR1); + reg = ~(1 0); /* SMB3 clock */ reg = ~(1 8); /* OTG1 clock */ reg = ~(1 11); /* AHB_MON clock */ + reg = ~(1 12); /* SMB4 clock */ writereg(JZ_CLKGR1, reg); reg = readreg(JZ_CLKGR0); + reg = ~(1 5); /* SMB0 clock */ + reg = ~(1 6); /* SMB1 clock */ reg = ~(1 24); /* UHC clock */ + reg = ~(1 25); /* SMB2 clock */ writereg(JZ_CLKGR0, reg); /* wake up the USB part */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Thu Mar 19 12:22:36 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: add SMBus registers To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.10 src/sys/arch/mips/ingenic/ingenic_regs.h:1.11 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.10 Tue Mar 17 07:22:40 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Thu Mar 19 12:22:36 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.10 2015/03/17 07:22:40 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.11 2015/03/19 12:22:36 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -380,4 +380,71 @@ gpio_as_intr_level(uint32_t g, int pin) #define JZ_SMB3_BASE 0x10053000 #define JZ_SMB4_BASE 0x10054000 +/* SMBus register offsets, per port */ +#define JZ_SMBCON 0x00 /* SMB control */ + #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ + #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ + #define JZ_REST 0x20 /* 1 - allow RESTART */ + #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ + #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ + #define JZ_SPD_M 0x06 /* bus speed control */ + #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ + #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ + #define JZ_MD 0x01 /* enable master */ +#define JZ_SMBTAR 0x04 /* SMB target address */ + #define JZ_SMATP 0x1000 /* enable 10bit master addr */ + #define JZ_SPECIAL 0x0800 /* 1 - special command */ + #define JZ_START 0x0400 /* 1 - send START */ + #define JZ_SMBTAR_M 0x03ff /* target address */ +#define JZ_SMBSAR 0x08 /* SMB slave address */ +#define JZ_SMBDC 0x10 /* SMB data buffer and command */ + #define JZ_CMD 0x100 /* 1 - read, 0 - write */ + #define JZ_DATA 0x0ff +#define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ +#define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ +#define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ +#define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ +#define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ + #define JZ_ISTT 0x400 /* START or RESTART occured */ + #define JZ_ISTP 0x200 /* STOP occured */ + #define JZ_TXABT 0x40 /* ABORT occured */ + #define JZ_TXEMP 0x10 /* TX FIFO is low */ + #define JZ_TXOF 0x08 /* TX FIFO is high */ + #define JZ_RXFL 0x04 /* RX FIFO is low */ + #define JZ_RXOF 0x02 /* RX FIFO is high */ + #define JZ_RXUF 0x01 /* RX FIFO underflow */ +#define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ +#define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ +#define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ +#define JZ_SMBCINT 0x40 /* Clear Interrupts */ + #define JZ_CLEARALL 0x01 +#define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ +#define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ +#define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ +#define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ +#define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ +#define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ +#define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ +#define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ +#define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ +#define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ +#define JZ_SMBENB 0x6C /* SMB Enable */ + #define JZ_ENABLE 0x01 +#define JZ_SMBST 0x70 /* SMB Status register */ + #define JZ_SLVACT 0x40 /* slave is active */ + #define JZ_MSTACT 0x20 /* master is active */ + #define JZ_RFF 0x10 /* RX FIFO is full */ + #define JZ_RFNE 0x08 /* RX FIFO not empty */ + #define JZ_TFE 0x04 /* TX FIFO is empty */ + #define JZ_TFNF 0x02 /* TX FIFO is not full */ + #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ +#define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ +#define JZ_SMBDMACR 0x88 /* DMA Control Register */ +#define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ +#define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ +#define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ +#define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ +#define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ +#define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ + #endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Mar 17 07:22:40 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: add SMBus base addresses To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.9 src/sys/arch/mips/ingenic/ingenic_regs.h:1.10 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.9 Tue Mar 10 18:02:16 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Mar 17 07:22:40 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.9 2015/03/10 18:02:16 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.10 2015/03/17 07:22:40 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -372,4 +372,12 @@ gpio_as_intr_level(uint32_t g, int pin) writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ } + +/* I2C / SMBus */ +#define JZ_SMB0_BASE 0x1005 +#define JZ_SMB1_BASE 0x10051000 +#define JZ_SMB2_BASE 0x10052000 +#define JZ_SMB3_BASE 0x10053000 +#define JZ_SMB4_BASE 0x10054000 + #endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Mar 17 07:25:08 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_dwctwo.c ingenic_ehci.c
ingenic_ohci.c ingenic_var.h
Log Message:
- keep a list of devices, addresses and interrupts in apbus.c
- pass irq numbers to devices
- reduce magic numbers in device drivers
- allow multiple instances of device drivers
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/ingenic/apbus.c \
src/sys/arch/mips/ingenic/ingenic_dwctwo.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_ehci.c \
src/sys/arch/mips/ingenic/ingenic_ohci.c \
src/sys/arch/mips/ingenic/ingenic_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.7 src/sys/arch/mips/ingenic/apbus.c:1.8
--- src/sys/arch/mips/ingenic/apbus.c:1.7 Mon Mar 9 13:24:21 2015
+++ src/sys/arch/mips/ingenic/apbus.c Tue Mar 17 07:25:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.7 2015/03/09 13:24:21 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.8 2015/03/17 07:25:07 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.7 2015/03/09 13:24:21 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.8 2015/03/17 07:25:07 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -62,14 +62,30 @@ struct mips_bus_dma_tag apbus_dmat = {
._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
};
-static const char *apbus_devs[] = {
- dwctwo,
- ohci,
- ehci,
- dme,
- jzgpio,
- jzfb,
- NULL
+typedef struct apbus_dev {
+ const char *name;
+ bus_addr_t addr;
+ uint32_t irq;
+} apbus_dev_t;
+
+static const apbus_dev_t apbus_devs[] = {
+ { dwctwo, JZ_DWC2_BASE, 21},
+ { ohci, JZ_OHCI_BASE,5 },
+ { ehci, JZ_EHCI_BASE, 20},
+ { dme, JZ_DME_BASE,-1}, /* irq via gpio abuse */
+ { jzgpio, JZ_GPIO_A_BASE, 17},
+ { jzgpio, JZ_GPIO_B_BASE, 16},
+ { jzgpio, JZ_GPIO_C_BASE, 15},
+ { jzgpio, JZ_GPIO_D_BASE, 14},
+ { jzgpio, JZ_GPIO_E_BASE, 13},
+ { jzgpio, JZ_GPIO_F_BASE, 12},
+ { jziic, JZ_SMB0_BASE, 60},
+ { jziic, JZ_SMB1_BASE, 59},
+ { jziic, JZ_SMB2_BASE, 58},
+ { jziic, JZ_SMB3_BASE, 57},
+ { jziic, JZ_SMB4_BASE, 56},
+ { jzfb, -1, -1},
+ { NULL, -1, -1}
};
void
@@ -135,10 +151,11 @@ apbus_attach(device_t parent, device_t s
printf(JZ_UHCCDR %08x\n, readreg(JZ_UHCCDR));
#endif
- for (const char **adv = apbus_devs; *adv != NULL; adv++) {
+ for (const apbus_dev_t *adv = apbus_devs; adv-name != NULL; adv++) {
struct apbus_attach_args aa;
- aa.aa_name = *adv;
- aa.aa_addr = 0;
+ aa.aa_name = adv-name;
+ aa.aa_addr = adv-addr;
+ aa.aa_irq = adv-irq;
aa.aa_dmat = apbus_dmat;
aa.aa_bst = apbus_memt;
@@ -151,12 +168,13 @@ apbus_print(void *aux, const char *pnp)
{
struct apbus_attach_args *aa = aux;
- if (pnp)
+ if (pnp) {
aprint_normal(%s at %s, aa-aa_name, pnp);
-
- if (aa-aa_addr)
- aprint_normal( addr 0x% PRIxBUSADDR, aa-aa_addr);
-
+ if (aa-aa_addr != -1)
+ aprint_normal( addr 0x% PRIxBUSADDR, aa-aa_addr);
+ if (aa-aa_irq != -1)
+ aprint_normal( irq %d, aa-aa_irq);
+ }
return (UNCONF);
}
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.7 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.8
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.7 Tue Mar 10 18:03:17 2015
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Mar 17 07:25:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.7 2015/03/10 18:03:17 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.8 2015/03/17 07:25:07 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.7 2015/03/10 18:03:17 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.8 2015/03/17 07:25:07 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -176,11 +176,11 @@ ingenic_dwc2_attach(device_t parent, dev
delay(1);
- sc-sc_ih = evbmips_intr_establish(21, dwc2_intr, sc-sc_dwc2);
+ sc-sc_ih = evbmips_intr_establish(aa-aa_irq, dwc2_intr, sc-sc_dwc2);
if (sc-sc_ih == NULL) {
aprint_error_dev(self, failed to establish interrupt %d\n,
- 21);
+ aa-aa_irq);
goto fail;
}
Index: src/sys/arch/mips/ingenic/ingenic_ehci.c
diff -u src/sys/arch/mips/ingenic/ingenic_ehci.c:1.1 src/sys/arch/mips/ingenic/ingenic_ehci.c:1.2
--- src/sys/arch/mips/ingenic/ingenic_ehci.c:1.1 Sun Mar 8 17:14:27 2015
+++ src/sys/arch/mips/ingenic/ingenic_ehci.c Tue Mar 17 07:25:07 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_ehci.c,v 1.1 2015/03/08 17:14:27 macallan Exp $ */
+/* $NetBSD: ingenic_ehci.c,v 1.2 2015/03/17 07:25:07 macallan Exp $ */
/*-
*
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Mar 17 09:27:09 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dwctwo.c ingenic_ehci.c
ingenic_ohci.c
Log Message:
set root hub vendor IDs
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_ehci.c \
src/sys/arch/mips/ingenic/ingenic_ohci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.8 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.9
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.8 Tue Mar 17 07:25:07 2015
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Mar 17 09:27:09 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.8 2015/03/17 07:25:07 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.9 2015/03/17 09:27:09 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.8 2015/03/17 07:25:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.9 2015/03/17 09:27:09 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -47,9 +47,9 @@ __KERNEL_RCSID(0, $NetBSD: ingenic_dwct
#include dev/usb/usbdi.h
#include dev/usb/usbdivar.h
#include dev/usb/usb_mem.h
+#include dev/usb/usbdevs.h
#include dwc2/dwc2var.h
-
#include dwc2/dwc2.h
#include dwc2_core.h
@@ -202,6 +202,8 @@ ingenic_dwc2_deferred(device_t self)
struct ingenic_dwc2_softc *sc = device_private(self);
int error;
+ sc-sc_dwc2.sc_id_vendor = USB_VENDOR_INGENIC;
+ strlcpy(sc-sc_dwc2.sc_vendor, Ingenic, sizeof(sc-sc_dwc2.sc_vendor));
error = dwc2_init(sc-sc_dwc2);
if (error != 0) {
aprint_error_dev(self, couldn't initialize host, error=%d\n,
Index: src/sys/arch/mips/ingenic/ingenic_ehci.c
diff -u src/sys/arch/mips/ingenic/ingenic_ehci.c:1.2 src/sys/arch/mips/ingenic/ingenic_ehci.c:1.3
--- src/sys/arch/mips/ingenic/ingenic_ehci.c:1.2 Tue Mar 17 07:25:07 2015
+++ src/sys/arch/mips/ingenic/ingenic_ehci.c Tue Mar 17 09:27:09 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_ehci.c,v 1.2 2015/03/17 07:25:07 macallan Exp $ */
+/* $NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_ehci.c,v 1.2 2015/03/17 07:25:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_ehci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $);
#include sys/param.h
#include sys/systm.h
@@ -47,6 +47,8 @@ __KERNEL_RCSID(0, $NetBSD: ingenic_ehci
#include dev/usb/ehcireg.h
#include dev/usb/ehcivar.h
+#include dev/usb/usbdevs.h
+
#include opt_ingenic.h
#include ohci.h
@@ -131,6 +133,8 @@ ingenic_ehci_attach(device_t parent, dev
#else
sc-sc_ncomp = 0;
#endif
+ sc-sc_id_vendor = USB_VENDOR_INGENIC;
+ strlcpy(sc-sc_vendor, Ingenic, sizeof(sc-sc_vendor));
status = ehci_init(sc);
if (status != USBD_NORMAL_COMPLETION) {
Index: src/sys/arch/mips/ingenic/ingenic_ohci.c
diff -u src/sys/arch/mips/ingenic/ingenic_ohci.c:1.2 src/sys/arch/mips/ingenic/ingenic_ohci.c:1.3
--- src/sys/arch/mips/ingenic/ingenic_ohci.c:1.2 Tue Mar 17 07:25:07 2015
+++ src/sys/arch/mips/ingenic/ingenic_ohci.c Tue Mar 17 09:27:09 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_ohci.c,v 1.2 2015/03/17 07:25:07 macallan Exp $ */
+/* $NetBSD: ingenic_ohci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_ohci.c,v 1.2 2015/03/17 07:25:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_ohci.c,v 1.3 2015/03/17 09:27:09 macallan Exp $);
#include sys/param.h
#include sys/systm.h
@@ -43,6 +43,7 @@ __KERNEL_RCSID(0, $NetBSD: ingenic_ohci
#include dev/usb/usbdi.h
#include dev/usb/usbdivar.h
#include dev/usb/usb_mem.h
+#include dev/usb/usbdevs.h
#include dev/usb/ohcireg.h
#include dev/usb/ohcivar.h
@@ -110,9 +111,11 @@ ingenic_ohci_attach(device_t parent, dev
goto fail;
}
- /* we don't handle endianess in bus space */
sc-sc_endian = OHCI_LITTLE_ENDIAN;
+ sc-sc_id_vendor = USB_VENDOR_INGENIC;
+ strlcpy(sc-sc_vendor, Ingenic, sizeof(sc-sc_vendor));
+
status = ohci_init(sc);
if (status != USBD_NORMAL_COMPLETION) {
aprint_error_dev(self, init failed, error=%d\n, status);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Mar 17 09:26:31 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
always print the child devices' address, print irq if not -1 and a driver
is actually attaching
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.8 src/sys/arch/mips/ingenic/apbus.c:1.9
--- src/sys/arch/mips/ingenic/apbus.c:1.8 Tue Mar 17 07:25:07 2015
+++ src/sys/arch/mips/ingenic/apbus.c Tue Mar 17 09:26:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.8 2015/03/17 07:25:07 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.9 2015/03/17 09:26:31 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.8 2015/03/17 07:25:07 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.9 2015/03/17 09:26:31 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -170,11 +170,11 @@ apbus_print(void *aux, const char *pnp)
if (pnp) {
aprint_normal(%s at %s, aa-aa_name, pnp);
- if (aa-aa_addr != -1)
- aprint_normal( addr 0x% PRIxBUSADDR, aa-aa_addr);
- if (aa-aa_irq != -1)
- aprint_normal( irq %d, aa-aa_irq);
}
+ if (aa-aa_addr != -1)
+ aprint_normal( addr 0x% PRIxBUSADDR, aa-aa_addr);
+ if ((pnp == NULL) (aa-aa_irq != -1))
+ aprint_normal( irq %d, aa-aa_irq);
return (UNCONF);
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Mar 10 18:03:18 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_dwctwo.c Log Message: flash the LED to show we're doing something ( and as a side effect make sure the USB PHY is powered up ) To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/ingenic/ingenic_dwctwo.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.6 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.7 --- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.6 Mon Mar 9 13:23:57 2015 +++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Mar 10 18:03:17 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_dwctwo.c,v 1.6 2015/03/09 13:23:57 macallan Exp $ */ +/* $NetBSD: ingenic_dwctwo.c,v 1.7 2015/03/10 18:03:17 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.6 2015/03/09 13:23:57 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.7 2015/03/10 18:03:17 macallan Exp $); /* * adapted from bcm2835_dwctwo.c @@ -137,6 +137,10 @@ ingenic_dwc2_attach(device_t parent, dev aprint_naive(: USB controller\n); aprint_normal(: USB controller\n); + gpio_set(5, 15, 0); + delay(25); + gpio_set(5, 15, 1); + reg = readreg(JZ_USBPCR); reg |= PCR_VBUSVLDEXTSEL; reg |= PCR_VBUSVLDEXT;
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Mar 10 18:15:47 UTC 2015
Added Files:
src/sys/arch/mips/ingenic: ingenic_dme.c
Log Message:
support CI20's onboard Ethernet controller
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/ingenic_dme.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/mips/ingenic/ingenic_dme.c
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_dme.c:1.1
--- /dev/null Tue Mar 10 18:15:47 2015
+++ src/sys/arch/mips/ingenic/ingenic_dme.c Tue Mar 10 18:15:47 2015
@@ -0,0 +1,165 @@
+/* $NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2015 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__KERNEL_RCSID(0, $NetBSD: ingenic_dme.c,v 1.1 2015/03/10 18:15:47 macallan Exp $);
+
+#include sys/param.h
+#include sys/systm.h
+#include sys/device.h
+#include sys/mutex.h
+#include sys/bus.h
+#include sys/workqueue.h
+
+#include mips/ingenic/ingenic_var.h
+#include mips/ingenic/ingenic_regs.h
+
+#include net/if.h
+#include net/if_ether.h
+#include net/if_media.h
+
+#include dev/ic/dm9000var.h
+#include dev/ic/dm9000reg.h
+
+#include opt_ingenic.h
+
+static int ingenic_dme_match(device_t, struct cfdata *, void *);
+static void ingenic_dme_attach(device_t, device_t, void *);
+static int ingenic_dme_intr(void *);
+
+CFATTACH_DECL_NEW(ingenic_dme, sizeof(struct dme_softc),
+ingenic_dme_match, ingenic_dme_attach, NULL, NULL);
+
+#define GPIO_DME_INT 19
+#define GPIO_DME_INT_MASK (1 GPIO_DME_INT)
+
+/* ARGSUSED */
+static int
+ingenic_dme_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (strcmp(aa-aa_name, dme) != 0)
+ return 0;
+
+ return 1;
+}
+
+/* ARGSUSED */
+static void
+ingenic_dme_attach(device_t parent, device_t self, void *aux)
+{
+ struct dme_softc *sc = device_private(self);
+ struct apbus_attach_args *aa = aux;
+ void *ih;
+ static uint8_t enaddr[ETHER_ADDR_LEN];
+ int error;
+
+ sc-sc_dev = self;
+
+ sc-sc_iot = aa-aa_bst;
+ sc-dme_io = JZ_DME_IO;
+ sc-dme_data = JZ_DME_DATA;
+ sc-sc_phy_initialized = 0;
+
+ if (aa-aa_addr == 0)
+ aa-aa_addr = JZ_DME_BASE;
+
+ error = bus_space_map(aa-aa_bst, aa-aa_addr, 4, 0, sc-sc_ioh);
+ if (error) {
+ aprint_error_dev(self,
+ can't map registers for %s: %d\n, aa-aa_name, error);
+ return;
+ }
+
+ aprint_naive(: DM9000 Ethernet controller\n);
+ aprint_normal(: DM9000 Ethernet controller\n);
+
+
+ /* make sure the chip is powered up and not in reset */
+ gpio_as_output(1, 25);
+ gpio_set(1, 25, 1);
+ gpio_as_output(5, 12);
+ gpio_set(5, 12, 1);
+
+ /* setup pins to talk to the chip */
+ gpio_as_dev0(1, 1);
+ gpio_as_dev0(0, 0);
+ gpio_as_dev0(0, 1);
+ gpio_as_dev0(0, 2);
+ gpio_as_dev0(0, 3);
+ gpio_as_dev0(0, 4);
+ gpio_as_dev0(0, 5);
+ gpio_as_dev0(0, 6);
+ gpio_as_dev0(0, 7);
+
+ gpio_as_dev0(0, 16);
+ gpio_as_dev0(0, 17);
+ gpio_as_dev0(0, 26);
+
+ /* DM9000 interrupt is on GPIO E pin 19 */
+ gpio_as_intr_level(4, GPIO_DME_INT);
+ ih = evbmips_intr_establish(13, ingenic_dme_intr, sc);
+
+ if (ih == NULL) {
+ aprint_error_dev(self, failed to establish interrupt %d\n,
+ 13);
+ goto fail;
+ }
+
+ /*
+ * XXX grab MAC address set by uboot
+ * I'm not sure uboot will program the MAC address into the chip when
+ * not netbooting, so this needs to go away
+ */
+ dme_read_c(sc, DM9000_PAB0, enaddr, 6);
+ dme_attach(sc, enaddr);
+ return;
+fail:
+ if (ih) {
+ evbmips_intr_disestablish(ih);
+ }
+ bus_space_unmap(sc-sc_iot, sc-sc_ioh, 4);
+}
+
+static
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Mon Mar 9 13:22:37 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: moar registers To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.7 src/sys/arch/mips/ingenic/ingenic_regs.h:1.8 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.7 Sat Mar 7 15:36:16 2015 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Mon Mar 9 13:22:37 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.7 2015/03/07 15:36:16 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.8 2015/03/09 13:22:37 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -221,7 +221,7 @@ MFC0(uint32_t r, uint32_t s) #define PCR_TXPREEMPH 0x0080 /* HS transm. pre-emphasis */ #define PCR_TXHSXVTUNE1 0x0060 /* dp/dm voltage adj. */ #define PCR_TXVREFTUNE1 0x0017 /* HS DC voltage adj. */ - #define PCR_TXRISETUNE1 0x0001 /* risa/fall wave adj. */ + #define PCR_TXRISETUNE1 0x0001 /* rise/fall wave adj. */ #define JZ_UHCCDR 0x106c /* UHC Clock Divider Register */ #define JZ_SPCR0 0x10b8 /* SRAM Power Control Registers */ @@ -255,5 +255,14 @@ MFC0(uint32_t r, uint32_t s) #define DMMAP_BASE 0xff00 /* base PADDR of memory chunk */ #define DMMAP_MASK 0x00ff /* mask which bits of PADDR are * constant */ +/* USB controllers */ +#define JZ_EHCI_BASE 0x1349 +#define JZ_OHCI_BASE 0x134a +#define JZ_DWC2_BASE 0x1350 + +/* Ethernet */ +#define JZ_DME_BASE 0x1600 +#define JZ_DME_IO JZ_DME_BASE +#define JZ_DME_ADDR (JZ_DME_BASE + 2) #endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Mon Mar 9 13:24:21 UTC 2015
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
moar devices
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.6 src/sys/arch/mips/ingenic/apbus.c:1.7
--- src/sys/arch/mips/ingenic/apbus.c:1.6 Sat Dec 27 17:22:15 2014
+++ src/sys/arch/mips/ingenic/apbus.c Mon Mar 9 13:24:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.6 2014/12/27 17:22:15 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.7 2015/03/09 13:24:21 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.6 2014/12/27 17:22:15 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.7 2015/03/09 13:24:21 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -64,6 +64,9 @@ struct mips_bus_dma_tag apbus_dmat = {
static const char *apbus_devs[] = {
dwctwo,
+ ohci,
+ ehci,
+ dme,
jzgpio,
jzfb,
NULL
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Mon Mar 9 13:23:57 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_dwctwo.c Log Message: magic number reduction To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/ingenic_dwctwo.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.5 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.6 --- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.5 Sat Dec 27 17:22:15 2014 +++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Mon Mar 9 13:23:57 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_dwctwo.c,v 1.5 2014/12/27 17:22:15 macallan Exp $ */ +/* $NetBSD: ingenic_dwctwo.c,v 1.6 2015/03/09 13:23:57 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.5 2014/12/27 17:22:15 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.6 2015/03/09 13:23:57 macallan Exp $); /* * adapted from bcm2835_dwctwo.c @@ -124,7 +124,7 @@ ingenic_dwc2_attach(device_t parent, dev sc-sc_dwc2.sc_params = ingenic_dwc2_params; if (aa-aa_addr == 0) - aa-aa_addr = 0x1350; + aa-aa_addr = JZ_DWC2_BASE; error = bus_space_map(aa-aa_bst, aa-aa_addr, 0x2, 0, sc-sc_dwc2.sc_ioh);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Sat Mar 7 15:35:33 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_com.c Log Message: fix uart parameters, now speed setting actually works To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_com.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_com.c diff -u src/sys/arch/mips/ingenic/ingenic_com.c:1.3 src/sys/arch/mips/ingenic/ingenic_com.c:1.4 --- src/sys/arch/mips/ingenic/ingenic_com.c:1.3 Tue Dec 23 15:12:23 2014 +++ src/sys/arch/mips/ingenic/ingenic_com.c Sat Mar 7 15:35:33 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_com.c,v 1.3 2014/12/23 15:12:23 macallan Exp $ */ +/* $NetBSD: ingenic_com.c,v 1.4 2015/03/07 15:35:33 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.3 2014/12/23 15:12:23 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.4 2015/03/07 15:35:33 macallan Exp $); #include sys/param.h #include sys/systm.h @@ -56,7 +56,7 @@ void ingenic_puts(const char *); void ingenic_putchar(char); #ifndef CONMODE -# define CONMODE ((TTYDEF_CFLAG ~(CSIZE | PARENB)) | CS8) +# define CONMODE ((TTYDEF_CFLAG ~(CSIZE | CSTOPB | PARENB)) | CS8) #endif @@ -163,7 +163,7 @@ ingenic_com_cnattach(void) * so we just leave alone whatever u-boot set up * my uplcom is too tolerant to show any difference */ - comcnattach1(regs, -1, 600, COM_TYPE_INGENIC, CONMODE); + comcnattach1(regs, 115200, 4800, COM_TYPE_INGENIC, CONMODE); } static int @@ -184,7 +184,7 @@ ingenic_com_attach(device_t parent, devi struct com_softc *sc = isc-sc_com; sc-sc_dev = self; - sc-sc_frequency = 1200; + sc-sc_frequency = 4800; sc-sc_type = COM_TYPE_INGENIC; memset(sc-sc_regs, 0, sizeof(sc-sc_regs)); COM_INIT_REGS(sc-sc_regs, ingenic_com_mbst, regh, 0);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Sat Mar 7 15:36:16 UTC 2015 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: add memory controller registers To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.6 src/sys/arch/mips/ingenic/ingenic_regs.h:1.7 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.6 Thu Dec 25 05:10:00 2014 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Mar 7 15:36:16 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.6 2014/12/25 05:10:00 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.7 2015/03/07 15:36:16 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -249,4 +249,11 @@ MFC0(uint32_t r, uint32_t s) #define JZ_DMR1 0x10001044 /* mask for PDMA */ #define JZ_DPR1 0x10001048 /* pending for PDMA */ +/* memory controller */ +#define JZ_DMMAP0 0x13010024 +#define JZ_DMMAP1 0x13010028 + #define DMMAP_BASE 0xff00 /* base PADDR of memory chunk */ + #define DMMAP_MASK 0x00ff /* mask which bits of PADDR are + * constant */ + #endif /* INGENIC_REGS_H */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Sat Dec 27 17:22:16 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_dwctwo.c
Log Message:
restrict DMA buffers to the lower 256MB - now dwc2 DMA works
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.5 src/sys/arch/mips/ingenic/apbus.c:1.6
--- src/sys/arch/mips/ingenic/apbus.c:1.5 Thu Dec 25 05:10:50 2014
+++ src/sys/arch/mips/ingenic/apbus.c Sat Dec 27 17:22:15 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.5 2014/12/25 05:10:50 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.6 2014/12/27 17:22:15 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.5 2014/12/25 05:10:50 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.6 2014/12/27 17:22:15 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -56,6 +56,7 @@ static struct mips_bus_space apbus_mbst;
bus_space_tag_t apbus_memt = NULL;
struct mips_bus_dma_tag apbus_dmat = {
+ ._bounce_alloc_hi = 0x1000,
._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.4 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.5
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.4 Thu Dec 25 05:13:49 2014
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Sat Dec 27 17:22:15 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.4 2014/12/25 05:13:49 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.5 2014/12/27 17:22:15 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.4 2014/12/25 05:13:49 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.5 2014/12/27 17:22:15 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -64,7 +64,7 @@ struct ingenic_dwc2_softc {
static struct dwc2_core_params ingenic_dwc2_params = {
.otg_cap = -1, /* HNP/SRP capable */
.otg_ver = -1, /* 1.3 */
- .dma_enable = 0, /* for now */
+ .dma_enable = 1,
.dma_desc_enable = 0,
.speed= -1, /* High Speed */
.enable_dynamic_fifo = -1,
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Thu Dec 25 05:10:00 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: even more registers To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.5 src/sys/arch/mips/ingenic/ingenic_regs.h:1.6 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.5 Tue Dec 23 18:48:52 2014 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Thu Dec 25 05:10:00 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.5 2014/12/23 18:48:52 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.6 2014/12/25 05:10:00 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -198,7 +198,7 @@ MFC0(uint32_t r, uint32_t s) #define PCR_TXPREEMPHTUNE 0x0040 #define PCR_TXHSXVTUNE 0x0030 #define PCR_TXVREFTUNE 0x000f - +#define JZ_USBRDT 0x1040 /* Reset Detect Timer Register */ #define JZ_USBPCR1 0x1048 #define PCR_SYNOPSYS 0x1000 /* Mentor mode otherwise */ #define PCR_REFCLK_CORE 0x0c00 @@ -222,7 +222,8 @@ MFC0(uint32_t r, uint32_t s) #define PCR_TXHSXVTUNE1 0x0060 /* dp/dm voltage adj. */ #define PCR_TXVREFTUNE1 0x0017 /* HS DC voltage adj. */ #define PCR_TXRISETUNE1 0x0001 /* risa/fall wave adj. */ - + +#define JZ_UHCCDR 0x106c /* UHC Clock Divider Register */ #define JZ_SPCR0 0x10b8 /* SRAM Power Control Registers */ #define JZ_SPCR1 0x10bc #define JZ_SRBC 0x10c4 /* Soft Reset Bus Control */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Thu Dec 25 05:10:50 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
un-gate yet another clock
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.4 src/sys/arch/mips/ingenic/apbus.c:1.5
--- src/sys/arch/mips/ingenic/apbus.c:1.4 Tue Dec 23 18:48:52 2014
+++ src/sys/arch/mips/ingenic/apbus.c Thu Dec 25 05:10:50 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.5 2014/12/25 05:10:50 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.5 2014/12/25 05:10:50 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -109,6 +109,7 @@ apbus_attach(device_t parent, device_t s
/* enable USB clocks */
reg = readreg(JZ_CLKGR1);
reg = ~(1 8); /* OTG1 clock */
+ reg = ~(1 11); /* AHB_MON clock */
writereg(JZ_CLKGR1, reg);
reg = readreg(JZ_CLKGR0);
@@ -127,6 +128,7 @@ apbus_attach(device_t parent, device_t s
printf(JZ_SPCR1 %08x\n, readreg(JZ_SPCR1));
printf(JZ_SRBC %08x\n, readreg(JZ_SRBC));
printf(JZ_OPCR %08x\n, readreg(JZ_OPCR));
+ printf(JZ_UHCCDR %08x\n, readreg(JZ_UHCCDR));
#endif
for (const char **adv = apbus_devs; *adv != NULL; adv++) {
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Thu Dec 25 05:13:50 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dwctwo.c
Log Message:
- use the same parameter block as the linux driver, only with DMA disabled
- reset the chip before handing it to dwc2/
now it actually detects some devices
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.3 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.4
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.3 Tue Dec 23 18:48:52 2014
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Thu Dec 25 05:13:49 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.4 2014/12/25 05:13:49 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.4 2014/12/25 05:13:49 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -53,6 +53,8 @@ __KERNEL_RCSID(0, $NetBSD: ingenic_dwct
#include dwc2/dwc2.h
#include dwc2_core.h
+#include opt_ingenic.h
+
struct ingenic_dwc2_softc {
struct dwc2_softc sc_dwc2;
@@ -60,31 +62,31 @@ struct ingenic_dwc2_softc {
};
static struct dwc2_core_params ingenic_dwc2_params = {
- .otg_cap = 0, /* HNP/SRP capable */
- .otg_ver = 0, /* 1.3 */
- .dma_enable = 1,
+ .otg_cap = -1, /* HNP/SRP capable */
+ .otg_ver = -1, /* 1.3 */
+ .dma_enable = 0, /* for now */
.dma_desc_enable = 0,
- .speed= 0, /* High Speed */
- .enable_dynamic_fifo = 1,
- .en_multiple_tx_fifo = 1,
- .host_rx_fifo_size = 774, /* 774 DWORDs */
- .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
- .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
- .max_transfer_size = 65535,
- .max_packet_count = 511,
- .host_channels = 8,
- .phy_type = 1, /* UTMI */
- .phy_utmi_width = 8, /* 8 bits */
- .phy_ulpi_ddr = 0, /* Single */
- .phy_ulpi_ext_vbus = 0,
- .i2c_enable = 0,
- .ulpi_fs_ls = 0,
- .host_support_fs_ls_low_power = 0,
- .host_ls_low_power_phy_clk = 0, /* 48 MHz */
- .ts_dline = 0,
- .reload_ctl = 0,
- .ahbcfg= 0x10,
- .uframe_sched = 1,
+ .speed= -1, /* High Speed */
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 1024, /* 1024 DWORDs */
+ .host_nperio_tx_fifo_size = 1024, /* 1024 DWORDs */
+ .host_perio_tx_fifo_size = 1024, /* 1024 DWORDs */
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1, /* UTMI */
+ .phy_utmi_width = -1, /* 16 bits */
+ .phy_ulpi_ddr = -1, /* Single */
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1, /* 48 MHz */
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg= -1,
+ .uframe_sched = 0,
};
static int ingenic_dwc2_match(device_t, struct cfdata *, void *);
@@ -152,13 +154,24 @@ ingenic_dwc2_attach(device_t parent, dev
reg = ~PCR_CLK_M;
reg |= PCR_CLK_48;
reg |= PCR_WORD_I_F0;
+ reg |= PCR_WORD_I_F1;
writereg(JZ_USBPCR1, reg);
#ifdef INGENIC_DEBUG
printf(JZ_USBPCR1 %08x\n, reg);
+ printf(JZ_USBRDT %08x\n, readreg(JZ_USBRDT));
#endif
delay(1);
+ reg = readreg(JZ_USBPCR);
+ reg |= PCR_POR;
+ writereg(JZ_USBPCR, reg);
+ delay(1000);
+ reg = ~PCR_POR;
+ writereg(JZ_USBPCR, reg);
+
+ delay(1);
+
sc-sc_ih = evbmips_intr_establish(21, dwc2_intr, sc-sc_dwc2);
if (sc-sc_ih == NULL) {
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Dec 23 15:03:56 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: moar registers To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.2 src/sys/arch/mips/ingenic/ingenic_regs.h:1.3 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.2 Sat Dec 6 14:33:34 2014 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Dec 23 15:03:56 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.2 2014/12/06 14:33:34 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.3 2014/12/23 15:03:56 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -161,6 +161,58 @@ MFC0(uint32_t r, uint32_t s) #define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ +/* power management */ +#define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */ +#define JZ_OPCR 0x1024 /* Oscillator Power Control Reg. */ +#define JZ_CLKGR1 0x1028 /* CLocK Gating Registers */ +#define JZ_USBPCR 0x103c + #define USB_MODE 0x8000 /* 1 - otg */ + #define AVLD_REG 0x4000 + #define IDPULLUP_MASK 0x3000 + #define INCR_MASK 0x0800 + #define TCRISETUNE 0x0400 + #define COMMONONN 0x0200 + #define VBUSVLDEXT 0x0100 + #define VBUSVLDEXTSEL 0x0080 + #define POR 0x0040 + #define SIDDQ 0x0020 + #define OTG_DISABLE 0x0010 + #define COMPDISTUNE_M 0x000e + #define OTGTUNE 0x0001c000 + #define SQRXTUNE 0x3800 + #define TXFSLSTUNE 0x0780 + #define TXPREEMPHTUNE 0x0040 + #define TXHSXVTUNE 0x0030 + #define TXVREFTUNE 0x000f + +#define JZ_USBPCR1 0x1048 + #define PCR_SYNOPSYS 0x1000 /* Mentor mode otherwise */ + #define PCR_REFCLK_CORE 0x0c00 + #define PCR_REFCLK_XO25 0x0400 + #define PCR_REFCLK_CO 0x + #define PCR_CLK_M 0x0300 /* clock */ + #define PCR_CLK_192 0x0300 /* 19.2MHz */ + #define PCR_CLK_48 0x0200 /* 48MHz */ + #define PCR_CLK_24 0x0100 /* 24MHz */ + #define PCR_CLK_12 0x /* 12MHz */ + #define PCR_DMPD1 0x0080 /* pull down D- on port 1 */ + #define PCR_DPPD1 0x0040 /* pull down D+ on port 1 */ + #define PCR_PORT0_RST 0x0020 /* port 0 reset */ + #define PCR_PORT1_RST 0x0010 /* port 1 reset */ + #define PCR_WORD_I_F0 0x0008 /* 1: 16bit/30M, 8/60 otherw. */ + #define PCR_WORD_I_F1 0x0004 /* same for port 1 */ + #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ + #define PCR_SQRXTUNE1 0x7000 /* squelch threshold */ + #define PCR_TXFSLSTUNE1 0x0f00 /* FS/LS impedance adj. */ + #define PCR_TXPREEMPH 0x0080 /* HS transm. pre-emphasis */ + #define PCR_TXHSXVTUNE1 0x0060 /* dp/dm voltage adj. */ + #define PCR_TXVREFTUNE1 0x0017 /* HS DC voltage adj. */ + #define PCR_TXRISETUNE1 0x0001 /* risa/fall wave adj. */ + +#define JZ_SPCR0 0x10b8 /* SRAM Power Control Registers */ +#define JZ_SPCR1 0x10bc +#define JZ_SRBC 0x10c4 /* Soft Reset Bus Control */ + /* interrupt controller */ #define JZ_ICSR0 0x10001000 /* raw IRQ line status */ #define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Dec 23 15:11:05 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
use defflag-ed debug options
enable USB clocks before attaching dwctwo
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.1 src/sys/arch/mips/ingenic/apbus.c:1.2
--- src/sys/arch/mips/ingenic/apbus.c:1.1 Sat Dec 6 14:34:56 2014
+++ src/sys/arch/mips/ingenic/apbus.c Tue Dec 23 15:11:05 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.1 2014/12/06 14:34:56 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.2 2014/12/23 15:11:05 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.1 2014/12/06 14:34:56 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.2 2014/12/23 15:11:05 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -43,6 +43,8 @@ __KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.
#include mips/ingenic/ingenic_var.h
#include mips/ingenic/ingenic_regs.h
+#include opt_ingenic.h
+
static int apbus_match(device_t, cfdata_t, void *);
static void apbus_attach(device_t, device_t, void *);
static int apbus_print(void *, const char *);
@@ -91,15 +93,34 @@ apbus_match(device_t parent, cfdata_t ma
void
apbus_attach(device_t parent, device_t self, void *aux)
{
+ uint32_t reg;
aprint_normal(\n);
/* should have been called early on */
apbus_init();
-printf(core ctrl: %08x\n, MFC0(12, 2));
-printf(core status: %08x\n, MFC0(12, 3));
-printf(REIM: %08x\n, MFC0(12, 4));
-printf(ID: %08x\n, MFC0(15, 1));
+#ifdef INGENIC_DEBUG
+ printf(core ctrl: %08x\n, MFC0(12, 2));
+ printf(core status: %08x\n, MFC0(12, 3));
+ printf(REIM: %08x\n, MFC0(12, 4));
+ printf(ID: %08x\n, MFC0(15, 1));
+#endif
+
+ reg = readreg(JZ_CLKGR1);
+ reg = ~(1 8); /* OTG1 clock */
+ writereg(JZ_CLKGR1, reg);
+
+ reg = readreg(JZ_CLKGR0);
+ reg = ~(1 24); /* UHC clock */
+ writereg(JZ_CLKGR0, reg);
+
+#ifdef INGENIC_DEBUG
+ printf(JZ_CLKGR0 %08x\n, readreg(JZ_CLKGR0));
+ printf(JZ_CLKGR1 %08x\n, readreg(JZ_CLKGR1));
+ printf(JZ_SPCR0 %08x\n, readreg(JZ_SPCR0));
+ printf(JZ_SPCR1 %08x\n, readreg(JZ_SPCR1));
+ printf(JZ_SRBC %08x\n, readreg(JZ_SRBC));
+#endif
for (const char **adv = apbus_devs; *adv != NULL; adv++) {
struct apbus_attach_args aa;
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Dec 23 15:12:23 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: ingenic_com.c Log Message: establish interrupt To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_com.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_com.c diff -u src/sys/arch/mips/ingenic/ingenic_com.c:1.2 src/sys/arch/mips/ingenic/ingenic_com.c:1.3 --- src/sys/arch/mips/ingenic/ingenic_com.c:1.2 Sat Dec 6 14:33:18 2014 +++ src/sys/arch/mips/ingenic/ingenic_com.c Tue Dec 23 15:12:23 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_com.c,v 1.2 2014/12/06 14:33:18 macallan Exp $ */ +/* $NetBSD: ingenic_com.c,v 1.3 2014/12/23 15:12:23 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.2 2014/12/06 14:33:18 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.3 2014/12/23 15:12:23 macallan Exp $); #include sys/param.h #include sys/systm.h @@ -190,7 +190,7 @@ ingenic_com_attach(device_t parent, devi COM_INIT_REGS(sc-sc_regs, ingenic_com_mbst, regh, 0); com_attach_subr(sc); printf(\n); - /* interrupt */ + evbmips_intr_establish(51, comintr, sc); } #define CHIP ingenic_com
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Dec 23 15:13:30 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: ingenic_dwctwo.c
Log Message:
establish interrupt
do some PHY setup, now the hardware actually responds
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.1 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.2
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.1 Sat Dec 6 14:35:47 2014
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Dec 23 15:13:30 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.1 2014/12/06 14:35:47 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.1 2014/12/06 14:35:47 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $);
/*
* adapted from bcm2835_dwctwo.c
@@ -112,6 +112,7 @@ ingenic_dwc2_attach(device_t parent, dev
{
struct ingenic_dwc2_softc *sc = device_private(self);
struct apbus_attach_args *aa = aux;
+ uint32_t reg;
int error;
sc-sc_dwc2.sc_dev = self;
@@ -134,27 +135,41 @@ ingenic_dwc2_attach(device_t parent, dev
aprint_naive(: USB controller\n);
aprint_normal(: USB controller\n);
-#if notyet
- sc-sc_ih = bcm2835_intr_establish(aaa-aaa_intr, IPL_SCHED,
- dwc2_intr, sc-sc_dwc2);
+ reg = readreg(JZ_USBPCR);
+ reg |= VBUSVLDEXTSEL;
+ reg |= VBUSVLDEXT;
+ reg |= USB_MODE;
+ reg |= COMMONONN;
+ reg = ~OTG_DISABLE;
+ writereg(JZ_USBPCR, reg);
+
+ reg = readreg(JZ_USBPCR1);
+ reg |= PCR_SYNOPSYS;
+ reg |= PCR_REFCLK_CORE;
+ reg = ~PCR_CLK_M;
+ reg |= PCR_CLK_48;
+ reg |= PCR_WORD_I_F0;
+ writereg(JZ_USBPCR1, reg);
+
+ delay(1);
+
+ sc-sc_ih = evbmips_intr_establish(21, dwc2_intr, sc-sc_dwc2);
if (sc-sc_ih == NULL) {
aprint_error_dev(self, failed to establish interrupt %d\n,
- aaa-aaa_intr);
+ 21);
goto fail;
}
-#endif
+
config_defer(self, ingenic_dwc2_deferred);
return;
-#if notyet
fail:
if (sc-sc_ih) {
- intr_disestablish(sc-sc_ih);
+ evbmips_intr_disestablish(sc-sc_ih);
sc-sc_ih = NULL;
}
-#endif
bus_space_unmap(sc-sc_dwc2.sc_iot, sc-sc_dwc2.sc_ioh, 0x2);
}
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Dec 23 16:15:05 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: ingenic_regs.h Log Message: yet more registers To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.3 src/sys/arch/mips/ingenic/ingenic_regs.h:1.4 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.3 Tue Dec 23 15:03:56 2014 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Dec 23 16:15:05 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.3 2014/12/23 15:03:56 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.4 2014/12/23 16:15:05 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -164,6 +164,20 @@ MFC0(uint32_t r, uint32_t s) /* power management */ #define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */ #define JZ_OPCR 0x1024 /* Oscillator Power Control Reg. */ + #define IDLE_DIS 0x8000 /* don't stop CPU clk on idle */ + #define GPU_CLK_STOP 0x4000 + #define L2CM_M 0x0c00 + #define L2CM_ON 0x /* L2 stays on in sleep */ + #define L2CM_RET 0x0400 /* L2 retention mode in sleep */ + #define L2CM_OFF 0x0800 /* L2 powers down in sleep */ + #define SPENDN0 0x0080 /* OTG port forced down */ + #define SPENDN1 0x0040 /* UHC port forced down */ + #define BUS_MODE 0x0020 /* 1 - bursts */ + #define O1SE 0x0010 /* EXTCLK on in sleep */ + #define PD 0x0008 /* P0 down in sleep */ + #define ERCS 0x0004 /* 1 RTCCLK, 0 EXTCLK/512 */ + #define CPU_MODE 0x0002 /* 1 access 'accelerated' */ + #define OSE 0x0001 /* disable EXTCLK */ #define JZ_CLKGR1 0x1028 /* CLocK Gating Registers */ #define JZ_USBPCR 0x103c #define USB_MODE 0x8000 /* 1 - otg */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Tue Dec 23 16:16:03 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: apbus.c
Log Message:
wake up the USB ports before attaching dwctwo
now it finds a root hub
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/apbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.2 src/sys/arch/mips/ingenic/apbus.c:1.3
--- src/sys/arch/mips/ingenic/apbus.c:1.2 Tue Dec 23 15:11:05 2014
+++ src/sys/arch/mips/ingenic/apbus.c Tue Dec 23 16:16:03 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.2 2014/12/23 15:11:05 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.2 2014/12/23 15:11:05 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $);
#include locators.h
#define _MIPS_BUS_DMA_PRIVATE
@@ -106,6 +106,7 @@ apbus_attach(device_t parent, device_t s
printf(ID: %08x\n, MFC0(15, 1));
#endif
+ /* enable USB clocks */
reg = readreg(JZ_CLKGR1);
reg = ~(1 8); /* OTG1 clock */
writereg(JZ_CLKGR1, reg);
@@ -114,12 +115,18 @@ apbus_attach(device_t parent, device_t s
reg = ~(1 24); /* UHC clock */
writereg(JZ_CLKGR0, reg);
+ /* wake up the USB part */
+ reg = readreg(JZ_OPCR);
+ reg |= SPENDN0 | SPENDN1;
+ writereg(JZ_OPCR, reg);
+
#ifdef INGENIC_DEBUG
printf(JZ_CLKGR0 %08x\n, readreg(JZ_CLKGR0));
printf(JZ_CLKGR1 %08x\n, readreg(JZ_CLKGR1));
printf(JZ_SPCR0 %08x\n, readreg(JZ_SPCR0));
printf(JZ_SPCR1 %08x\n, readreg(JZ_SPCR1));
printf(JZ_SRBC %08x\n, readreg(JZ_SRBC));
+ printf(JZ_OPCR %08x\n, readreg(JZ_OPCR));
#endif
for (const char **adv = apbus_devs; *adv != NULL; adv++) {
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Tue Dec 23 18:48:52 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: apbus.c ingenic_dwctwo.c ingenic_regs.h Log Message: appease nick To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/apbus.c cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_dwctwo.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ingenic/ingenic_regs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/apbus.c diff -u src/sys/arch/mips/ingenic/apbus.c:1.3 src/sys/arch/mips/ingenic/apbus.c:1.4 --- src/sys/arch/mips/ingenic/apbus.c:1.3 Tue Dec 23 16:16:03 2014 +++ src/sys/arch/mips/ingenic/apbus.c Tue Dec 23 18:48:52 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $ */ +/* $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -29,7 +29,7 @@ /* catch-all for on-chip peripherals */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $); #include locators.h #define _MIPS_BUS_DMA_PRIVATE @@ -117,7 +117,7 @@ apbus_attach(device_t parent, device_t s /* wake up the USB part */ reg = readreg(JZ_OPCR); - reg |= SPENDN0 | SPENDN1; + reg |= OPCR_SPENDN0 | OPCR_SPENDN1; writereg(JZ_OPCR, reg); #ifdef INGENIC_DEBUG Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.2 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.3 --- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.2 Tue Dec 23 15:13:30 2014 +++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Dec 23 18:48:52 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $ */ +/* $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $); /* * adapted from bcm2835_dwctwo.c @@ -136,12 +136,15 @@ ingenic_dwc2_attach(device_t parent, dev aprint_normal(: USB controller\n); reg = readreg(JZ_USBPCR); - reg |= VBUSVLDEXTSEL; - reg |= VBUSVLDEXT; - reg |= USB_MODE; - reg |= COMMONONN; - reg = ~OTG_DISABLE; + reg |= PCR_VBUSVLDEXTSEL; + reg |= PCR_VBUSVLDEXT; + reg |= PCR_USB_MODE; + reg |= PCR_COMMONONN; + reg = ~PCR_OTG_DISABLE; writereg(JZ_USBPCR, reg); +#ifdef INGENIC_DEBUG + printf(JZ_USBPCR %08x\n, reg); +#endif reg = readreg(JZ_USBPCR1); reg |= PCR_SYNOPSYS; @@ -150,6 +153,9 @@ ingenic_dwc2_attach(device_t parent, dev reg |= PCR_CLK_48; reg |= PCR_WORD_I_F0; writereg(JZ_USBPCR1, reg); +#ifdef INGENIC_DEBUG + printf(JZ_USBPCR1 %08x\n, reg); +#endif delay(1); Index: src/sys/arch/mips/ingenic/ingenic_regs.h diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.4 src/sys/arch/mips/ingenic/ingenic_regs.h:1.5 --- src/sys/arch/mips/ingenic/ingenic_regs.h:1.4 Tue Dec 23 16:15:05 2014 +++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Dec 23 18:48:52 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_regs.h,v 1.4 2014/12/23 16:15:05 macallan Exp $ */ +/* $NetBSD: ingenic_regs.h,v 1.5 2014/12/23 18:48:52 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -164,41 +164,41 @@ MFC0(uint32_t r, uint32_t s) /* power management */ #define JZ_CLKGR0 0x1020 /* CLocK Gating Registers */ #define JZ_OPCR 0x1024 /* Oscillator Power Control Reg. */ - #define IDLE_DIS 0x8000 /* don't stop CPU clk on idle */ - #define GPU_CLK_STOP 0x4000 - #define L2CM_M 0x0c00 - #define L2CM_ON 0x /* L2 stays on in sleep */ - #define L2CM_RET 0x0400 /* L2 retention mode in sleep */ - #define L2CM_OFF 0x0800 /* L2 powers down in sleep */ - #define SPENDN0 0x0080 /* OTG port forced down */ - #define SPENDN1 0x0040 /* UHC port forced down */ - #define BUS_MODE 0x0020 /* 1 - bursts */ - #define O1SE 0x0010 /* EXTCLK on in sleep */ - #define PD 0x0008 /* P0 down in sleep */ - #define ERCS 0x0004 /* 1 RTCCLK, 0 EXTCLK/512 */ - #define CPU_MODE 0x0002 /* 1 access 'accelerated' */ - #define OSE 0x0001 /* disable EXTCLK */ + #define OPCR_IDLE_DIS 0x8000 /* don't stop CPU clk on idle */ + #define OPCR_GPU_CLK_ST 0x4000 /* stop GPU clock */ + #define OPCR_L2CM_M 0x0c00 + #define OPCR_L2CM_ON 0x /* L2 stays on in sleep */ + #define OPCR_L2CM_RET 0x0400 /* L2 retention mode in sleep */ + #define OPCR_L2CM_OFF 0x0800 /* L2 powers down in sleep */ + #define OPCR_SPENDN0 0x0080 /* OTG port forced down */ + #define OPCR_SPENDN1 0x0040 /* UHC port forced down */ + #define OPCR_BUS_MODE 0x0020 /* 1 - bursts */ +
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Sat Dec 6 14:33:34 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
moar registers!
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.1 src/sys/arch/mips/ingenic/ingenic_regs.h:1.2
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.1 Sat Nov 22 15:17:01 2014
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Dec 6 14:33:34 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.1 2014/11/22 15:17:01 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.2 2014/12/06 14:33:34 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -46,7 +46,7 @@
#define JZ_WDOG_TCSR 0x1000200c
#define TCSR_PCK_EN 0x01 /* PCLK */
#define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */
- #define TCSR_EXT_EN 0x04 /* EXTCLK - 12MHz? */
+ #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */
#define TCSR_PRESCALE_M 0x38
#define TCSR_DIV_1 0x00
#define TCSR_DIV_4 0x08
@@ -63,11 +63,33 @@
#define TESR_TCST2 0x0004 /* enable counter 2 */
#define TESR_TCST3 0x0008 /* enable counter 3 */
#define TESR_TCST4 0x0010 /* enable counter 4 */
- #define TESR_TCST5 0x0014 /* enable counter 5 */
- #define TESR_TCST6 0x0018 /* enable counter 6 */
- #define TESR_TCST7 0x001c /* enable counter 7 */
+ #define TESR_TCST5 0x0020 /* enable counter 5 */
+ #define TESR_TCST6 0x0040 /* enable counter 6 */
+ #define TESR_TCST7 0x0080 /* enable counter 7 */
#define TESR_OST 0x8000 /* enable OST */
#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */
+#define JZ_TC_TFR 0x10002020
+ #define TFR_FFLAG0 0x0001 /* channel 0 */
+ #define TFR_FFLAG1 0x0002 /* channel 1 */
+ #define TFR_FFLAG2 0x0004 /* channel 2 */
+ #define TFR_FFLAG3 0x0008 /* channel 3 */
+ #define TFR_FFLAG4 0x0010 /* channel 4 */
+ #define TFR_FFLAG5 0x0020 /* channel 5 */
+ #define TFR_FFLAG6 0x0040 /* channel 6 */
+ #define TFR_FFLAG7 0x0080 /* channel 7 */
+ #define TFR_OSTFLAG 0x8000 /* OS timer */
+#define JZ_TC_TFSR 0x10002024 /* timer flag set */
+#define JZ_TC_TFCR 0x10002028 /* timer flag clear */
+#define JZ_TC_TMR 0x10002030 /* timer flag mask */
+#define JZ_TC_TMSR 0x10002034 /* timer flag mask set */
+#define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/
+
+#define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */
+#define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */
+#define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */
+
+#define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10))
+/* same bits as in JZ_WDOG_TCSR */
/* operating system timer */
#define JZ_OST_DATA 0x100020e0 /* compare */
@@ -102,4 +124,62 @@ readreg(uint32_t reg)
return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
}
-#endif /* INGENIC_REGS_H */
\ No newline at end of file
+/* extra CP0 registers */
+static inline uint32_t
+MFC0(uint32_t r, uint32_t s)
+{
+ uint32_t ret = 0x12345678;
+
+ __asm volatile(mfc0 %0, $%1, %2; nop; : =r(ret) : i(r), i(s));
+ return ret;
+}
+
+#define MTC0(v, r, s) __asm volatile(mtc0 %0, $%1, %2; nop; :: r(v), i(r), i(s))
+
+#define CP0_CORE_CTRL 12 /* select 2 */
+ #define CC_SW_RST0 1 /* reset core 0 */
+ #define CC_SW_RST1 2 /* reset core 1 */
+ #define CC_RPC0 0x100 /* dedicater reset entry core 0 */
+ #define CC_RPC1 0x200 /* -- || -- core 1 */
+ #define CC_SLEEP0M 0x1 /* mask sleep core 0 */
+ #define CC_SLEEP1M 0x2 /* mask sleep core 1 */
+
+/* cores status, 12 select 3 */
+#define CS_MIRQ0_P 0x1 /* mailbox IRQ for 0 pending */
+#define CS_MIRQ1_P 0x2 /* || core 1 */
+#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */
+#define CS_IRQ1_P 0x00200 /* || core 1 */
+#define CS_SLEEP0 0x1 /* core 0 sleeping */
+#define CS_SLEEP1 0x2 /* core 1 sleeping */
+
+/* cores reset entry IRQ masks - 12 select 4 */
+#define REIM_MIRQ0_M 0x1 /* allow mailbox IRQ for core 0 */
+#define REIM_MIRQ1_M 0x2 /* allow mailbox IRQ for core 1 */
+#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */
+#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */
+#define REIM_ENTRY_M 0x /* reset exception entry if RPCn=1 */
+
+#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
+
+/* interrupt controller */
+#define JZ_ICSR0 0x10001000 /* raw IRQ line status */
+#define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */
+#define JZ_ICMSR0 0x10001008 /* sets bits in mask register */
+#define JZ_ICMCR0 0x1000100c /* clears bits in maks register */
+#define JZ_ICPR0 0x10001010 /* line status after masking */
+
+#define JZ_ICSR1 0x10001020 /* raw IRQ line status */
+#define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */
+#define JZ_ICMSR1 0x10001028 /* sets bits in mask register */
CVS commit: src/sys/arch/mips/ingenic
Module Name:src Committed By: macallan Date: Sat Dec 6 14:33:18 UTC 2014 Modified Files: src/sys/arch/mips/ingenic: ingenic_com.c Log Message: sprinkle static To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_com.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/mips/ingenic/ingenic_com.c diff -u src/sys/arch/mips/ingenic/ingenic_com.c:1.1 src/sys/arch/mips/ingenic/ingenic_com.c:1.2 --- src/sys/arch/mips/ingenic/ingenic_com.c:1.1 Sat Nov 22 15:17:01 2014 +++ src/sys/arch/mips/ingenic/ingenic_com.c Sat Dec 6 14:33:18 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: ingenic_com.c,v 1.1 2014/11/22 15:17:01 macallan Exp $ */ +/* $NetBSD: ingenic_com.c,v 1.2 2014/12/06 14:33:18 macallan Exp $ */ /*- * Copyright (c) 2014 Michael Lorenz @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.1 2014/11/22 15:17:01 macallan Exp $); +__KERNEL_RCSID(0, $NetBSD: ingenic_com.c,v 1.2 2014/12/06 14:33:18 macallan Exp $); #include sys/param.h #include sys/systm.h @@ -60,8 +60,8 @@ void ingenic_putchar(char); #endif -struct mips_bus_space ingenic_com_mbst; -int mbst_valid = 0; +static struct mips_bus_space ingenic_com_mbst; +static int mbst_valid = 0; static void ingenic_com_bus_mem_init(bus_space_tag_t, void *); void ingenic_com_cnattach(void);
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Sat Dec 6 14:34:57 UTC 2014
Added Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_var.h
Log Message:
peripheral bus, not really tested
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/apbus.c \
src/sys/arch/mips/ingenic/ingenic_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u /dev/null src/sys/arch/mips/ingenic/apbus.c:1.1
--- /dev/null Sat Dec 6 14:34:57 2014
+++ src/sys/arch/mips/ingenic/apbus.c Sat Dec 6 14:34:56 2014
@@ -0,0 +1,136 @@
+/* $NetBSD: apbus.c,v 1.1 2014/12/06 14:34:56 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* catch-all for on-chip peripherals */
+
+#include sys/cdefs.h
+__KERNEL_RCSID(0, $NetBSD: apbus.c,v 1.1 2014/12/06 14:34:56 macallan Exp $);
+
+#include locators.h
+#define _MIPS_BUS_DMA_PRIVATE
+
+#include sys/param.h
+#include sys/bus.h
+#include sys/device.h
+#include sys/extent.h
+#include sys/systm.h
+
+#include mips/ingenic/ingenic_var.h
+#include mips/ingenic/ingenic_regs.h
+
+static int apbus_match(device_t, cfdata_t, void *);
+static void apbus_attach(device_t, device_t, void *);
+static int apbus_print(void *, const char *);
+static void apbus_bus_mem_init(bus_space_tag_t, void *);
+
+CFATTACH_DECL_NEW(apbus, 0, apbus_match, apbus_attach, NULL, NULL);
+
+static struct mips_bus_space apbus_mbst;
+bus_space_tag_t apbus_memt = NULL;
+
+struct mips_bus_dma_tag apbus_dmat = {
+ ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
+ ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
+ ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
+};
+
+static const char *apbus_devs[] = {
+ dwctwo,
+ jzgpio,
+ jzfb,
+ NULL
+};
+
+void
+apbus_init(void)
+{
+ static bool done = false;
+ if (done)
+ return;
+ done = true;
+
+ apbus_bus_mem_init(apbus_mbst, NULL);
+ apbus_memt = apbus_mbst;
+}
+
+int
+apbus_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mainbusdev {
+ const char *md_name;
+ } *aa = aux;
+ if (strcmp(aa-md_name, apbus) == 0) return 1;
+ return 0;
+}
+
+void
+apbus_attach(device_t parent, device_t self, void *aux)
+{
+ aprint_normal(\n);
+
+ /* should have been called early on */
+ apbus_init();
+
+printf(core ctrl: %08x\n, MFC0(12, 2));
+printf(core status: %08x\n, MFC0(12, 3));
+printf(REIM: %08x\n, MFC0(12, 4));
+printf(ID: %08x\n, MFC0(15, 1));
+
+ for (const char **adv = apbus_devs; *adv != NULL; adv++) {
+ struct apbus_attach_args aa;
+ aa.aa_name = *adv;
+ aa.aa_addr = 0;
+ aa.aa_dmat = apbus_dmat;
+ aa.aa_bst = apbus_memt;
+
+ (void) config_found_ia(self, apbus, aa, apbus_print);
+ }
+}
+
+int
+apbus_print(void *aux, const char *pnp)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (pnp)
+ aprint_normal(%s at %s, aa-aa_name, pnp);
+
+ if (aa-aa_addr)
+ aprint_normal( addr 0x% PRIxBUSADDR, aa-aa_addr);
+
+ return (UNCONF);
+}
+
+#define CHIP apbus
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x1000UL
+#define CHIP_W1_BUS_END(v) 0x2000UL
+#define CHIP_W1_SYS_START(v) 0x1000UL
+#define CHIP_W1_SYS_END(v) 0x2000UL
+
+#include mips/mips/bus_space_alignstride_chipdep.c
Index: src/sys/arch/mips/ingenic/ingenic_var.h
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_var.h:1.1
--- /dev/null Sat Dec 6 14:34:57 2014
+++ src/sys/arch/mips/ingenic/ingenic_var.h Sat Dec 6 14:34:56 2014
@@ -0,0 +1,44 @@
+/* $NetBSD: ingenic_var.h,v 1.1 2014/12/06 14:34:56 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights
CVS commit: src/sys/arch/mips/ingenic
Module Name:src
Committed By: macallan
Date: Sat Dec 6 14:35:47 UTC 2014
Added Files:
src/sys/arch/mips/ingenic: ingenic_dwctwo.c
Log Message:
dwc2 attachment, doesn't do much yet
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.1
--- /dev/null Sat Dec 6 14:35:47 2014
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Sat Dec 6 14:35:47 2014
@@ -0,0 +1,175 @@
+/* $NetBSD: ingenic_dwctwo.c,v 1.1 2014/12/06 14:35:47 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__KERNEL_RCSID(0, $NetBSD: ingenic_dwctwo.c,v 1.1 2014/12/06 14:35:47 macallan Exp $);
+
+/*
+ * adapted from bcm2835_dwctwo.c
+ */
+
+#include sys/param.h
+#include sys/systm.h
+#include sys/device.h
+#include sys/mutex.h
+#include sys/bus.h
+#include sys/workqueue.h
+
+#include mips/ingenic/ingenic_var.h
+#include mips/ingenic/ingenic_regs.h
+
+#include dev/usb/usb.h
+#include dev/usb/usbdi.h
+#include dev/usb/usbdivar.h
+#include dev/usb/usb_mem.h
+
+#include dwc2/dwc2var.h
+
+#include dwc2/dwc2.h
+#include dwc2_core.h
+
+struct ingenic_dwc2_softc {
+ struct dwc2_softc sc_dwc2;
+
+ void *sc_ih;
+};
+
+static struct dwc2_core_params ingenic_dwc2_params = {
+ .otg_cap = 0, /* HNP/SRP capable */
+ .otg_ver = 0, /* 1.3 */
+ .dma_enable = 1,
+ .dma_desc_enable = 0,
+ .speed= 0, /* High Speed */
+ .enable_dynamic_fifo = 1,
+ .en_multiple_tx_fifo = 1,
+ .host_rx_fifo_size = 774, /* 774 DWORDs */
+ .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
+ .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
+ .max_transfer_size = 65535,
+ .max_packet_count = 511,
+ .host_channels = 8,
+ .phy_type = 1, /* UTMI */
+ .phy_utmi_width = 8, /* 8 bits */
+ .phy_ulpi_ddr = 0, /* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0,
+ .host_support_fs_ls_low_power = 0,
+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
+ .ts_dline = 0,
+ .reload_ctl = 0,
+ .ahbcfg= 0x10,
+ .uframe_sched = 1,
+};
+
+static int ingenic_dwc2_match(device_t, struct cfdata *, void *);
+static void ingenic_dwc2_attach(device_t, device_t, void *);
+static void ingenic_dwc2_deferred(device_t);
+
+CFATTACH_DECL_NEW(ingenic_dwctwo, sizeof(struct ingenic_dwc2_softc),
+ingenic_dwc2_match, ingenic_dwc2_attach, NULL, NULL);
+
+/* ARGSUSED */
+static int
+ingenic_dwc2_match(device_t parent, struct cfdata *match, void *aux)
+{
+ struct apbus_attach_args *aa = aux;
+
+ if (strcmp(aa-aa_name, dwctwo) != 0)
+ return 0;
+
+ return 1;
+}
+
+/* ARGSUSED */
+static void
+ingenic_dwc2_attach(device_t parent, device_t self, void *aux)
+{
+ struct ingenic_dwc2_softc *sc = device_private(self);
+ struct apbus_attach_args *aa = aux;
+ int error;
+
+ sc-sc_dwc2.sc_dev = self;
+
+ sc-sc_dwc2.sc_iot = aa-aa_bst;
+ sc-sc_dwc2.sc_bus.dmatag = aa-aa_dmat;
+ sc-sc_dwc2.sc_params = ingenic_dwc2_params;
+
+ if (aa-aa_addr == 0)
+ aa-aa_addr = 0x1350;
+
+ error = bus_space_map(aa-aa_bst, aa-aa_addr, 0x2, 0,
+ sc-sc_dwc2.sc_ioh);
+ if (error) {
+ aprint_error_dev(self,
+ can't map registers for %s: %d\n, aa-aa_name, error);
+ return;
+ }
+
+ aprint_naive(: USB controller\n);
+ aprint_normal(: USB controller\n);
+
+#if notyet
+ sc-sc_ih = bcm2835_intr_establish(aaa-aaa_intr, IPL_SCHED,
+ dwc2_intr, sc-sc_dwc2);
+
+ if (sc-sc_ih == NULL) {
+
