CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri May 19 07:40:58 UTC 2017

Modified Files:
src/sys/arch/evbmips/ingenic: autoconf.c clock.c cpu.c machdep.c
mainbus.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/autoconf.c \
src/sys/arch/evbmips/ingenic/cpu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/clock.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/autoconf.c
diff -u src/sys/arch/evbmips/ingenic/autoconf.c:1.2 src/sys/arch/evbmips/ingenic/autoconf.c:1.3
--- src/sys/arch/evbmips/ingenic/autoconf.c:1.2	Thu Oct  8 17:51:15 2015
+++ src/sys/arch/evbmips/ingenic/autoconf.c	Fri May 19 07:40:58 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.2 2015/10/08 17:51:15 macallan Exp $ */
+/* $NetBSD: autoconf.c,v 1.3 2017/05/19 07:40:58 skrll Exp $ */
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.2 2015/10/08 17:51:15 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
 
 #include 
 #include 
@@ -46,7 +46,7 @@ void ingenic_set_enaddr(uint8_t *);
 
 /*
  * Configure all devices on system
- */ 
+ */
 void
 cpu_configure(void)
 {
@@ -72,7 +72,7 @@ device_register(device_t dev, void *aux)
 	if (device_is_a(dev, "dme") && have_enaddr) {
 		prop_dictionary_t dict;
 		prop_data_t blob;
-		
+
 		dict = device_properties(dev);
 
 		blob = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
Index: src/sys/arch/evbmips/ingenic/cpu.c
diff -u src/sys/arch/evbmips/ingenic/cpu.c:1.2 src/sys/arch/evbmips/ingenic/cpu.c:1.3
--- src/sys/arch/evbmips/ingenic/cpu.c:1.2	Fri Aug 26 13:54:18 2016
+++ src/sys/arch/evbmips/ingenic/cpu.c	Fri May 19 07:40:58 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.2 2016/08/26 13:54:18 skrll Exp $	*/
+/*	$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2016/08/26 13:54:18 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
 
 #include "opt_ingenic.h"
 #include "opt_multiprocessor.h"
@@ -79,7 +79,7 @@ cpu_attach(device_t parent, device_t sel
 #ifdef MULTIPROCESSOR
 		uint32_t vec, reg;
 		int bail = 1;
-		
+
 		startup_cpu_info = cpu_info_alloc(NULL, unit, 0, unit, 0);
 		startup_cpu_info->ci_cpu_freq = ci->ci_cpu_freq;
 		ci = startup_cpu_info;

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.8 src/sys/arch/evbmips/ingenic/clock.c:1.9
--- src/sys/arch/evbmips/ingenic/clock.c:1.8	Fri Aug 26 15:45:48 2016
+++ src/sys/arch/evbmips/ingenic/clock.c	Fri May 19 07:40:58 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.8 2016/08/26 15:45:48 skrll Exp $ */
+/*	$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.8 2016/08/26 15:45:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $");
 
 #include "opt_multiprocessor.h"
 
@@ -87,7 +87,7 @@ cpu_initclocks(void)
 	 * that to work yet ( all I get is INT0 which is for hardware interrupts
 	 * in general )
 	 * So if we can get OST to fire on INT2 we can just block INT0 on core1
-	 * and have a timer interrupt on both cores, if not the regular timer 
+	 * and have a timer interrupt on both cores, if not the regular timer
 	 * would be more convenient but we'd have to shoot an IPI to core1 on
 	 * every tick.
 	 * For now, use OST and hope we'll figure out how to make it fire on
@@ -129,7 +129,7 @@ cpu_initclocks(void)
 	printf("cnt5: %08x\n", readreg(JZ_TC_TCNT(5)));
 	printf("CR: %08x\n", MFC0(MIPS_COP_0_CAUSE, 0));
 	printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));
-	
+
 	printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
 	delay(300);
 	printf("%s %d\n", __func__, MFC0(12, 3));
@@ -209,8 +209,8 @@ ingenic_clockintr(struct clockframe *cf)
 	/* Check for lost clock interrupts */
 	new_cnt = readreg(JZ_OST_CNT_LO);
 
-	/* 
-	 * Missed one or more clock interrupts, so let's start 
+	/*
+	 * Missed one or more clock interrupts, so let's start
 	 * counting again from the current value.
 	 */
 	if ((ci->ci_next_cp0_clk_intr - new_cnt) & 0x8000) {

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.12 src/sys/arch/evbmips/ingenic/machdep.c:1.13
--- src/sys/arch/evbmips/ingenic/machdep.c:1.12	Thu Dec 22 14:47:57 2016
+++ src/sys/arch/evbmips/ingenic/machdep.c	Fri May 19 07:40:58 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri May 19 07:40:58 UTC 2017

Modified Files:
src/sys/arch/evbmips/ingenic: autoconf.c clock.c cpu.c machdep.c
mainbus.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/autoconf.c \
src/sys/arch/evbmips/ingenic/cpu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/clock.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat Aug 27 05:52:43 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.11 src/sys/arch/evbmips/ingenic/intr.c:1.12
--- src/sys/arch/evbmips/ingenic/intr.c:1.11	Fri Aug 26 15:45:48 2016
+++ src/sys/arch/evbmips/ingenic/intr.c	Sat Aug 27 05:52:43 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.11 2016/08/26 15:45:48 skrll Exp $ */
+/*	$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.11 2016/08/26 15:45:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
 
 #define __INTR_PRIVATE
 
@@ -143,7 +143,7 @@ evbmips_iointr(int ipl, uint32_t ipendin
 	uint32_t id;
 #ifdef INGENIC_INTR_DEBUG
 	char buffer[256];
-	
+
 #if 0
 	snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
 	MFC0(MIPS_COP_0_CAUSE, 0));
@@ -172,7 +172,7 @@ evbmips_iointr(int ipl, uint32_t ipendin
 #ifdef MULTIPROCESSOR
 uint32_t tag;
 tag = MFC0(CP0_CORE_MBOX, 0);
-	
+
 ipi_process(curcpu(), tag);
 #ifdef INGENIC_INTR_DEBUG
 snprintf(buffer, 256,
@@ -222,9 +222,9 @@ evbmips_iointr(int ipl, uint32_t ipendin
 		 * but I haven't seen them there so for now we just weed them
 		 * out right here.
 		 * The idea is to allow peripheral interrupts on both cores but
-		 * block INT0 on core1 so it would see only timer interrupts 
+		 * block INT0 on core1 so it would see only timer interrupts
 		 * and IPIs. If that doesn't work we'll have to send an IPI to
-		 * core1 for each timer tick.  
+		 * core1 for each timer tick.
 		 */
 		mask = readreg(JZ_ICPR0);
 		if (mask & 0x0c00) {
@@ -268,13 +268,13 @@ ingenic_irq(int ipl)
 		if (intrs[idx].ih_func != NULL) {
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_LOCK(1, NULL);
-			intrs[idx].ih_func(intrs[idx].ih_arg);	
+			intrs[idx].ih_func(intrs[idx].ih_arg);
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_UNLOCK_ONE(NULL);
 		} else {
 			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR0, mask);
-		}		
+		}
 		irql &= ~mask;
 		bit = ffs32(irql);
 		bail--;
@@ -296,13 +296,13 @@ ingenic_irq(int ipl)
 		if (intrs[idx].ih_func != NULL) {
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_LOCK(1, NULL);
-			intrs[idx].ih_func(intrs[idx].ih_arg);	
+			intrs[idx].ih_func(intrs[idx].ih_arg);
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_UNLOCK_ONE(NULL);
 		} else {
 			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR1, mask);
-		}		
+		}
 		irqh &= ~mask;
 		bit = ffs32(irqh);
 	}

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat Aug 27 05:52:43 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri Aug 26 13:54:18 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: cpu.c

Log Message:
#include "opt_multiprocessor.h"


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri Aug 26 13:54:18 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: cpu.c

Log Message:
#include "opt_multiprocessor.h"


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/cpu.c
diff -u src/sys/arch/evbmips/ingenic/cpu.c:1.1 src/sys/arch/evbmips/ingenic/cpu.c:1.2
--- src/sys/arch/evbmips/ingenic/cpu.c:1.1	Fri Jan 29 01:54:14 2016
+++ src/sys/arch/evbmips/ingenic/cpu.c	Fri Aug 26 13:54:18 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $	*/
+/*	$NetBSD: cpu.c,v 1.2 2016/08/26 13:54:18 skrll Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,10 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.2 2016/08/26 13:54:18 skrll Exp $");
+
+#include "opt_ingenic.h"
+#include "opt_multiprocessor.h"
 
 #include 
 #include 
@@ -47,8 +50,6 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1 
 #include 
 #include 
 
-#include "opt_ingenic.h"
-
 static int	cpu_match(device_t, cfdata_t, void *);
 static void	cpu_attach(device_t, device_t, void *);
 

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri Aug 26 13:53:36 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
#include "opt_multiprocessor.h"


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.10 src/sys/arch/evbmips/ingenic/machdep.c:1.11
--- src/sys/arch/evbmips/ingenic/machdep.c:1.10	Fri Jan 29 01:54:14 2016
+++ src/sys/arch/evbmips/ingenic/machdep.c	Fri Aug 26 13:53:36 2016
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.10 2016/01/29 01:54:14 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.11 2016/08/26 13:53:36 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,11 +27,12 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.10 2016/01/29 01:54:14 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.11 2016/08/26 13:53:36 skrll Exp $");
 
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_modular.h"
+#include "opt_multiprocessor.h"
 
 #include 
 #include 

CVS commit: src/sys/arch/evbmips/ingenic

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Fri Aug 26 13:53:36 UTC 2016

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
#include "opt_multiprocessor.h"


To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Oct  8 17:51:15 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: autoconf.c

Log Message:
add mechanism to pass a MAC address to dme


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/autoconf.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/autoconf.c
diff -u src/sys/arch/evbmips/ingenic/autoconf.c:1.1 src/sys/arch/evbmips/ingenic/autoconf.c:1.2
--- src/sys/arch/evbmips/ingenic/autoconf.c:1.1	Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/autoconf.c	Thu Oct  8 17:51:15 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+/* $NetBSD: autoconf.c,v 1.2 2015/10/08 17:51:15 macallan Exp $ */
 
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include 
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.1 2014/11/22 15:17:02 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.2 2015/10/08 17:51:15 macallan Exp $");
 
 #include 
 #include 
@@ -38,6 +38,12 @@ __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v
 #include 
 #include 
 
+#include 
+
+static uint8_t enaddr[ETHER_ADDR_LEN];
+static int have_enaddr = false;
+void ingenic_set_enaddr(uint8_t *);
+
 /*
  * Configure all devices on system
  */ 
@@ -63,7 +69,24 @@ cpu_rootconf(void)
 void
 device_register(device_t dev, void *aux)
 {
+	if (device_is_a(dev, "dme") && have_enaddr) {
+		prop_dictionary_t dict;
+		prop_data_t blob;
+		
+		dict = device_properties(dev);
+
+		blob = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
+		prop_dictionary_set(dict, "mac-address", blob);
+		prop_object_release(blob);
+	}
 #ifdef notyet
 	(*platformsw->apsw_device_register)(dev, aux);
 #endif
 }
+
+void
+ingenic_set_enaddr(uint8_t *goop)
+{
+	memcpy(enaddr, goop, ETHER_ADDR_LEN);
+	have_enaddr = true;
+}

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Oct  8 17:51:15 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: autoconf.c

Log Message:
add mechanism to pass a MAC address to dme


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/autoconf.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Jun 30 04:10:10 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
don't mess with the cycle counter event counter, out timer interrupt comes
from elsewhere and is counted there


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.5 src/sys/arch/evbmips/ingenic/clock.c:1.6
--- src/sys/arch/evbmips/ingenic/clock.c:1.5	Wed Dec 31 15:25:08 2014
+++ src/sys/arch/evbmips/ingenic/clock.c	Tue Jun 30 04:10:10 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $ */
+/*	$NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $);
+__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $);
 
 #include sys/param.h
 #include sys/cpu.h
@@ -194,7 +194,6 @@ ingenic_clockintr(uint32_t id)
 #ifdef USE_OST
 	uint32_t new_cnt;
 #endif
-	ci-ci_ev_count_compare.ev_count++;
 
 	/* clear flags */
 	writereg(JZ_TC_TFCR, TFR_OSTFLAG);

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Jun 30 04:10:10 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
don't mess with the cycle counter event counter, out timer interrupt comes
from elsewhere and is counted there


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Jun 11 15:38:19 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
use kcpuset_isset()


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.6 src/sys/arch/evbmips/ingenic/machdep.c:1.7
--- src/sys/arch/evbmips/ingenic/machdep.c:1.6	Sat Apr  4 13:06:01 2015
+++ src/sys/arch/evbmips/ingenic/machdep.c	Thu Jun 11 15:38:18 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.7 2015/06/11 15:38:18 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.7 2015/06/11 15:38:18 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -138,7 +138,7 @@ ingenic_send_ipi(struct cpu_info *ci, in
 
 	msg = 1  tag;
 
-	if (cpus_running  (1  cpu_index(ci))) {
+	if (kcpuset_isset(cpus_running, cpu_index(ci))) {
 		if (cpu_index(ci) == 0) {
 			MTC0(msg, CP0_CORE_MBOX, 0);
 		} else {

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Jun 11 15:38:19 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
use kcpuset_isset()


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Apr  4 13:06:01 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c machdep.c mainbus.c

Log Message:
add IPI support
compile-tested only since we don't actually spin up the 2nd core yet


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/intr.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.8 src/sys/arch/evbmips/ingenic/intr.c:1.9
--- src/sys/arch/evbmips/ingenic/intr.c:1.8	Sat Mar 28 16:57:23 2015
+++ src/sys/arch/evbmips/ingenic/intr.c	Sat Apr  4 13:06:01 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.9 2015/04/04 13:06:01 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.9 2015/04/04 13:06:01 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -121,7 +121,7 @@ evbmips_intr_init(void)
 	/* allow peripheral interrupts to core 0 only */
 	reg = MFC0(12, 4);	/* reset entry and interrupts */
 	reg = 0x;
-	reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M;
+	reg |= REIM_IRQ0_M | REIM_MIRQ0_M;
 	MTC0(reg, 12, 4);
 }
 
@@ -149,7 +149,6 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 	if (ipending  MIPS_INT_MASK_1) {
 		/*
 		 * this is a mailbox interrupt / IPI
-		 * for now just print the message and clear it
 		 */
 		uint32_t reg;
 
@@ -157,26 +156,34 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		reg = MFC0(12, 3);
 		if (id == 0) {
 			if (reg  CS_MIRQ0_P) {
+#ifdef MULTIPROCESSOR
+uint32_t tag;
+tag = MFC0(CP0_CORE_MBOX, 0);
 	
+ipi_process(curcpu(), tag);
 #ifdef INGENIC_INTR_DEBUG
 snprintf(buffer, 256,
-IPI for core 0, msg %08x\n,
-MFC0(CP0_CORE_MBOX, 0));
+IPI for core 0, msg %08x\n, tag);
 ingenic_puts(buffer);
 #endif
+#endif
 reg = (~CS_MIRQ0_P);
 /* clear it */
 MTC0(reg, 12, 3);
 			}
 		} else if (id == 1) {
 			if (reg  CS_MIRQ1_P) {
+#ifdef MULTIPROCESSOR
+uint32_t tag;
+tag = MFC0(CP0_CORE_MBOX, 1);
+ipi_process(curcpu(), tag);
 #ifdef INGENIC_INTR_DEBUG
 snprintf(buffer, 256,
-IPI for core 1, msg %08x\n,
-MFC0(CP0_CORE_MBOX, 1));
+IPI for core 1, msg %08x\n, tag);
 ingenic_puts(buffer);
 #endif
-reg = ( 7 - CS_MIRQ1_P);
+#endif
+reg = (~CS_MIRQ1_P);
 /* clear it */
 MTC0(reg, 12, 3);
 			}

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.5 src/sys/arch/evbmips/ingenic/machdep.c:1.6
--- src/sys/arch/evbmips/ingenic/machdep.c:1.5	Tue Mar 10 22:39:38 2015
+++ src/sys/arch/evbmips/ingenic/machdep.c	Sat Apr  4 13:06:01 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.6 2015/04/04 13:06:01 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -115,6 +115,40 @@ cal_timer(void)
 	do {} while (junk == readreg(JZ_OST_CNT_LO));
 }
 
+#ifdef MULTIPROCESSOR
+static void
+ingenic_cpu_init(struct cpu_info *ci)
+{
+	uint32_t reg;
+
+	/* enable IPIs for this core */
+	reg = MFC0(12, 4);	/* reset entry and interrupts */
+	reg = 0x;
+	if (cpu_index(ci) == 1) {
+		reg |= REIM_MIRQ1_M;
+	} else
+		reg |= REIM_MIRQ0_M;
+	MTC0(reg, 12, 4);
+}
+
+static int
+ingenic_send_ipi(struct cpu_info *ci, int tag)
+{
+	uint32_t msg;
+
+	msg = 1  tag;
+
+	if (cpus_running  (1  cpu_index(ci))) {
+		if (cpu_index(ci) == 0) {
+			MTC0(msg, CP0_CORE_MBOX, 0);
+		} else {
+			MTC0(msg, CP0_CORE_MBOX, 1);
+		}
+	}
+	return 0;
+}
+#endif
+
 void
 mach_init(void)
 {
@@ -154,7 +188,11 @@ mach_init(void)
 	printf(Memory size: 0x%08x\n, memsize);
 	physmem = btoc(memsize);
 
-	/* XXX this is CI20 specific */
+	/*
+	 * memory is at 0x2000 with first 256MB mirrored to 0x so
+	 * we can see them through KSEG*
+	 * assume 1GB for now, the SoC can theoretically support up to 3GB
+	 */
 	mem_clusters[0].start = PAGE_SIZE;
 	mem_clusters[0].size = 0x1000 - PAGE_SIZE;
 	mem_clusters[1].start = 0x3000;
@@ -182,6 +220,11 @@ mach_init(void)
 	 */
 	mips_init_lwp0_uarea();
 
+#ifdef MULTIPROCESSOR
+	mips_locoresw.lsw_send_ipi = ingenic_send_ipi;
+	mips_locoresw.lsw_cpu_init = ingenic_cpu_init;
+#endif
+
 	apbus_init();
 	/*
 	 * Initialize debuggers, and break into them, if 

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Apr  4 13:06:01 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c machdep.c mainbus.c

Log Message:
add IPI support
compile-tested only since we don't actually spin up the 2nd core yet


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/intr.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar 28 16:57:23 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
PIC - INTC to match documentation
no functional change


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.7 src/sys/arch/evbmips/ingenic/intr.c:1.8
--- src/sys/arch/evbmips/ingenic/intr.c:1.7	Wed Mar 11 12:40:36 2015
+++ src/sys/arch/evbmips/ingenic/intr.c	Sat Mar 28 16:57:23 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.8 2015/03/28 16:57:23 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -111,7 +111,7 @@ evbmips_intr_init(void)
 		snprintf(intrs[i].ih_name, sizeof(intrs[i].ih_name),
 		irq %d, i);
 		evcnt_attach_dynamic(intrs[i].ih_count, EVCNT_TYPE_INTR,
-		NULL, PIC, intrs[i].ih_name);
+		NULL, INTC, intrs[i].ih_name);
 	}
 
 	/* mask all peripheral IRQs */

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar 28 16:57:23 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
PIC - INTC to match documentation
no functional change


To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Wed Mar 11 12:40:36 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
add an event counter for clock interrupts


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.6 src/sys/arch/evbmips/ingenic/intr.c:1.7
--- src/sys/arch/evbmips/ingenic/intr.c:1.6	Sat Mar  7 15:37:46 2015
+++ src/sys/arch/evbmips/ingenic/intr.c	Wed Mar 11 12:40:36 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -89,6 +89,7 @@ struct intrhand {
 };
 
 struct intrhand intrs[NINTR];
+struct evcnt clockintrs;
 
 void ingenic_irq(int);
 
@@ -100,6 +101,9 @@ evbmips_intr_init(void)
 
 	ipl_sr_map = ingenic_ipl_sr_map;
 
+	evcnt_attach_dynamic(clockintrs,
+	EVCNT_TYPE_INTR, NULL, timer, intr);
+
 	/* zero all handlers */
 	for (i = 0; i  NINTR; i++) {
 		intrs[i].ih_func = NULL;
@@ -181,6 +185,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 	if (ipending  MIPS_INT_MASK_2) {
 		/* this is a timer interrupt */
 		ingenic_clockintr(id);
+		clockintrs.ev_count++;
 		ingenic_puts(INT2\n);
 	}
 	if (ipending  MIPS_INT_MASK_0) {
@@ -202,6 +207,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 			writereg(JZ_ICMSR0, mask);
 			ingenic_clockintr(id);
 			writereg(JZ_ICMCR0, mask);
+			clockintrs.ev_count++;
 		}
 		ingenic_irq(ipl);
 		KASSERT(id == 0);

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Wed Mar 11 12:40:36 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
add an event counter for clock interrupts


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Mar 10 22:39:38 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
enable the full 1GB of RAM
TODO: actually probe for it


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.4 src/sys/arch/evbmips/ingenic/machdep.c:1.5
--- src/sys/arch/evbmips/ingenic/machdep.c:1.4	Sat Mar  7 15:38:32 2015
+++ src/sys/arch/evbmips/ingenic/machdep.c	Tue Mar 10 22:39:38 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.4 2015/03/07 15:38:32 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.4 2015/03/07 15:38:32 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.5 2015/03/10 22:39:38 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -149,7 +149,7 @@ mach_init(void)
 	 * Note: Reserve the first page!  That's where the trap
 	 * vectors are located.
 	 */
-	memsize = 0x1000;
+	memsize = 0x4000;
 
 	printf(Memory size: 0x%08x\n, memsize);
 	physmem = btoc(memsize);
@@ -159,7 +159,7 @@ mach_init(void)
 	mem_clusters[0].size = 0x1000 - PAGE_SIZE;
 	mem_clusters[1].start = 0x3000;
 	mem_clusters[1].size = 0x3000;
-	mem_cluster_cnt = 1;
+	mem_cluster_cnt = 2;
 
 	/*
 	 * Load the available pages into the VM system.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Mar 10 22:39:38 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
enable the full 1GB of RAM
TODO: actually probe for it


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar  7 15:38:32 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
only use the first 256MB for now until I figure out how to properly access
the rest


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar  7 15:37:46 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
count all interrupts, not just the ones we have handlers for


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar  7 15:38:32 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c

Log Message:
only use the first 256MB for now until I figure out how to properly access
the rest


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.3 src/sys/arch/evbmips/ingenic/machdep.c:1.4
--- src/sys/arch/evbmips/ingenic/machdep.c:1.3	Tue Dec 23 15:09:13 2014
+++ src/sys/arch/evbmips/ingenic/machdep.c	Sat Mar  7 15:38:32 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.3 2014/12/23 15:09:13 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.4 2015/03/07 15:38:32 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.3 2014/12/23 15:09:13 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.4 2015/03/07 15:38:32 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -149,7 +149,7 @@ mach_init(void)
 	 * Note: Reserve the first page!  That's where the trap
 	 * vectors are located.
 	 */
-	memsize = 0x4000;
+	memsize = 0x1000;
 
 	printf(Memory size: 0x%08x\n, memsize);
 	physmem = btoc(memsize);
@@ -159,7 +159,7 @@ mach_init(void)
 	mem_clusters[0].size = 0x1000 - PAGE_SIZE;
 	mem_clusters[1].start = 0x3000;
 	mem_clusters[1].size = 0x3000;
-	mem_cluster_cnt = 2;
+	mem_cluster_cnt = 1;
 
 	/*
 	 * Load the available pages into the VM system.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Mar  7 15:37:46 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
count all interrupts, not just the ones we have handlers for


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.5 src/sys/arch/evbmips/ingenic/intr.c:1.6
--- src/sys/arch/evbmips/ingenic/intr.c:1.5	Thu Mar  5 17:42:29 2015
+++ src/sys/arch/evbmips/ingenic/intr.c	Sat Mar  7 15:37:46 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.5 2015/03/05 17:42:29 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.5 2015/03/05 17:42:29 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -234,13 +234,13 @@ ingenic_irq(int ipl)
 	while (bit != 0) {
 		idx = bit - 1;
 		mask = 1  idx;
+		intrs[idx].ih_count.ev_count++;
 		if (intrs[idx].ih_func != NULL) {
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_LOCK(1, NULL);
 			intrs[idx].ih_func(intrs[idx].ih_arg);	
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_UNLOCK_ONE(NULL);
-			intrs[idx].ih_count.ev_count++;
 		} else {
 			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR0, mask);
@@ -262,13 +262,13 @@ ingenic_irq(int ipl)
 		idx = bit - 1;
 		mask = 1  idx;
 		idx += 32;
+		intrs[idx].ih_count.ev_count++;
 		if (intrs[idx].ih_func != NULL) {
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_LOCK(1, NULL);
 			intrs[idx].ih_func(intrs[idx].ih_arg);	
 			if (intrs[idx].ih_ipl == IPL_VM)
 KERNEL_UNLOCK_ONE(NULL);
-			intrs[idx].ih_count.ev_count++;
 		} else {
 			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR1, mask);

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Mar  5 17:42:29 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
disable interrupts while processing them, reenable when we're done


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Thu Mar  5 17:42:29 UTC 2015

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
disable interrupts while processing them, reenable when we're done


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.4 src/sys/arch/evbmips/ingenic/intr.c:1.5
--- src/sys/arch/evbmips/ingenic/intr.c:1.4	Fri Dec 26 18:06:52 2014
+++ src/sys/arch/evbmips/ingenic/intr.c	Thu Mar  5 17:42:29 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.4 2014/12/26 18:06:52 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.5 2015/03/05 17:42:29 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.4 2014/12/26 18:06:52 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.5 2015/03/05 17:42:29 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -184,6 +184,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		ingenic_puts(INT2\n);
 	}
 	if (ipending  MIPS_INT_MASK_0) {
+		uint32_t mask;
 		/* peripheral interrupt */
 
 		/*
@@ -196,8 +197,11 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		 * and IPIs. If that doesn't work we'll have to send an IPI to
 		 * core1 for each timer tick.  
 		 */
-		if (readreg(JZ_ICPR0)  0x0c00) {
+		mask = readreg(JZ_ICPR0);
+		if (mask  0x0c00) {
+			writereg(JZ_ICMSR0, mask);
 			ingenic_clockintr(id);
+			writereg(JZ_ICMCR0, mask);
 		}
 		ingenic_irq(ipl);
 		KASSERT(id == 0);
@@ -207,13 +211,14 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 void
 ingenic_irq(int ipl)
 {
-	uint32_t irql, irqh, mask;
+	uint32_t irql, irqh, mask, ll, hh;
 	int bit, idx, bail;
 #ifdef INGENIC_INTR_DEBUG
 	char buffer[16];
 #endif
 
 	irql = readreg(JZ_ICPR0);
+	irqh = readreg(JZ_ICPR1);
 #ifdef INGENIC_INTR_DEBUG
 	if (irql != 0) {
 		snprintf(buffer, 16,  il%08x, irql);
@@ -221,6 +226,10 @@ ingenic_irq(int ipl)
 	}
 #endif
 	bail = 32;
+	ll = irql;
+	hh = irqh;
+	writereg(JZ_ICMSR0, ll);
+	writereg(JZ_ICMSR1, hh);
 	bit = ffs32(irql);
 	while (bit != 0) {
 		idx = bit - 1;
@@ -242,7 +251,6 @@ ingenic_irq(int ipl)
 		KASSERT(bail  0);
 	}
 
-	irqh = readreg(JZ_ICPR1);
 #ifdef INGENIC_INTR_DEBUG
 	if (irqh != 0) {
 		snprintf(buffer, 16,  ih%08x, irqh);
@@ -268,6 +276,8 @@ ingenic_irq(int ipl)
 		irqh = ~mask;
 		bit = ffs32(irqh);
 	}
+	writereg(JZ_ICMCR0, ll);
+	writereg(JZ_ICMCR1, hh);
 }
 
 void *

CVS commit: src/sys/arch/evbmips/ingenic

[Martin Husemann]

Module Name:src
Committed By:   martin
Date:   Wed Dec 31 15:25:08 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
Move struct clockframe cf as extern declaration into ingenic_clockintr(),
to avoid a duplicate common.


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.4 src/sys/arch/evbmips/ingenic/clock.c:1.5
--- src/sys/arch/evbmips/ingenic/clock.c:1.4	Fri Dec 26 17:43:32 2014
+++ src/sys/arch/evbmips/ingenic/clock.c	Wed Dec 31 15:25:08 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $ */
+/*	$NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.5 2014/12/31 15:25:08 martin Exp $);
 
 #include sys/param.h
 #include sys/cpu.h
@@ -44,8 +44,6 @@ extern void ingenic_puts(const char *);
 
 void ingenic_clockintr(uint32_t);
 
-struct clockframe cf;
-
 static u_int
 ingenic_count_read(struct timecounter *tc)
 {
@@ -191,6 +189,7 @@ int cnt = 99;
 void
 ingenic_clockintr(uint32_t id)
 {
+	extern struct clockframe cf;
 	struct cpu_info * const ci = curcpu();
 #ifdef USE_OST
 	uint32_t new_cnt;

CVS commit: src/sys/arch/evbmips/ingenic

[Martin Husemann]

Module Name:src
Committed By:   martin
Date:   Wed Dec 31 15:25:08 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
Move struct clockframe cf as extern declaration into ingenic_clockintr(),
to avoid a duplicate common.


To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Fri Dec 26 17:43:32 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.3 src/sys/arch/evbmips/ingenic/clock.c:1.4
--- src/sys/arch/evbmips/ingenic/clock.c:1.3	Tue Dec 23 15:07:33 2014
+++ src/sys/arch/evbmips/ingenic/clock.c	Fri Dec 26 17:43:32 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $ */
+/*	$NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $);
 
 #include sys/param.h
 #include sys/cpu.h
@@ -75,8 +75,8 @@ cpu_initclocks(void)
 	/* start the timer interrupt */
 	cnt = readreg(JZ_OST_CNT_LO);
 	ci-ci_next_cp0_clk_intr = cnt + ci-ci_cycles_per_hz;
-	writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
 	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+	writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
 	/*
 	 * XXX
 	 * We can use OST or one of the regular timers to generate the 100hz
@@ -93,7 +93,7 @@ cpu_initclocks(void)
 	 * For now, use OST and hope we'll figure out how to make it fire on
 	 * INT2.
 	 */
-#if 1
+#ifdef USE_OST
 	writereg(JZ_TC_TMCR, TFR_OSTFLAG);
 #else
 	writereg(JZ_TC_TECR, TESR_TCST5);	/* disable timer 5 */
@@ -108,8 +108,9 @@ cpu_initclocks(void)
 
 #ifdef INGENIC_CLOCK_DEBUG
 	printf(INTC %08x %08x\n, readreg(JZ_ICSR0), readreg(JZ_ICSR1));
-	writereg(JZ_ICMCR0, 0x0c00); /* TCU2, OST */
+	printf(ICMR0 %08x\n, readreg(JZ_ICMR0));
 #endif
+	writereg(JZ_ICMCR0, 0x0c00); /* TCU2, OST */
 	spl0();
 #ifdef INGENIC_CLOCK_DEBUG
 	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
@@ -191,8 +192,9 @@ void
 ingenic_clockintr(uint32_t id)
 {
 	struct cpu_info * const ci = curcpu();
+#ifdef USE_OST
 	uint32_t new_cnt;
-
+#endif
 	ci-ci_ev_count_compare.ev_count++;
 
 	/* clear flags */
@@ -200,6 +202,7 @@ ingenic_clockintr(uint32_t id)
 
 	KASSERT((ci-ci_cycles_per_hz  ~(0x)) == 0);
 	ci-ci_next_cp0_clk_intr += (uint32_t)(ci-ci_cycles_per_hz  0x);
+#ifdef USE_OST
 	writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
 
 	/* Check for lost clock interrupts */
@@ -215,6 +218,10 @@ ingenic_clockintr(uint32_t id)
 		writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
 		curcpu()-ci_ev_count_compare_missed.ev_count++;
 	}
+	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+#else
+	writereg(JZ_TC_TFCR, TFR_FFLAG5);
+#endif
 
 #ifdef INGENIC_CLOCK_DEBUG
 	cnt++;

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Fri Dec 26 18:06:52 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
make interrupt names part of the handler struct so event counters will show
up correctly
also reshuffle debug code a bit


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.3 src/sys/arch/evbmips/ingenic/intr.c:1.4
--- src/sys/arch/evbmips/ingenic/intr.c:1.3	Tue Dec 23 16:17:39 2014
+++ src/sys/arch/evbmips/ingenic/intr.c	Fri Dec 26 18:06:52 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.3 2014/12/23 16:17:39 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.4 2014/12/26 18:06:52 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.3 2014/12/23 16:17:39 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.4 2014/12/26 18:06:52 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -82,6 +82,7 @@ static const struct ipl_sr_map ingenic_i
 /* some timer channels share interrupts, couldn't find any others */
 struct intrhand {
 	struct evcnt ih_count;
+	char ih_name[16];
 	int (*ih_func)(void *);
 	void *ih_arg;
 	int ih_ipl;
@@ -96,7 +97,6 @@ evbmips_intr_init(void)
 {
 	uint32_t reg;
 	int i;
-	char irqstr[8];
 
 	ipl_sr_map = ingenic_ipl_sr_map;
 
@@ -104,9 +104,10 @@ evbmips_intr_init(void)
 	for (i = 0; i  NINTR; i++) {
 		intrs[i].ih_func = NULL;
 		intrs[i].ih_arg = NULL;
-		snprintf(irqstr, sizeof(irqstr), irq %d, i);
+		snprintf(intrs[i].ih_name, sizeof(intrs[i].ih_name),
+		irq %d, i);
 		evcnt_attach_dynamic(intrs[i].ih_count, EVCNT_TYPE_INTR,
-		NULL, PIC, irqstr);
+		NULL, PIC, intrs[i].ih_name);
 	}
 
 	/* mask all peripheral IRQs */
@@ -127,10 +128,12 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 #ifdef INGENIC_INTR_DEBUG
 	char buffer[256];
 	
+#if 0
 	snprintf(buffer, 256, pending: %08x CR %08x\n, ipending,
 	MFC0(MIPS_COP_0_CAUSE, 0));
 	ingenic_puts(buffer);
 #endif
+#endif
 	/* see which core we're on */
 	id = MFC0(15, 1)  7;
 
@@ -193,7 +196,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		 * and IPIs. If that doesn't work we'll have to send an IPI to
 		 * core1 for each timer tick.  
 		 */
-		if (readreg(JZ_ICPR0)  0x0800) {
+		if (readreg(JZ_ICPR0)  0x0c00) {
 			ingenic_clockintr(id);
 		}
 		ingenic_irq(ipl);
@@ -205,7 +208,7 @@ void
 ingenic_irq(int ipl)
 {
 	uint32_t irql, irqh, mask;
-	int bit, idx;
+	int bit, idx, bail;
 #ifdef INGENIC_INTR_DEBUG
 	char buffer[16];
 #endif
@@ -217,6 +220,7 @@ ingenic_irq(int ipl)
 		ingenic_puts(buffer);
 	}
 #endif
+	bail = 32;
 	bit = ffs32(irql);
 	while (bit != 0) {
 		idx = bit - 1;
@@ -234,6 +238,8 @@ ingenic_irq(int ipl)
 		}		
 		irql = ~mask;
 		bit = ffs32(irql);
+		bail--;
+		KASSERT(bail  0);
 	}
 
 	irqh = readreg(JZ_ICPR1);
@@ -262,7 +268,6 @@ ingenic_irq(int ipl)
 		irqh = ~mask;
 		bit = ffs32(irqh);
 	}
-
 }
 
 void *

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Fri Dec 26 17:43:32 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Fri Dec 26 18:06:52 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
make interrupt names part of the handler struct so event counters will show
up correctly
also reshuffle debug code a bit


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:07:33 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
use defflag-ed debug options


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.2 src/sys/arch/evbmips/ingenic/clock.c:1.3
--- src/sys/arch/evbmips/ingenic/clock.c:1.2	Sat Dec  6 14:24:58 2014
+++ src/sys/arch/evbmips/ingenic/clock.c	Tue Dec 23 15:07:33 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.2 2014/12/06 14:24:58 macallan Exp $ */
+/*	$NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.2 2014/12/06 14:24:58 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $);
 
 #include sys/param.h
 #include sys/cpu.h
@@ -38,6 +38,8 @@ __KERNEL_RCSID(0, $NetBSD: clock.c,v 1.
 
 #include mips/ingenic/ingenic_regs.h
 
+#include opt_ingenic.h
+
 extern void ingenic_puts(const char *);
 
 void ingenic_clockintr(uint32_t);
@@ -103,9 +105,13 @@ cpu_initclocks(void)
 	writereg(JZ_TC_TFCR, TFR_FFLAG5);
 	writereg(JZ_TC_TESR, TESR_TCST5);	/* enable timer 5 */
 #endif
+
+#ifdef INGENIC_CLOCK_DEBUG
 	printf(INTC %08x %08x\n, readreg(JZ_ICSR0), readreg(JZ_ICSR1));
 	writereg(JZ_ICMCR0, 0x0c00); /* TCU2, OST */
+#endif
 	spl0();
+#ifdef INGENIC_CLOCK_DEBUG
 	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
 	printf(TMR: %08x\n, readreg(JZ_TC_TMR));
 	printf(cnt5: %08x\n, readreg(JZ_TC_TCNT(5)));
@@ -125,6 +131,7 @@ cpu_initclocks(void)
 	
 	printf(INTC %08x %08x\n, readreg(JZ_ICSR0), readreg(JZ_ICSR1));
 	delay(300);
+#endif
 }
 
 /* shamelessly stolen from mips3_clock.c */
@@ -176,8 +183,9 @@ setstatclockrate(int r)
 	/* we could just use another timer channel here */
 }
 
+#ifdef INGENIC_CLOCK_DEBUG
 int cnt = 99;
-
+#endif
 
 void
 ingenic_clockintr(uint32_t id)
@@ -208,11 +216,12 @@ ingenic_clockintr(uint32_t id)
 		curcpu()-ci_ev_count_compare_missed.ev_count++;
 	}
 
+#ifdef INGENIC_CLOCK_DEBUG
 	cnt++;
 	if (cnt == 100) {
 		cnt = 0;
 		ingenic_puts(+);
 	}
-
+#endif
 	hardclock(cf);
 }

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:08:26 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
preliminary support for the interrupt controller
didn't get much testing yet


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.1 src/sys/arch/evbmips/ingenic/intr.c:1.2
--- src/sys/arch/evbmips/ingenic/intr.c:1.1	Sat Dec  6 14:26:40 2014
+++ src/sys/arch/evbmips/ingenic/intr.c	Tue Dec 23 15:08:25 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.2 2014/12/23 15:08:25 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.2 2014/12/23 15:08:25 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -37,12 +37,15 @@ __KERNEL_RCSID(0, $NetBSD: intr.c,v 1.1
 #include sys/kernel.h
 #include sys/systm.h
 #include sys/timetc.h
+#include sys/bitops.h
 
 #include mips/locore.h
 #include machine/intr.h
 
 #include mips/ingenic/ingenic_regs.h
 
+#include opt_ingenic.h
+
 extern void ingenic_clockintr(uint32_t);
 extern void ingenic_puts(const char *);
 
@@ -74,19 +77,43 @@ static const struct ipl_sr_map ingenic_i
 },
 };
 
-//#define INGENIC_DEBUG
+#define NINTR 64
+
+/* some timer channels share interrupts, couldn't find any others */
+struct intrhand {
+	struct evcnt ih_count;
+	int (*ih_func)(void *);
+	void *ih_arg;
+	int ih_ipl;
+};
+
+struct intrhand intrs[NINTR];
+
+void ingenic_irq(int);
+
 void
 evbmips_intr_init(void)
 {
 	uint32_t reg;
+	int i;
+	char irqstr[8];
 
 	ipl_sr_map = ingenic_ipl_sr_map;
 
+	/* zero all handlers */
+	for (i = 0; i  NINTR; i++) {
+		intrs[i].ih_func = NULL;
+		intrs[i].ih_arg = NULL;
+		snprintf(irqstr, sizeof(irqstr), irq %d, i);
+		evcnt_attach_dynamic(intrs[i].ih_count, EVCNT_TYPE_INTR,
+		NULL, PIC, irqstr);
+	}
+
 	/* mask all peripheral IRQs */
 	writereg(JZ_ICMR0, 0x);
 	writereg(JZ_ICMR1, 0x);
 
-	/* allow mailbox and peripheral interrupts to core 0 only */
+	/* allow peripheral interrupts to core 0 only */
 	reg = MFC0(12, 4);	/* reset entry and interrupts */
 	reg = 0x;
 	reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M;
@@ -100,7 +127,8 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 #ifdef INGENIC_DEBUG
 	char buffer[256];
 	
-	snprintf(buffer, 256, pending: %08x CR %08x\n, ipending, MFC0(MIPS_COP_0_CAUSE, 0));
+	snprintf(buffer, 256, pending: %08x CR %08x\n, ipending,
+	MFC0(MIPS_COP_0_CAUSE, 0));
 	ingenic_puts(buffer);
 #endif
 	/* see which core we're on */
@@ -124,7 +152,8 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 			if (reg  CS_MIRQ0_P) {
 	
 #ifdef INGENIC_DEBUG
-snprintf(buffer, 256, IPI for core 0, msg %08x\n,
+snprintf(buffer, 256,
+IPI for core 0, msg %08x\n,
 MFC0(CP0_CORE_MBOX, 0));
 ingenic_puts(buffer);
 #endif
@@ -135,7 +164,8 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		} else if (id == 1) {
 			if (reg  CS_MIRQ1_P) {
 #ifdef INGENIC_DEBUG
-snprintf(buffer, 256, IPI for core 1, msg %08x\n,
+snprintf(buffer, 256,
+IPI for core 1, msg %08x\n,
 MFC0(CP0_CORE_MBOX, 1));
 ingenic_puts(buffer);
 #endif
@@ -163,8 +193,111 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		 * and IPIs. If that doesn't work we'll have to send an IPI to
 		 * core1 for each timer tick.  
 		 */
-		if (readreg(JZ_ICPR0)  0x0800)
+		if (readreg(JZ_ICPR0)  0x0800) {
 			ingenic_clockintr(id);
+		}
+		ingenic_irq(ipl);
 		KASSERT(id == 0);
 	}
 }
+
+void
+ingenic_irq(int ipl)
+{
+	uint32_t irql, irqh, mask;
+	int bit, idx;
+
+	irql = readreg(JZ_ICPR0);
+	bit = ffs32(irql);
+	while (bit != 0) {
+		idx = bit - 1;
+		mask = 1  idx;
+		if (intrs[idx].ih_func != NULL) {
+			if (intrs[idx].ih_ipl == IPL_VM)
+KERNEL_LOCK(1, NULL);
+			intrs[idx].ih_func(intrs[idx].ih_arg);	
+			if (intrs[idx].ih_ipl == IPL_VM)
+KERNEL_UNLOCK_ONE(NULL);
+			intrs[idx].ih_count.ev_count++;
+		} else {
+			/* spurious interrupt, maks it */
+			writereg(JZ_ICMSR0, mask);
+		}		
+		irql = ~mask;
+		bit = ffs32(irql);
+	}
+
+	irqh = readreg(JZ_ICPR1);
+	bit = ffs32(irqh);
+	while (bit != 0) {
+		idx = bit - 1;
+		mask = 1  idx;
+		idx += 32;
+		if (intrs[idx].ih_func != NULL) {
+			if (intrs[idx].ih_ipl == IPL_VM)
+KERNEL_LOCK(1, NULL);
+			intrs[idx].ih_func(intrs[idx].ih_arg);	
+			if (intrs[idx].ih_ipl == IPL_VM)
+KERNEL_UNLOCK_ONE(NULL);
+			intrs[idx].ih_count.ev_count++;
+		} else {
+			/* spurious interrupt, maks it */
+			writereg(JZ_ICMSR1, mask);
+		}		
+		irqh = ~mask;
+		bit = ffs32(irqh);
+	}
+
+}
+
+void *
+evbmips_intr_establish(int irq, 

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:09:13 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c mainbus.c

Log Message:
use defflag-ed debug options


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/machdep.c \
src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.2 src/sys/arch/evbmips/ingenic/machdep.c:1.3
--- src/sys/arch/evbmips/ingenic/machdep.c:1.2	Sat Dec  6 14:30:11 2014
+++ src/sys/arch/evbmips/ingenic/machdep.c	Tue Dec 23 15:09:13 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.2 2014/12/06 14:30:11 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.3 2014/12/23 15:09:13 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.2 2014/12/06 14:30:11 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.3 2014/12/23 15:09:13 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -62,6 +62,8 @@ __KERNEL_RCSID(0, $NetBSD: machdep.c,v 
 #include mips/ingenic/ingenic_regs.h
 #include mips/ingenic/ingenic_var.h
 
+#include opt_ingenic.h
+
 /* Maps for VM objects. */
 struct vm_map *phys_map = NULL;
 
Index: src/sys/arch/evbmips/ingenic/mainbus.c
diff -u src/sys/arch/evbmips/ingenic/mainbus.c:1.2 src/sys/arch/evbmips/ingenic/mainbus.c:1.3
--- src/sys/arch/evbmips/ingenic/mainbus.c:1.2	Sat Dec  6 14:30:11 2014
+++ src/sys/arch/evbmips/ingenic/mainbus.c	Tue Dec 23 15:09:13 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: mainbus.c,v 1.2 2014/12/06 14:30:11 macallan Exp $ */
+/*	$NetBSD: mainbus.c,v 1.3 2014/12/23 15:09:13 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
  
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mainbus.c,v 1.2 2014/12/06 14:30:11 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: mainbus.c,v 1.3 2014/12/23 15:09:13 macallan Exp $);
 
 #include sys/param.h
 #include sys/systm.h
@@ -38,6 +38,8 @@ __KERNEL_RCSID(0, $NetBSD: mainbus.c,v 
 
 #include mips/ingenic/ingenic_regs.h
 
+#include opt_ingenic.h
+
 #include locators.h
 
 static int	mainbus_match(device_t, cfdata_t, void *);

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 16:17:39 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
use separate debugging flag for interrupts


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u src/sys/arch/evbmips/ingenic/intr.c:1.2 src/sys/arch/evbmips/ingenic/intr.c:1.3
--- src/sys/arch/evbmips/ingenic/intr.c:1.2	Tue Dec 23 15:08:25 2014
+++ src/sys/arch/evbmips/ingenic/intr.c	Tue Dec 23 16:17:39 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: intr.c,v 1.2 2014/12/23 15:08:25 macallan Exp $ */
+/*	$NetBSD: intr.c,v 1.3 2014/12/23 16:17:39 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.2 2014/12/23 15:08:25 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.3 2014/12/23 16:17:39 macallan Exp $);
 
 #define __INTR_PRIVATE
 
@@ -124,7 +124,7 @@ void
 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
 {
 	uint32_t id;
-#ifdef INGENIC_DEBUG
+#ifdef INGENIC_INTR_DEBUG
 	char buffer[256];
 	
 	snprintf(buffer, 256, pending: %08x CR %08x\n, ipending,
@@ -151,7 +151,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 		if (id == 0) {
 			if (reg  CS_MIRQ0_P) {
 	
-#ifdef INGENIC_DEBUG
+#ifdef INGENIC_INTR_DEBUG
 snprintf(buffer, 256,
 IPI for core 0, msg %08x\n,
 MFC0(CP0_CORE_MBOX, 0));
@@ -163,7 +163,7 @@ evbmips_iointr(int ipl, vaddr_t pc, uint
 			}
 		} else if (id == 1) {
 			if (reg  CS_MIRQ1_P) {
-#ifdef INGENIC_DEBUG
+#ifdef INGENIC_INTR_DEBUG
 snprintf(buffer, 256,
 IPI for core 1, msg %08x\n,
 MFC0(CP0_CORE_MBOX, 1));
@@ -206,8 +206,17 @@ ingenic_irq(int ipl)
 {
 	uint32_t irql, irqh, mask;
 	int bit, idx;
+#ifdef INGENIC_INTR_DEBUG
+	char buffer[16];
+#endif
 
 	irql = readreg(JZ_ICPR0);
+#ifdef INGENIC_INTR_DEBUG
+	if (irql != 0) {
+		snprintf(buffer, 16,  il%08x, irql);
+		ingenic_puts(buffer);
+	}
+#endif
 	bit = ffs32(irql);
 	while (bit != 0) {
 		idx = bit - 1;
@@ -220,7 +229,7 @@ ingenic_irq(int ipl)
 KERNEL_UNLOCK_ONE(NULL);
 			intrs[idx].ih_count.ev_count++;
 		} else {
-			/* spurious interrupt, maks it */
+			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR0, mask);
 		}		
 		irql = ~mask;
@@ -228,6 +237,12 @@ ingenic_irq(int ipl)
 	}
 
 	irqh = readreg(JZ_ICPR1);
+#ifdef INGENIC_INTR_DEBUG
+	if (irqh != 0) {
+		snprintf(buffer, 16,  ih%08x, irqh);
+		ingenic_puts(buffer);
+	}
+#endif
 	bit = ffs32(irqh);
 	while (bit != 0) {
 		idx = bit - 1;
@@ -241,7 +256,7 @@ ingenic_irq(int ipl)
 KERNEL_UNLOCK_ONE(NULL);
 			intrs[idx].ih_count.ev_count++;
 		} else {
-			/* spurious interrupt, maks it */
+			/* spurious interrupt, mask it */
 			writereg(JZ_ICMSR1, mask);
 		}		
 		irqh = ~mask;

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:07:33 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
use defflag-ed debug options


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:08:26 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
preliminary support for the interrupt controller
didn't get much testing yet


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 15:09:13 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c mainbus.c

Log Message:
use defflag-ed debug options


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/machdep.c \
src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Tue Dec 23 16:17:39 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
use separate debugging flag for interrupts


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:24:58 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
add timecounter, timer interrupt and plenty of debugging goop
very much work in progress


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.1 src/sys/arch/evbmips/ingenic/clock.c:1.2
--- src/sys/arch/evbmips/ingenic/clock.c:1.1	Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/clock.c	Sat Dec  6 14:24:58 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: clock.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+/*	$NetBSD: clock.c,v 1.2 2014/12/06 14:24:58 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,20 +27,104 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.1 2014/11/22 15:17:02 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: clock.c,v 1.2 2014/12/06 14:24:58 macallan Exp $);
 
 #include sys/param.h
 #include sys/cpu.h
 #include sys/device.h
 #include sys/kernel.h
 #include sys/systm.h
+#include sys/timetc.h
+
 #include mips/ingenic/ingenic_regs.h
 
+extern void ingenic_puts(const char *);
+
+void ingenic_clockintr(uint32_t);
+
+struct clockframe cf;
+
+static u_int
+ingenic_count_read(struct timecounter *tc)
+{
+	return readreg(JZ_OST_CNT_LO);
+}
+
 void
 cpu_initclocks(void)
 {
+	struct cpu_info * const ci = curcpu();
+	uint32_t cnt;
 
-	/* timecounter setup and such */
+	static struct timecounter tc =  {
+		ingenic_count_read,		/* get_timecount */
+		0,/* no poll_pps */
+		~0u,/* counter_mask */
+		1200,			/* frequency */
+		Ingenic OS timer,		/* name */
+		100,/* quality */
+	};
+
+	curcpu()-ci_cctr_freq = tc.tc_frequency;
+
+	tc_init(tc);
+
+	printf(starting timer interrupt...\n);
+	/* start the timer interrupt */
+	cnt = readreg(JZ_OST_CNT_LO);
+	ci-ci_next_cp0_clk_intr = cnt + ci-ci_cycles_per_hz;
+	writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
+	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+	/*
+	 * XXX
+	 * We can use OST or one of the regular timers to generate the 100hz
+	 * interrupt. OST interrupts need to be rescheduled every time and by
+	 * only one core, the regular timer can be programmed to fire every
+	 * 10ms without rescheduling and we'd still use the OST as time base.
+	 * OST is supposed to fire on INT2 although I haven't been able to get
+	 * that to work yet ( all I get is INT0 which is for hardware interrupts
+	 * in general )
+	 * So if we can get OST to fire on INT2 we can just block INT0 on core1
+	 * and have a timer interrupt on both cores, if not the regular timer 
+	 * would be more convenient but we'd have to shoot an IPI to core1 on
+	 * every tick.
+	 * For now, use OST and hope we'll figure out how to make it fire on
+	 * INT2.
+	 */
+#if 1
+	writereg(JZ_TC_TMCR, TFR_OSTFLAG);
+#else
+	writereg(JZ_TC_TECR, TESR_TCST5);	/* disable timer 5 */
+	writereg(JZ_TC_TCNT(5), 0);
+	writereg(JZ_TC_TDFR(5), 3);	/* 10ms at 48MHz / 16 */
+	writereg(JZ_TC_TDHR(5), 6);	/* not reached */
+	writereg(JZ_TC_TCSR(5), TCSR_EXT_EN| TCSR_DIV_16);
+	writereg(JZ_TC_TMCR, TFR_FFLAG5);
+	writereg(JZ_TC_TFCR, TFR_FFLAG5);
+	writereg(JZ_TC_TESR, TESR_TCST5);	/* enable timer 5 */
+#endif
+	printf(INTC %08x %08x\n, readreg(JZ_ICSR0), readreg(JZ_ICSR1));
+	writereg(JZ_ICMCR0, 0x0c00); /* TCU2, OST */
+	spl0();
+	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
+	printf(TMR: %08x\n, readreg(JZ_TC_TMR));
+	printf(cnt5: %08x\n, readreg(JZ_TC_TCNT(5)));
+	printf(CR: %08x\n, MFC0(MIPS_COP_0_CAUSE, 0));
+	printf(SR: %08x\n, MFC0(MIPS_COP_0_STATUS, 0));
+	delay(10);
+	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
+	printf(TMR: %08x\n, readreg(JZ_TC_TMR));
+	printf(cnt5: %08x\n, readreg(JZ_TC_TCNT(5)));
+	printf(CR: %08x\n, MFC0(MIPS_COP_0_CAUSE, 0));
+	printf(SR: %08x\n, MFC0(MIPS_COP_0_STATUS, 0));
+	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
+	printf(TMR: %08x\n, readreg(JZ_TC_TMR));
+	printf(cnt5: %08x\n, readreg(JZ_TC_TCNT(5)));
+	printf(CR: %08x\n, MFC0(MIPS_COP_0_CAUSE, 0));
+	printf(SR: %08x\n, MFC0(MIPS_COP_0_STATUS, 0));
+	
+	printf(INTC %08x %08x\n, readreg(JZ_ICSR0), readreg(JZ_ICSR1));
+	delay(300);
 }
 
 /* shamelessly stolen from mips3_clock.c */
@@ -89,5 +173,46 @@ delay(int n)
 void
 setstatclockrate(int r)
 {
-	/* nothing to see here */
+	/* we could just use another timer channel here */
+}
+
+int cnt = 99;
+
+
+void
+ingenic_clockintr(uint32_t id)
+{
+	struct cpu_info * const ci = curcpu();
+	uint32_t new_cnt;
+
+	ci-ci_ev_count_compare.ev_count++;
+
+	/* clear flags */
+	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+
+	KASSERT((ci-ci_cycles_per_hz  ~(0x)) == 0);
+	ci-ci_next_cp0_clk_intr += (uint32_t)(ci-ci_cycles_per_hz  0x);
+	writereg(JZ_OST_DATA, ci-ci_next_cp0_clk_intr);
+
+	/* Check for lost clock 

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:26:40 UTC 2014

Added Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
timer interrupt and IPIs


To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Added files:

Index: src/sys/arch/evbmips/ingenic/intr.c
diff -u /dev/null src/sys/arch/evbmips/ingenic/intr.c:1.1
--- /dev/null	Sat Dec  6 14:26:40 2014
+++ src/sys/arch/evbmips/ingenic/intr.c	Sat Dec  6 14:26:40 2014
@@ -0,0 +1,170 @@
+/*	$NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__KERNEL_RCSID(0, $NetBSD: intr.c,v 1.1 2014/12/06 14:26:40 macallan Exp $);
+
+#define __INTR_PRIVATE
+
+#include sys/param.h
+#include sys/cpu.h
+#include sys/device.h
+#include sys/kernel.h
+#include sys/systm.h
+#include sys/timetc.h
+
+#include mips/locore.h
+#include machine/intr.h
+
+#include mips/ingenic/ingenic_regs.h
+
+extern void ingenic_clockintr(uint32_t);
+extern void ingenic_puts(const char *);
+
+/*
+ * This is a mask of bits to clear in the SR when we go to a
+ * given hardware interrupt priority level.
+ */
+static const struct ipl_sr_map ingenic_ipl_sr_map = {
+.sr_bits = {
+	[IPL_NONE] =		0,
+	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
+	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
+	[IPL_VM] =
+	MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+	MIPS_INT_MASK_0 |
+	MIPS_INT_MASK_3 |
+	MIPS_INT_MASK_4 |
+	MIPS_INT_MASK_5,
+	[IPL_SCHED] =
+	MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+	MIPS_INT_MASK_0 |
+	MIPS_INT_MASK_1 |
+	MIPS_INT_MASK_2 |
+	MIPS_INT_MASK_3 |
+	MIPS_INT_MASK_4 |
+	MIPS_INT_MASK_5,
+	[IPL_DDB] =		MIPS_INT_MASK,
+	[IPL_HIGH] =MIPS_INT_MASK,
+},
+};
+
+//#define INGENIC_DEBUG
+void
+evbmips_intr_init(void)
+{
+	uint32_t reg;
+
+	ipl_sr_map = ingenic_ipl_sr_map;
+
+	/* mask all peripheral IRQs */
+	writereg(JZ_ICMR0, 0x);
+	writereg(JZ_ICMR1, 0x);
+
+	/* allow mailbox and peripheral interrupts to core 0 only */
+	reg = MFC0(12, 4);	/* reset entry and interrupts */
+	reg = 0x;
+	reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M;
+	MTC0(reg, 12, 4);
+}
+
+void
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+{
+	uint32_t id;
+#ifdef INGENIC_DEBUG
+	char buffer[256];
+	
+	snprintf(buffer, 256, pending: %08x CR %08x\n, ipending, MFC0(MIPS_COP_0_CAUSE, 0));
+	ingenic_puts(buffer);
+#endif
+	/* see which core we're on */
+	id = MFC0(15, 1)  7;
+
+	/*
+	 * XXX
+	 * the manual counts the softint bits as INT0 and INT1, out headers
+	 * don't so everything here looks off by two
+	 */
+	if (ipending  MIPS_INT_MASK_1) {
+		/*
+		 * this is a mailbox interrupt / IPI
+		 * for now just print the message and clear it
+		 */
+		uint32_t reg;
+
+		/* read pending IPIs */
+		reg = MFC0(12, 3);
+		if (id == 0) {
+			if (reg  CS_MIRQ0_P) {
+	
+#ifdef INGENIC_DEBUG
+snprintf(buffer, 256, IPI for core 0, msg %08x\n,
+MFC0(CP0_CORE_MBOX, 0));
+ingenic_puts(buffer);
+#endif
+reg = (~CS_MIRQ0_P);
+/* clear it */
+MTC0(reg, 12, 3);
+			}
+		} else if (id == 1) {
+			if (reg  CS_MIRQ1_P) {
+#ifdef INGENIC_DEBUG
+snprintf(buffer, 256, IPI for core 1, msg %08x\n,
+MFC0(CP0_CORE_MBOX, 1));
+ingenic_puts(buffer);
+#endif
+reg = ( 7 - CS_MIRQ1_P);
+/* clear it */
+MTC0(reg, 12, 3);
+			}
+		}
+	}
+	if (ipending  MIPS_INT_MASK_2) {
+		/* this is a 

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:30:11 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c mainbus.c

Log Message:
apbus attachment goop, move interrupt stuff to intr.c


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/machdep.c \
src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u src/sys/arch/evbmips/ingenic/machdep.c:1.1 src/sys/arch/evbmips/ingenic/machdep.c:1.2
--- src/sys/arch/evbmips/ingenic/machdep.c:1.1	Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/machdep.c	Sat Dec  6 14:30:11 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+/*	$NetBSD: machdep.c,v 1.2 2014/12/06 14:30:11 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.1 2014/11/22 15:17:02 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: machdep.c,v 1.2 2014/12/06 14:30:11 macallan Exp $);
 
 #include opt_ddb.h
 #include opt_kgdb.h
@@ -42,13 +42,12 @@ __KERNEL_RCSID(0, $NetBSD: machdep.c,v 
 #include sys/mount.h
 #include sys/reboot.h
 #include sys/cpu.h
+#include sys/bus.h
 
 #include uvm/uvm_extern.h
 
 #include dev/cons.h
 
-#include mips/ingenic/ingenic_regs.h
-
 #include ksyms.h
 
 #if NKSYMS || defined(DDB) || defined(MODULAR)
@@ -60,6 +59,9 @@ __KERNEL_RCSID(0, $NetBSD: machdep.c,v 
 #include mips/locore.h
 #include mips/cpuregs.h
 
+#include mips/ingenic/ingenic_regs.h
+#include mips/ingenic/ingenic_var.h
+
 /* Maps for VM objects. */
 struct vm_map *phys_map = NULL;
 
@@ -178,6 +180,7 @@ mach_init(void)
 	 */
 	mips_init_lwp0_uarea();
 
+	apbus_init();
 	/*
 	 * Initialize debuggers, and break into them, if appropriate.
 	 */
@@ -278,7 +281,7 @@ cpu_reboot(int howto, char *bootstr)
 	if (boothowto  RB_DUMP)
 		dumpsys();
 
- haltsys:
+haltsys:
 	/* Run any shutdown hooks. */
 	doshutdownhooks();
 
@@ -328,19 +331,3 @@ ingenic_reset(void)
 	writereg(JZ_WDOG_TCSR, TCSR_RTC_EN | TCSR_DIV_256);
 	writereg(JZ_WDOG_TCER, TCER_ENABLE);	/* fire! */	
 }
-
-void
-evbmips_intr_init(void)
-{
-#if notyet
-	(*platformsw-apsw_intr_init)();
-#endif
-}
-
-void
-evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
-{
-#if notyet
-	(*platformsw-apsw_intrsw-aisw_iointr)(ipl, pc, ipending);
-#endif
-}
Index: src/sys/arch/evbmips/ingenic/mainbus.c
diff -u src/sys/arch/evbmips/ingenic/mainbus.c:1.1 src/sys/arch/evbmips/ingenic/mainbus.c:1.2
--- src/sys/arch/evbmips/ingenic/mainbus.c:1.1	Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/mainbus.c	Sat Dec  6 14:30:11 2014
@@ -1,4 +1,4 @@
-/*	$NetBSD: mainbus.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+/*	$NetBSD: mainbus.c,v 1.2 2014/12/06 14:30:11 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
  
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mainbus.c,v 1.1 2014/11/22 15:17:02 macallan Exp $);
+__KERNEL_RCSID(0, $NetBSD: mainbus.c,v 1.2 2014/12/06 14:30:11 macallan Exp $);
 
 #include sys/param.h
 #include sys/systm.h
@@ -36,6 +36,8 @@ __KERNEL_RCSID(0, $NetBSD: mainbus.c,v 
 #include mips/cache.h
 #include mips/cpuregs.h
 
+#include mips/ingenic/ingenic_regs.h
+
 #include locators.h
 
 static int	mainbus_match(device_t, cfdata_t, void *);
@@ -55,6 +57,7 @@ struct mainbusdev {
 struct mainbusdev mainbusdevs[] = {
 	{ cpu,	},
 	{ com,	},
+	{ apbus,	},
 	{ NULL,		}
 };
 
@@ -80,6 +83,15 @@ mainbus_attach(device_t parent, device_t
 		struct mainbusdev ma = *md;
 		config_found_ia(self, mainbus, ma, mainbus_print);
 	}
+
+#ifdef INGENIC_DEBUG
+	printf(TFR: %08x\n, readreg(JZ_TC_TFR));
+	printf(TMR: %08x\n, readreg(JZ_TC_TMR));
+
+	/* send ourselves an IPI */
+	MTC0(0x12345678, CP0_CORE_MBOX, 0);
+	delay(1000);
+#endif
 }
 
 static int

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:24:58 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: clock.c

Log Message:
add timecounter, timer interrupt and plenty of debugging goop
very much work in progress


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/clock.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:26:40 UTC 2014

Added Files:
src/sys/arch/evbmips/ingenic: intr.c

Log Message:
timer interrupt and IPIs


To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/ingenic/intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: src/sys/arch/evbmips/ingenic

[Michael Lorenz]

Module Name:src
Committed By:   macallan
Date:   Sat Dec  6 14:30:11 UTC 2014

Modified Files:
src/sys/arch/evbmips/ingenic: machdep.c mainbus.c

Log Message:
apbus attachment goop, move interrupt stuff to intr.c


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/machdep.c \
src/sys/arch/evbmips/ingenic/mainbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.