Hi All,
Here is a driver for Maxim 3110 SPI-UART device, please help to review.
It has been validated with Designware SPI controller (drivers/spi: dw_spi.c
dw_spi_pci.c). It supports polling and IRQ mode, supports batch read, and
provides a console.
change log:
since v4:
* Add
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On Tuesday 02 March 2010, Feng Tang wrote:
+ * 3. This driver doesn't support work with a spi cotnroller in DMA mode,
As Grant said: That's a bug ... one that will randomly
kick in based on whether the underlying SPI controller driver
happens to use DMA for a given transaction.
On Wed, 3 Mar 2010 12:51:58 +0800
David Brownell davi...@pacbell.net wrote:
On Tuesday 02 March 2010, Feng Tang wrote:
+ * 3. This driver doesn't support work with a spi cotnroller in
DMA mode,
As Grant said: That's a bug ... one that will randomly
kick in based on whether the
On Tuesday 02 March 2010, Feng Tang wrote:
On Wed, 3 Mar 2010 12:51:58 +0800
David Brownell davi...@pacbell.net wrote:
On Tuesday 02 March 2010, Feng Tang wrote:
+ * 3. This driver doesn't support work with a spi cotnroller in
DMA mode,
As Grant said: That's a bug ... one that
Here comes another idea, can we add a capability flag in struct
spi_master indicating the master supporting poll or dma or both.
Also we add similar bits in struct spi_transfer indicating the this
transfer wants to be handled in poll or dma mode.
Let's not do either of those.
On Tue, Mar 2, 2010 at 7:57 PM, Feng Tang feng.t...@intel.com wrote:
Hi All,
Here is a driver for Maxim 3110 SPI-UART device, please help to review.
It has been validated with Designware SPI controller (drivers/spi: dw_spi.c
dw_spi_pci.c). It supports polling and IRQ mode, supports batch
On Tuesday 02 March 2010, Feng Tang wrote:
Here comes another idea, can we add a capability flag in struct
spi_master indicating the master supporting poll or dma or both.
Also we add similar bits in struct spi_transfer indicating the this
transfer wants to be handled in poll or dma
