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Re: [PATCH 1/3] spi/s3c64xx: Log error interrupts

Hi Mark, Some minor doubts/ questions. On 1/21/12, Mark Brown wrote: > Although the hardware supports interrupts we're not currently using them > at all since for small transfers the overhead is greater than that for > busy waiting and for large transfers we have interrupts from the DMA. > This m

Re: [PATCH v2 RESEND] SPI: add CSR SiRFprimaII SPI controller driver

ping... 2011/12/14 Barry Song : > From: Zhiwu Song > > CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features: > * Master and slave modes > * 8-/12-/16-/32-bit data unit > * 256 bytes receive data FIFO and 256 bytes transmit data FIFO > * Multi-unit frame > * Configurable SPI_EN (chip select pin)