Grant == Grant Likely grant.lik...@secretlab.ca writes:
Hi,
Since at least some SPI master drivers queue messages from the
attached devices, the mux can only send 1 message at a time from its
own queue to the master, because otherwise there would not be a
guarantee that the mux settings
(http://obfm41.com/unvvihqw3xsodiyjhd/index0.html)
(http://obfm41.com/e5va0hw035tj0hdj3s/index1.html)
(http://obfm41.com/k4vkkhsq3ukoersxil/index2.html)
(http://obfm41.com/vrvifhpi3y4jwmlxay/index3.html)
--
On Wed, 13 Feb 2013 12:03:46 -0800, Girish K S girishks2...@gmail.com wrote:
Currently the drivers supports only the GPIO based i/o pins.
But there are Exynos SoC's that use the same controller with
dedicated i/o pins.
This patch provides provision to support gpio/dedicated pins.
The
On Fri, 15 Feb 2013 16:52:20 +0100, Andreas Larsson andr...@gaisler.com wrote:
Changes since v3:
- Patches 1-7: Added Acked-by: Anton Vorontsov an...@enomsg.org
- Patch 1: Small style tweak lining up function arguments properly
- Patch 7: Changed a style issue with two variables declared on
On Wed, 20 Feb 2013 08:51:48 +0100, Nicolas Ferre nicolas.fe...@atmel.com
wrote:
On 02/19/2013 10:44 PM, Joachim Eastwood :
atmel_spi_transfer() would check speed_hz and fail if
the speed was changed in the transfer. After commit
spi: make sure all transfer has proper speed set
this
On Wed, 27 Feb 2013 11:32:39 +, Manjunathappa, Prakash
prakash...@ti.com wrote:
On Wed, Feb 27, 2013 at 14:09:57, Nori, Sekhar wrote:
On 2/25/2013 4:14 PM, Manjunathappa, Prakash wrote:
Patch enables support for m25p80 SPI flash support on
da850-EVM.
Testing information:
On Fri, 22 Feb 2013 17:09:18 +0900, Boojin Kim boojin@samsung.com wrote:
This patch adds dma maxburst size initialization.
The maxburst should be set by MODE_CFGn.DMA_TYPE,
because the pl330 dma driver supports burst mode.
Signed-off-by: Hyeonkook Kim hk619@samsung.com
Applied,
On Wed, 13 Feb 2013 14:23:24 +0100, Andreas Larsson andr...@gaisler.com wrote:
This makes sure that an error is returned on an incorrectly formed
cs-gpios property, but reports success when the cs-gpios property is
well formed or missing.
When holes in the cs-gpios property phandle list is
On Fri, 22 Feb 2013 17:09:18 +0900, Boojin Kim boojin@samsung.com wrote:
This patch adds dma maxburst size initialization.
The maxburst should be set by MODE_CFGn.DMA_TYPE,
because the pl330 dma driver supports burst mode.
Signed-off-by: Hyeonkook Kim hk619@samsung.com
Hello
On Wed, 13 Feb 2013 14:20:25 +0100, Andreas Larsson andr...@gaisler.com wrote:
The return value from of_get_named_gpio is -ENOENT when the given index
matches a hole in the cs-gpios property phandle list. However, the
default value of cs_gpio in struct spi_device and entries of cs_gpios in
On Wed, 27 Feb 2013 23:25:41 +0800, Shawn Guo shawn@linaro.org wrote:
With the generic DMA device tree helper supported by mxs-dma driver,
client devices only need to call dma_request_slave_channel() for
requesting a DMA channel from dmaengine.
Since mxs is a DT only platform now, along
On Tue, 26 Feb 2013 14:47:54 +0800, Wenyou Yang wenyou.y...@atmel.com wrote:
if the spi property cs-gpios is set as below:
cs-gpios = 0, pioC 11 0, 0, 0;
the master-num_chipselect will wrongly be set to 0,
and the spi fail to probe.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
On 14:47 Tue 26 Feb , Wenyou Yang wrote:
if the spi property cs-gpios is set as below:
cs-gpios = 0, pioC 11 0, 0, 0;
the master-num_chipselect will wrongly be set to 0,
and the spi fail to probe.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
Cc:
On Fri, 22 Feb 2013 17:09:18 +0900, Boojin Kim boojin@samsung.com wrote:
This patch adds dma maxburst size initialization.
The maxburst should be set by MODE_CFGn.DMA_TYPE,
because the pl330 dma driver supports burst mode.
Signed-off-by: Hyeonkook Kim hk619@samsung.com
Acked-by:
On Fri, 15 Feb 2013 15:03:50 -0700, Stephen Warren swar...@wwwdotorg.org
wrote:
From: Stephen Warren swar...@nvidia.com
The platform data header is no longer used. Delete it.
Signed-off-by: Stephen Warren swar...@nvidia.com
I like the diffstat for this series. Applied!
Thanks,
g.
On Fri, 22 Feb 2013 19:59:11 +0530, Manish Badarkhe badarkhe.man...@gmail.com
wrote:
On Fri, Feb 22, 2013 at 6:07 PM, Laxman Dewangan ldewan...@nvidia.com wrote:
Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller
is different than the older SoCs SPI controller in internal
Hi Mark,
On Fri, Feb 22, 2013 at 11:32 PM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
On Fri, Feb 22, 2013 at 07:59:11PM +0530, Manish Badarkhe wrote:
On Fri, Feb 22, 2013 at 6:07 PM, Laxman Dewangan ldewan...@nvidia.com
wrote:
Add SPI driver for NVIDIA's Tegra114 SPI controller.
On 14:47 Tue 26 Feb , Wenyou Yang wrote:
the has_dma_support needed for future use with dmaengine driver.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
Cc: spi-devel-general@lists.sourceforge.net
Cc: linux-ker...@vger.kernel.org
---
drivers/spi/spi-atmel.c | 70
On Sun, Mar 3, 2013 at 4:28 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, 13 Feb 2013 12:03:45 -0800, Girish K S girishks2...@gmail.com wrote:
The 64xx spi driver supports partial polling mode.
Only the last chunk of the transfer length is transferred
or recieved in polling mode.
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