Evadez vous en profitant jusqu'à 70% de réduction
Document sans nom Si ce message ne s'affiche pas correctement, visualisez la
version en ligne. :
http://p5trc.emv2.com/HM?a=ENX7CqmVXCyi8SA9MKJuS-XnGHxKLhAPCvcStGb5lw8W0bBhOG5mpqVsje_HhdA5HlIP
CLUB PRIVE VACANCES.com
Nos offres à ne pas louper
Jusqu'à 70% de réductions
spi-devel-general@lists.sourceforge.net
OK
http://p5trc.emv2.com/HP?a=ENX7CqmVXCyi8SA9MKJuS-XnGHxKLhAPCPcStGb5lw8W0bBhOG5mpqVsje_HhdA5HlIN
ILE MAURICE Ile Maurice
UN CADRE IDYLLIQUE
Hotel Mauritius Resort 5* 1185€ dès 470€ ttc JUSQU'A -60%*
ACCEDER A LA VENTE PRAGUE Prague
LA VILLE AUX CENT CLOCHERS
Hotel Elite 4* 327€ dès 79€ ttc JUSQU'A -75%*
ACCEDER A LA VENTE REUNION Reunion
ENTRE MER ET SAVANE
Hotel Tama 3* 1011€ dès 299€ ttc JUSQU'A -70%*
ACCEDER A LA VENTE LISBONNE Lisbonne
VACANCES SOUS UN AIR BOHEME
VIP Executive Villa Rica Hotel 4* 240€ dès 63€ ttc JUSQU'A -73%*
ACCEDER A LA VENTE
Réductions & Privilèges
pour les membres uniquement
Parrainage
Invitez un ami, recevez 100€ ! (1)
Ventes flash
Jusqu?à -70%* de réduction sur une sélection d?hôtels de rêve
Appli iPhone
Je télécharge l?appli iPhone gratuite
Garantie soleil
Vos vacances ensoleillées ou 150€ remboursés** CLUBPRIVEVACANCES.COM
Fb
G+
La vente de voyages sous la marque Clubprivévacances.com est assurée
par Karavel - 17 rue de l?Echiquier 75010 Paris - SAS au capital de
39.838.060 euros - RCS Paris B 499 668 606 -Immatriculation "Atout
France": IM075110099 - Garant : APS, 15 av Carnot 75017 Paris - RCP :
Hiscox, 19 rue Louis le Grand 75002 Paris.
Nos prix sont affich és en TTC (soit le prix du séjour HT complété des
taxes obligatoires hors taxes de séjour): prix " à partir de" et sous
réserve de disponibilités. Ces tarifs n?incluent pas les frais de
dossier et de dernière minute, ni les suppléments spécifiques
susceptibles de s?appliquer à certaines destinations.
Les prix indiqués correspondent aux tarifs en ligne sur notre site
Internet à la date d?envoi de la présente lettre d?informations
commerciale . Ils peuvent faire l?objet d?une actualisation suivant
l?évolution de nos disponibilités
(*) Taux de réduction maximal, calculé à partir du tarif de référence
sur une sélection de dates et de séjours. Offre soumise à conditions et
valable sous réserve de disponibilité.
(**) La garantie soleil entre dans le cadre des garanties incluses
dans l'assurance Multirisques Premium et vous permet de bénéficier
d'une indemnisation de 150{ par dossier sous forme de "Bon Voyages "
si, pendant plus de la moitié de votre séjour, il pleut au moins 4 h de
temps entre 10h et 17h.
Cette garantie est prise en considération si les informations figurant
sur le site www.wunderground.com :
http://p5trc.emv2.com/HP?a=ENX7CqmVXCyi8SA9MKJuS-XnGHxKLhAPCfcStGb5lw8W0bBhOG5mpqVsje_HhdA5HlIS
concernant le lieu du séjour lui-même permettent de confirmer les
problèmes d'intempéries rencontrés.
(1) Consultez les conditions d'utilisation des bons de réduction sur
le site www.clubprivevacances.com :
http://p5trc.emv2.com/HP?a=ENX7CqmVXCyi8SA9MKJuS-XnGHxKLhAPDvcStGb5lw8W0bBhOG5mpqVsje_HhdA5HlIT
Pour être retiré de nos listes de diffusion, rendez-vous sur cette page :
http://p5trc.emv2.com/HU?a=ENX7CqmVXCyi8SA9MKJuS-XnGHxKLhAPC_cStGb5lw8W0bBhOG5mpqVsje_HhdA5HlIM
--
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://p.sf.net/sfu/appdyn_d2d_mar
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] mxs/spi: Add SPI slave mode operation DT prop
On Wed, Mar 20, 2013 at 4:35 PM, Marek Vasut wrote: >> On Thu, Aug 23, 2012 at 7:42 PM, Marek Vasut >> > + - The DMA has to wait indefinitelly for the arriving data. >> >> Is there a reason that this must be done? I'd guess that after the >> SSP is told to start a transfer in slave mode it waits for the master >> to assert the SSn line and begin the transfer. If the completion >> times out before this happens then it makes sense it wouldn't work. >> But does it still not work if the SPI transfer completes before the >> completion timeout? Or is this necessary because in your application >> there might be a long wait before the master chooses to initiate a >> transfer after you program it on the Linux side? > > The problem is the SPI block in slave mode ignores SS being pulled back up. I've setup a board with a spi-gpio port looped to a spi-mxs port in slave mode so I can test this. I did not need to change the DMA timeout to get it to work. If the master does not send enough within the SSP timeout the slave transaction will timeout. It does not seem to ignore SS, but rather the DMA will not finish until all the requested words are received, no matter how many SS pulses that happens to take. For general purpose slave support it would of course be nice to be able to end the message when the master drops SS, but the SSP either doesn't support this or a different technique is needed. I've found that if PHASE = 0, the SSP expects the SS to be pulsed high between each word (w/ current driver, word == 8 bits). This is slightly alluded to in the imx28 manual, where the PHASE = 0 descriptions in sections 17.5.3 and 17.5.5 contain, "... in the case of continuous back-to-back transmissions, the SSn signal must be pulsed high between each data word[.]" While for the PHASE = 1 descriptions in sections 17.5.4 and 17.5.6 it says, "For continuous back-to-back transfers, the SSn pin is held low between successive data words[.]" One would think this is talking about master mode like the rest of the section, but it seems to only apply to slave mode. In master mode one can easily produce a SPI signal without SS pulsed between each word with either phase setting. Testing with the master TX sending 1 byte per SS asserted period: $ echo abcd1234ABCDwxyz | dd of=/dev/spidev4.0 bs=1 Slave RX receives the first four bytes: $ dd if=/dev/spidev2.0 count=1 bs=4 | hd [ 638.673625] spidev spi2.0: Start POL 0 PHA 0 61 62 63 64 |abcd| Trying with 4 bytes per SS assertion: $ echo abcd1234ABCDwxyz | dd of=/dev/spidev4.0 bs=4 $ dd if=/dev/spidev2.0 count=1 bs=4 | hd 61 31 41 77 |a1Aw| The slave receives the first byte of each SS assertion pulse. If I change the protocol to PHASE=1, then this case works as well and I receive the first four bytes. I didn't need to set POLARITY to 1, just phase. $ dd if=/dev/spidev2.0 count=1 bs=16 | hd [ 261.277000] spidev spi2.0: Start POL 0 PHA 1 $ echo abcd1234ABCDwxyz | dd of=/dev/spidev4.0 bs=4 61 62 63 64 31 32 33 34 41 42 43 44 77 78 79 7a |abcd1234ABCDwxyz| The same thing happens if the bs for the master size is to 1, 2, 8, or 16. Setting it to another values like 3, 5, 32 doesn't work. Maybe the slave ignores extra SS pulses in the middle of a transfer, but will fail to complete the transfer if it doesn't get SS de-asserted at the end as expected? >> another application but was never happy with it. I imagine this is >> why no one has ever created a general spi slave framework for Linux. > > SPI slave is hard because you can not anticipate the amount of data you will > receive. You can not anticipate when you will receive those either. The same can be said for a serial UART or an ethernet MAC, yet those don't seem to be too hard. I think the problem is that these devices usually have things like FIFOs, IRQ trigger levels, pools of buffer descriptors, etc. that are designed to handle this. The design of slave mode in SPI and I2C controllers seems to be more of an afterthought, with none of the features one would except to deal with it. Also, the slave protocol design for things like EEPROMs often have nanosecond scale latencies that are nearly impossible to achieve in a general purpose CPU running a multitasking OS. No one would design a network protocol that requires an ACK packet within 10 ns of receiving a REQ, and expect the CPU to handle that. Yet that can be expected of a SPI EEPROM. However, there are applications where one can predict what the master will do ahead of time and don't have these problems. In my case I know what and when the master will do something and can prime the SSP with a matching slave mode transaction before the master initiates. I know I'm not the first person who has needed to do this on Linux. So maybe it's worthwhile to add a limited slave support system without solving the problem of general purpose slave support.
Vente privée Kickers : jusquà -50%, livraison et retour gratuits
Vente Privée KICKERS : jusqu’à -50% sur plus de 600 modèles pour toute la famille (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2F) FEMME (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fchaussure-femme) HOMME (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fchaussure-homme) ENFANT (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fchaussure-enfant) SACS (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fsacs) PROMOS (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fchaussure-pas-cher-femme) 600 MARQUES (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fchaussure-marque) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) Livraison toujours gratuite (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) sans minimum de commande (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-retour-gratuit) retour gratuit pendant 100 jours (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-retour-gratuit) pas de stress si vous changez d'avis (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-retour-gratuit) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fventes-privees-chaussures) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fventes-privees-chaussures) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-femme) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-homme) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-enfant) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2Fvente-privee-kickers-mars13) Printemps / Été 2010, 2011 et 2012 et Automne/Hiver 2008 , 2009, 2010, 2011 et 2012. Du jeudi 21 mars à minuit au lundi 25 mars à 12h 4 bonnes raisons de choisir Sarenza.com parmi tant d'autres… (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) Livraison offerte sans minimum chez vous ou dans un Relais Kiala (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?eemail=&eurl=http%3A%2F%2Fwww.sarenza.com%2FGaranties-livraison-gratuite) (http://eulerian.sarenza.com/click/sarenza/w8QJGwZp6DPssZVf3FnOXy3.66vC5FzwivnaZiYZrrUpB9Q-/?e
代_开_发_栗,Q:2586801282
致：贵公司负责人 你们好，本公司现有（建筑，广告，服务，运输，商品销售，租赁）等发栗代开。机打，包真，欢迎来电咨询 手机：135 9020 8936 张小兵 Q：2586801282 -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_mar ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[SPAM] Votre carrière dans limmobilier
(http://obfm41.com/14mqk1apslvohwlhby/index0.html) (http://obfm41.com/frmsf1bfsvnjmnsh0l/index1.html) (http://obfm41.com/cnmji1vssmlogedmts/index2.html) (http://obfm41.com/x5ml011ks12j1vym2d/index3.html) (http://obfm41.com/ann0ihxyt2yoihdanl/index4.html) (http://obfm41.com/i5nf0huutnbjriya4y/index5.html) (http://obfm41.com/34nbkh25thuoqml5wd/index6.html) (http://obfm41.com/hrn1fhhxtgzjcrs5zs/index7.html) (http://obfm41.com/m41cug3mssaouql2uy/index8.html) (http://obfm41.com/pr1txgt1sk5jzgs2el/index9.html) (http://obfm41.com/5yt2nzcnafxit11svd/index10.html) (http://obfm41.com/rjmxl1vvymxggcjmkd/index11.html) (http://obfm41.com/tma4c2st4udxnuscig/index12.html) (http://obfm41.com/2ndri55sfddp3k0uag/index13.html) (http://obfm41.com/fuwye324ch24qvv5el/index14.html) (http://obfm41.com/1axg0dikwo2bbezdul/index15.html) (http://obfm41.com/tcwzo3lf1hwnqz35ig/index16.html) (http://obfm41.com/20xmpdronow0b4rdag/index17.html) (http://obfm41.com/cdbjpneoupncswqsky/index18.html) (http://obfm41.com/xqrlox1fj1nm1nfmvy/index19.html) (http://obfm41.com/jledmafdxbgre2cxvl/index20.html) (http://obfm41.com/qgjoglu0zwg150oekl/index21.html) -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_mar ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Votre mutuelle santé en 1 clic à partir de 5,42 euros par mois
Faire des économies, c'est facile ! Trouver votre MUTUELLE santé en 1 Clic (http://obfm41.com/tsk44uspikeisnffcy/index0.html) COMPAREZ les tarifs et garanties des plus grandes marques françaises OPTIMISEZ le budget santé de la famille -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_mar ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH v7 00/14] spi/spi-atmel: add dmaengine support for atmel spi controller and to test the device tree support
On 03/21/2013 10:32 AM, Nicolas Ferre : > On 03/19/2013 08:41 AM, Wenyou Yang : >> Hi All, >> >> This set of patches is to add dmaengine support for atmel spi and to test >> device tree support. >> >> The work is based on Nicolas and Richard's work. >> >> Because the dma engine device tree support isn't available now, to >> at91sam9x5ek and at91sam9n12ek >> with dma support, it doesn't work on the dmaengine mode, only on PIO mode so >> far. >> >> It has been tested as below: >> 1./tested on v3.9-rc3, by using mtd utils, "mount", "umount" and "cp" >> commands. >> 2./tested on "spi/next" git tree after changing master->num_chipselect >> which fixed in v3.9-rc1. >> 3./tested by using Documentation/spi/spidev_test.c on "/dev/spidev". >> 4./tested on on at91sam9x5ek, at91sam9m10g45ek, at91sam9263ek and >> at91sam9g20ek boards. >> >> It is based on v3.9-rc3 + Joachim Eastwood's spi/atmel: fix speed_hz check >> in atmel_spi_transfer(). >> >> Changelog: >> v7: >> 1./ remove patch: fix probing failure after xfer->speed_hz set. >> 2./ remove patch: add pinctrl support for atmel spi. > > > It it makes sense, you can add my: > > Acked-by: Nicolas Ferre > > on patches that I did not acknowledged yet. > > Grant, > > Can we move forward with this patch series so that we can build on solid > bases for future developments on atmel SPI. Moreover, if it can ease the process, I can take patches 11, 12, 13 and 14 with at91-dt branch and submit that to arm-soc. Tell me if you feel it is better... Bye, >> v6: >> 1./ remove: fix master->num_chipselect wrongly set patch which isn't a >> issue in v3.9-rc1. >> 2./ fix probing failure after xfer->speed_hz set. >> >> v5: >> 1./ add pinctrl patches. >> 2./ detect capabilities by reading spi version register to replace >> multiple compatiles. >> 3./ change the "cs-gpios" property of spi node. >> 4./ rebase on v3.8. >> >> v4: >> 1./ Take Joe Perches's adivce, rewrite atmel_spi_is_v2(struct atmel_spi >> *as) >> and atmel_spi_use_dma(struct atmel_spi *as), >> and remove atmel_spi_use_pdc(struct atmel_spi *as). >> 2./ Rebase on v3.8-rc3. >> >> V3: >> 1./ Rebase on v3.8-rc2. >> 2./ Remove some Jean-Christophe's patches which has been applied on >> v3.8-rc2. >> 3./ Remove spi property "cs-gpios" from the SoC dtsi files to the board >> dts files >> to avoid some useless pin conflicts. >> >> v2: >> 1./ Remove the patch :PATCH]mtd: m25p80: change the m25p80_read to >> reading page to page >> which purpose to fix the BUG: when run "flashcp /bin/busybox >> /dev/mtdX" in the at91sam9g25ek >> with DMA mode, it arises a OOPS. Now fix it in this patch: >> [PATHC] spi/atmel_spi: add dmaengine support changing to fix the >> [BUG]. >> 2./ Remove two patches: >> which purpose to read dts property to select SPI IP version and DMA >> mode >> Now they will be gat from device tree different compatile. >> 3./ Fix DMA: when enable both spi0 AND spi1, the spi0 doesn't work BUG. >> 4./ Rebase v3.7-rc8. >> >> Best Regards, >> Wenyou Yang. >> >> >> Nicolas Ferre (5): >> spi/spi-atmel: add physical base address >> spi/spi-atmel: call unmapping on transfers buffers >> spi/spi-atmel: status information passed through controller data >> spi/spi-atmel: add flag to controller data for lock operations >> spi/spi-atmel: add dmaengine support >> >> Richard Genoud (6): >> spi/spi-atmel: fix spi-atmel driver to adapt to slave_config changes >> spi/spi-atmel: correct 16 bits transfers using PIO >> spi/spi-atmel: correct 16 bits transfers with DMA >> ARM: at91: add clocks for spi dt entries >> ARM: dts: add spi nodes for atmel SoC >> ARM: dts: add spi nodes for the atmel boards >> >> Wenyou Yang (3): >> spi/spi-atmel: detect the capabilities of SPI core by reading the >> VERSION register. >> spi/spi-atmel: add support transfer on CS1,2,3, not only on CS0 >> ARM: dts: add pinctrl property for spi node for atmel SoC >> >> arch/arm/boot/dts/at91sam9260.dtsi | 40 ++ >> arch/arm/boot/dts/at91sam9263.dtsi | 40 ++ >> arch/arm/boot/dts/at91sam9263ek.dts | 10 + >> arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 10 + >> arch/arm/boot/dts/at91sam9g45.dtsi | 40 ++ >> arch/arm/boot/dts/at91sam9m10g45ek.dts | 10 + >> arch/arm/boot/dts/at91sam9n12.dtsi | 40 ++ >> arch/arm/boot/dts/at91sam9n12ek.dts | 10 + >> arch/arm/boot/dts/at91sam9x5.dtsi | 40 ++ >> arch/arm/boot/dts/at91sam9x5ek.dtsi | 10 + >> arch/arm/mach-at91/at91sam9260.c|2 + >> arch/arm/mach-at91/at91sam9g45.c|2 + >> arch/arm/mach-at91/at91sam9n12.c|2 + >> arch/arm/mach-at91/at91sam9x5.c |2 + >> drivers/spi/spi-atmel.c | 753 >> --- >> 15 files changed, 945 i
[PATCH 02/17] of_spi: add generic binding support to specify cs gpio
From: Jean-Christophe PLAGNIOL-VILLARD
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Cc: devicetree-disc...@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
Cc: grant.lik...@secretlab.ca
Cc: rob.herr...@calxeda.com
Cc: r...@landley.net
Cc: richard.gen...@gmail.com
---
Documentation/devicetree/bindings/spi/spi-bus.txt |6 +++
drivers/spi/spi.c | 55 +++--
include/linux/spi/spi.h |3 ++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt
b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..c253379 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
recommended practice.
+- cs-gpios - (optional) gpios chip select.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to
manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
+If cs-gpios is used the number of chip select will automatically increased.
+
SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- reg - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
- spi-cs-high - (optional) Empty property indicating device requires
chip select active high
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
SPI example for an MPC5200 SPI bus:
spi@f00 {
#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 84c2861..74e6577 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -327,6 +328,7 @@ struct spi_device *spi_alloc_device(struct spi_master
*master)
spi->dev.parent = &master->dev;
spi->dev.bus = &spi_bus_type;
spi->dev.release = spidev_release;
+ spi->cs_gpio = -EINVAL;
device_initialize(&spi->dev);
return spi;
}
@@ -344,15 +346,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
int spi_add_device(struct spi_device *spi)
{
static DEFINE_MUTEX(spi_add_lock);
- struct device *dev = spi->master->dev.parent;
+ struct spi_master *master = spi->master;
+ struct device *dev = master->dev.parent;
struct device *d;
int status;
/* Chipselects are numbered 0..max; validate. */
- if (spi->chip_select >= spi->master->num_chipselect) {
+ if (spi->chip_select >= master->num_chipselect) {
dev_err(dev, "cs%d >= max %d\n",
spi->chip_select,
- spi->master->num_chipselect);
+ master->num_chipselect);
return -EINVAL;
}
@@ -376,6 +379,9 @@ int spi_add_device(struct spi_device *spi)
goto done;
}
+ if (master->cs_gpios)
+ spi->cs_gpio = master->cs_gpios[spi->chip_select];
+
/* Drivers may modify this initial i/o setup, but will
* normally rely on the device being setup. Devices
* using SPI_CS_HIGH can't coexist well otherwise...
@@ -946,6 +952,45 @@ struct spi_master *spi_alloc_master(struct device *dev,
unsigned size)
}
EXPORT_SYMBOL_GPL(spi_alloc_master);
+#ifdef CONFIG_OF
+static int of_spi_register_master(struct spi_master *master)
+{
+ int nb, i;
+ int *cs;
+ struct device_node *np = master->dev.of_node;
+
+ if (!np)
+ return 0;
+
+ nb = of_gpio_named_count(np, "cs-gpios");
+
+ if (nb < 1)
+ return 0;
+
+ cs = devm_kzalloc(&master->dev,
+ sizeof(int) * (master->num_chipselect + nb),
+ GFP_KERNEL);
+ master->cs_gpios = cs;
+
+ if (!master->cs_gpios)
+ return -ENOMEM;
+
+ memset(cs, -EINVAL, master->num_chipselect);
+ cs += master->num_chipselect;
+ master->num_chipselect += nb;
+
+ for (i = 0; i < nb; i++)
+ cs[i] = of_get_named_gpio(np, "cs-gpios", i);
+
+ return 0;
+}
+#else
+static int of_spi_register_master(struc
Votre sejour jusqu'a moins70 pourcent.
Les ventes privées du N°1 de la vente de séjours sur internet (http://obfm40.com/elf3ry4uz4sin5c03d/index0.html) (http://obfm40.com/ujfedyoyztthvpx0hs/index1.html) (http://obfm40.com/vsfh4yrxzoki2a1dal/index2.html) Devenez membre du Club Privé du N°1 de la vente de séjours sur Internet. Plus une minute à perdre ! (http://obfm40.com/kqfuoyd5z34hl3fdiy/index3.html) (http://obfm40.com/tst44zsfukeiwk1tqs/index4.html) (http://obfm40.com/2qtrozppuswheuftjd/index5.html) (http://obfm40.com/bltnrzqkufdi04csgy/index6.html) (http://obfm40.com/0jt5dzwsup0hdzxsol/index7.html) (http://obfm40.com/dlppmbzeznqi5ycifd/index8.html) (http://obfm40.com/yjpwlbjdz2chasxi1s/index9.html) (http://obfm40.com/xf2dsrfo1tvlee5blg/index10.html) (http://obfm40.com/ctpo4tufnnve5vhisg/index11.html) (http://obfm40.com/4eiuafdhdap4yfegqd/index12.html) Une île intense d'est en ouest LA RéUNION 1069 ? 699?-35%* (http://obfm40.com/niyhxwmmiqpbcx44jd/index13.html) Je découvre (http://obfm40.com/ppztbvbg3vaxpcy3dq/index14.html) (http://obfm40.com/m4ccuj31ssapv122yq/index15.html) VACANCES TOUT INCLUS SUR L´ÎLE DE SAL CAP VERT 1378? 949?-31%* (http://obfm40.com/4lzkmvyvavocpoq3qd/index16.html) Je découvre (http://obfm40.com/ngcigjpnysomvjf2jd/index17.html) (http://obfm40.com/r10fgpkn24jnwg3bso/index18.html) DÉTENTE ET DOUCEURS SUR UNE OASIS FLOTTANTE DJERBA 379? 114?-69%* (http://obfm40.com/5250m0xvm2j0aqrilo/index19.html) Je découvre (http://obfm40.com/acu2oec5hxz2tipolq/index20.html) (http://obfm40.com/i0qxpovalrzwghinsq/index21.html) SUR UNE COLLINE AVEC VUE SUR LE TAGE LISBONNE 297? 55?-81%* (http://obfm40.com/3octsjtjykumnix2dq/index22.html) Je découvre (http://obfm40.com/hszc4vaxaluc3hg3yq/index23.html) (http://obfm40.com/amr0cxxzs2y5arthlq/index24.html) (http://obfm40.com/inbfinku34yfwmdtsq/index25.html) Des voyages à des tarifs privilégiés : jusqu´à 70% de réduction (http://obfm40.com/3ayb0w2yiibbqrz4dq/index26.html) Des avantages exclusivement réservés aux membres (http://obfm40.com/hui1efibdjb4bmvgyq/index27.html) 100? offerts pour chaque proche parrainé1 (http://obfm40.com/cruofvkp3znx4vsf1q/index28.html) Une nouvelle sélection de voyages chaque semaine (http://obfm40.com/xwqd3jx3s0nphe0vfq/index29.html) La vente de voyages sous la marque Clubprivévacances.com est assurée par Karavel - 17 rue de l´Echiquier 75010 Paris – SAS au capital de 39.838.060 euros – RCS Paris B 499 668 606 -Immatriculation "Atout France": IM075110099 – Garant : APS, 15 av Carnot 75017 Paris – RCP : Hiscox, 19 rue Louis le Grand 75002 Paris Nos prix sont affichés en TTC (soit le prix du séjour HT complété des taxes obligatoires hors taxes de séjour): prix "à partir de" et sous réserve de disponibilités. Ces tarifs n´incluent pas les frais de dossier et de dernière minute, ni les suppléments spécifiques susceptibles de s´appliquer à certaines dest inations. (*) Taux de réduction maximal, calculé à partir du tarif de référence sur une sélection de dates et de séjours. Offre soumise à conditions et valable sous réserve de disponibilité. (1) Consultez les conditions d´utilisation des bons de réduction sur : http://static.service-voyages.com/resources/club.prive/pdf/conditionsUtilisationBDR.pdf -- Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_mar ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH v3] gpio: mcp23s08: convert driver to DT
Hi Lars,
sorry for taking eternities to review stuff :-(
I recommend that you include SPI co-maintainer Mark Brown on subsequent
postings.
On Mon, Mar 4, 2013 at 5:34 PM, Lars Poeschel wrote:
> This converts the mcp23s08 driver to be able to be used with device
> tree.
OK!
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
> @@ -0,0 +1,43 @@
> +Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
> +8-/16-bit I/O expander with serial interface (I2C/SPI)
> +
> +Required properties:
> +- compatible : Should be
> +- "mcp,mcp23s08" for 8 GPIO SPI version
> +- "mcp,mcp23s17" for 16 GPIO SPI version
> +- "mcp,mcp23008" for 8 GPIO I2C version or
> +- "mcp,mcp23017" for 16 GPIO I2C version of the chip
> +- #gpio-cells : Should be two.
> + - first cell is the pin number
> + - second cell is used to specify flags. Flags currently used:
> +bit0 : activate a ~100k pullup
Pullup is basically about pin config. This is sort of sneaking
behind the subsystems, but I know I might be overzealous.
Can the electronics do more things than pull-up?
Like pull-down, open drain, drive strength...
If it's a lot it's better to consider pinctrl from the start.
I'm saying this because the DT bindings will be maintained
perpetually and need to set a good example.
I would currently feel a lot better if you did not include this
flag. How would you control this the day drivers need to
enable/disable pull-up at runtime?
> +- gpio-controller : Marks the device node as a GPIO controller.
> +- reg : For an address on its bus
On the I2C/SPI bus?
Please state here what kind of buses it can be. Explain if multiple
buses are supported.
> +Required device specific properties (only for SPI chips):
> +- mcp,spi-present-mask : This is a present flag, that makes only sense for
> SPI
> +chips - as the name suggests.
AFAIK this is not how we disable/enable devices in the device tree.
Istead we include a property on the node called "status" and set it
to "disabled" if the device is not there.
> +Multiple chips can share the same
> +SPI chipselect. Set bit 0-7 in this mask to 1 if there is a chip
> +connected with this spi address. If you have a chip with address 3
> +connected, you have to set bit3 to 1, which is 0x08. mcp23s08 only
> +supports bits 0-3. It is not possible to mix mcp23s08 and mcp23s17
> +on the same chipselect. Set at least one bit to 1 for SPI chips.
This looks awkward, why are you using a bitfield for this? Then you
can only ever support 8 devices, since the text also implies that the
value is 8bit (this should be stated).
What about just using a number?
> diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
> index 3cea0ea..a8ca469 100644
> --- a/drivers/gpio/gpio-mcp23s08.c
> +++ b/drivers/gpio/gpio-mcp23s08.c
> @@ -12,6 +12,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> /**
> * MCP types supported by driver
> @@ -21,6 +23,11 @@
> #define MCP_TYPE_008 2
> #define MCP_TYPE_017 3
>
> +/**
> + * Flags used in device tree
> + */
> +#define MCP_DT_FLAG_PULLUP 0x01
So I'm sceptical here. Is this already supported using platform data?
> /* Registers are all 8 bits wide.
> *
> * The mcp23s17 has twice as many bits, and can be configured to work
> @@ -75,6 +82,25 @@ struct mcp23s08_driver_data {
> struct mcp23s08 chip[];
> };
>
> +#ifdef CONFIG_OF
> +static int mcp23s08_of_xlate(struct gpio_chip *gc,
> + const struct of_phandle_args *gpiospec, u32 *flags);
> +
> +static int mcp23s08_set_pullup(struct mcp23s08 *mcp, unsigned offset)
> +{
> + int status;
> + u16 value;
> +
> + mutex_lock(&mcp->lock);
> + value = mcp->cache[MCP_GPPU] | (1 << offset);
> + status = mcp->ops->write(mcp, MCP_GPPU, value);
> + if (!status)
> + mcp->cache[MCP_GPPU] = value;
> + mutex_unlock(&mcp->lock);
> +
> + return status;
> +}
The pull-up business actually looks like new functionality that
has nothing to do with adding device tree support and should be
a separate patch.
Yours,
Linus Walleij
--
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://p.sf.net/sfu/appdyn_d2d_mar
___
spi-devel-general mailing list
spi-devel-general@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/spi-devel-general
