On Fri, May 13, 2011 at 09:22:57AM +0530, viresh kumar wrote:
On 05/11/2011 09:37 AM, viresh kumar wrote:
Actually i am seeing a different behavior by some of the spi
memories, like m25p10.
If there is a delay between read_sts_reg command and dummy bytes, then
0xFF is
returned in
On Wed, May 11, 2011 at 09:37:19AM +0530, viresh kumar wrote:
Following is what i understood after reading m25p80 driver and spi
master drivers in drivers/spi folder.
chip_select signal controls start and end of transfer. For ex: if we have to
read
status reg of spi memory, then we use
Hi Feng,
On Mon, Mar 21, 2011 at 10:06:42AM +0800, Feng Tang wrote:
Hi Jamie,
On Sat, 19 Mar 2011 04:11:35 +0800
Jamie Iles ja...@jamieiles.com wrote:
Hi,
I have a platform with a DesignWare SSI and I'm trying to use the
dw_spi block using a GPIO for the chip select to workaround
clk_get() returns a struct clk cookie to the driver and some platforms
may return NULL if they only support a single clock. clk_get() has only
failed if it returns a ERR_PTR() encoded pointer.
Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: Jamie Iles ja...@jamieiles.com
---
drivers
Some platforms have been known to return NULL from clk_get() if they
support only a single struct clk. Whilst tegra doesn't do this, make
the drivers consistent with others.
Cc: Erik Gilling konk...@android.com
Signed-off-by: Jamie Iles ja...@jamieiles.com
---
drivers/spi/spi_tegra.c |2
