The core can do the validation for us.
Signed-off-by: Mark Brown broo...@opensource.wolfsonmicro.com
---
drivers/spi/spi-s3c64xx.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 7f5f8ee..27ff669 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -911,15 +911,6 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spin_unlock_irqrestore(sdd-lock, flags);
- if (spi-bits_per_word != 8
-spi-bits_per_word != 16
-spi-bits_per_word != 32) {
- dev_err(spi-dev, setup: %dbits/wrd not supported!\n,
- spi-bits_per_word);
- err = -EINVAL;
- goto setup_exit;
- }
-
pm_runtime_get_sync(sdd-pdev-dev);
/* Check if we can provide the requested rate */
@@ -1237,6 +1228,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
master-unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
master-num_chipselect = sci-num_cs;
master-dma_alignment = 8;
+ master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
/* the spi-mode bits understood by this driver: */
master-mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
--
1.7.10.4
--
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