Author: br
Date: Tue Jun 4 15:40:30 2019
New Revision: 348626
URL: https://svnweb.freebsd.org/changeset/base/348626
Log:
MFC r347351:
Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.
Sponsored by: DARPA, AFRL
Modified:
stable/12/sys/conf/files.riscv
stable/12/sys/riscv/conf/GENERIC
Modified: stable/12/sys/conf/files.riscv
==============================================================================
--- stable/12/sys/conf/files.riscv Tue Jun 4 15:39:28 2019
(r348625)
+++ stable/12/sys/conf/files.riscv Tue Jun 4 15:40:30 2019
(r348626)
@@ -5,10 +5,13 @@ cddl/dev/dtrace/riscv/dtrace_subr.c
optional dtrace
cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt |
dtraceall compile-with "${FBT_C}"
crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support
crypto/des/des_enc.c optional crypto | ipsec | ipsec_support
| netsmb
+dev/cadence/if_cgem.c optional cgem
dev/ofw/ofw_cpu.c optional fdt
dev/uart/uart_cpu_fdt.c optional uart fdt
dev/uart/uart_dev_lowrisc.c optional uart_lowrisc
dev/xilinx/axi_quad_spi.c optional xilinx_spi
+dev/xilinx/axidma.c optional axidma xdma
+dev/xilinx/if_xae.c optional xae
kern/kern_clocksource.c standard
kern/msi_if.m standard
kern/pic_if.m standard
Modified: stable/12/sys/riscv/conf/GENERIC
==============================================================================
--- stable/12/sys/riscv/conf/GENERIC Tue Jun 4 15:39:28 2019
(r348625)
+++ stable/12/sys/riscv/conf/GENERIC Tue Jun 4 15:40:30 2019
(r348626)
@@ -102,6 +102,16 @@ device uart # Generic UART driver
device uart_lowrisc # lowRISC UART driver
device uart_ns8250 # ns8250-type UART driver
+
+# Ethernet drivers
+device miibus # MII bus support
+device cgem # Cadence Gigabit Ethernet MAC
+device xae # Xilinx AXI Ethernet MAC
+
+# DMA support
+device xdma # DMA interface
+device axidma # Xilinx AXI DMA Controller
+
# Uncomment for memory disk
# options MD_ROOT
# options MD_ROOT_SIZE=32768 # 32MB ram disk
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