Author: dim
Date: Thu Nov 21 20:32:34 2019
New Revision: 354983
URL: https://svnweb.freebsd.org/changeset/base/354983
Log:
Merge commit e578d0fd2 from llvm git (by Simon Atanasyan):
[mips] Fix `__mips_isa_rev` macros value for Octeon CPU
This is one of the upstream changes needed for adding support for the
OCTEON+ CPU type, so that we can test Clang builds using the most
commonly available FreeBSD/mips64 reference platform, the Edge Router
Lite.
Requested by: kevans
MFC after: 1 month
X-MFC-With: r353358
Modified:
head/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp
Modified: head/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp
==============================================================================
--- head/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp Thu Nov 21
20:26:34 2019 (r354982)
+++ head/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp Thu Nov 21
20:32:34 2019 (r354983)
@@ -62,7 +62,7 @@ void MipsTargetInfo::fillValidCPUList(
unsigned MipsTargetInfo::getISARev() const {
return llvm::StringSwitch<unsigned>(getCPU())
.Cases("mips32", "mips64", 1)
- .Cases("mips32r2", "mips64r2", 2)
+ .Cases("mips32r2", "mips64r2", "octeon", 2)
.Cases("mips32r3", "mips64r3", 3)
.Cases("mips32r5", "mips64r5", 5)
.Cases("mips32r6", "mips64r6", 6)
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