On Saturday 01 May 2010 9:47:58 pm M. Warner Losh wrote:
> In message: <9624cc6a-eeb1-4492-9e62-7acd0bf6f...@gsoft.com.au>
> "Daniel O'Connor" writes:
> :
> : On 02/05/2010, at 2:06 AM, Warner Losh wrote:
> : > Unfortunately, this condition is impossible to detect at runtime
> : > w
On 02/05/2010, at 11:17 AM, M. Warner Losh wrote:
> : Could you do TUNABLE_INT in the MIPS code and TUNABLE_INT_FETCH in ath_hal?
>
> How is that better than a kernel option? The only place this would
> ever happen is atheros AR71xx SoC. It isn't like some of the Atheros
> 71xx SoCs would have
In message: <9624cc6a-eeb1-4492-9e62-7acd0bf6f...@gsoft.com.au>
"Daniel O'Connor" writes:
:
: On 02/05/2010, at 2:06 AM, Warner Losh wrote:
: > Unfortunately, this condition is impossible to detect at runtime
: > without MIPS specific ifdefs. Rather than cast an overly-broad net
:
On 02/05/2010, at 2:06 AM, Warner Losh wrote:
> Unfortunately, this condition is impossible to detect at runtime
> without MIPS specific ifdefs. Rather than cast an overly-broad net
> like Linux/OpenWRT dues (which enables this workaround all the time on
> MIPS32 platforms), we put this optio
Author: imp
Date: Sat May 1 16:36:14 2010
New Revision: 207472
URL: http://svn.freebsd.org/changeset/base/207472
Log:
The Atheros AR71xx CPUs, when paired with the AR5212 parts, has a bug
that generates a fatal bus trap. Normally, the chips are setup to do
128 byte DMA bursts, but when on
