Author: imp
Date: Wed Jun 13 05:02:51 2012
New Revision: 236992
URL: http://svn.freebsd.org/changeset/base/236992
Log:
trim trailing whitespace
Modified:
head/sys/arm/include/armreg.h
head/sys/arm/include/asmacros.h
head/sys/arm/include/atomic.h
head/sys/arm/include/blockio.h
head/sys/arm/include/cpufunc.h
head/sys/arm/include/elf.h
head/sys/arm/include/endian.h
head/sys/arm/include/fdt.h
head/sys/arm/include/fp.h
head/sys/arm/include/frame.h
head/sys/arm/include/ieee.h
head/sys/arm/include/in_cksum.h
head/sys/arm/include/intr.h
head/sys/arm/include/katelib.h
head/sys/arm/include/param.h
head/sys/arm/include/pmap.h
head/sys/arm/include/profile.h
head/sys/arm/include/pte.h
head/sys/arm/include/resource.h
head/sys/arm/include/stack.h
head/sys/arm/include/vmparam.h
Modified: head/sys/arm/include/armreg.h
==============================================================================
--- head/sys/arm/include/armreg.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/armreg.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -327,7 +327,7 @@
/*
* ARM Instructions
*
- * 3 3 2 2 2
+ * 3 3 2 2 2
* 1 0 9 8 7 0
* +-------+-------------------------------------------------------+
* | cond | instruction dependant |
Modified: head/sys/arm/include/asmacros.h
==============================================================================
--- head/sys/arm/include/asmacros.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/asmacros.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -92,7 +92,7 @@
* This should only be used if the processor is not currently in SVC32
* mode. The processor mode is switched to SVC mode and the trap frame is
* stored. The SVC lr field is used to store the previous value of
- * lr in SVC mode.
+ * lr in SVC mode.
*
* NOTE: r13 and r14 are stored separately as a work around for the
* SA110 rev 2 STM^ bug
Modified: head/sys/arm/include/atomic.h
==============================================================================
--- head/sys/arm/include/atomic.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/atomic.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -285,7 +285,6 @@ atomic_fetchadd_32(volatile uint32_t *p,
return (start);
}
-
#endif /* _KERNEL */
static __inline int
Modified: head/sys/arm/include/blockio.h
==============================================================================
--- head/sys/arm/include/blockio.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/blockio.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -14,7 +14,7 @@
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/cpufunc.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -315,7 +315,7 @@ void sa11x0_drain_readbuf (void);
void sa11x0_context_switch (void);
void sa11x0_cpu_sleep (int mode);
-
+
void sa11x0_setup (char *string);
#endif
@@ -471,7 +471,7 @@ extern unsigned armv5_dcache_index_inc;
defined(CPU_FA526) || defined(CPU_FA626TE) ||
\
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
-
+
void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void);
void armv4_tlb_flushD (void);
@@ -526,7 +526,7 @@ void xscale_cache_flushD_rng (vm_offset_
void xscale_context_switch (void);
void xscale_setup (char *string);
-#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 ||
CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#ifdef CPU_XSCALE_81342
@@ -628,7 +628,7 @@ extern int arm_picache_ways;
extern int arm_pdcache_size; /* and unified */
extern int arm_pdcache_line_size;
-extern int arm_pdcache_ways;
+extern int arm_pdcache_ways;
extern int arm_pcache_type;
extern int arm_pcache_unified;
Modified: head/sys/arm/include/elf.h
==============================================================================
--- head/sys/arm/include/elf.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/elf.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -99,8 +99,8 @@ __ElfType(Auxinfo);
#define ELF_TARG_MACH EM_ARM
#define ELF_TARG_VER 1
-/*
- * Magic number for the elf trampoline, chosen wisely to be an immediate
+/*
+ * Magic number for the elf trampoline, chosen wisely to be an immediate
* value.
*/
#define MAGIC_TRAMP_NUMBER 0x5c000003
Modified: head/sys/arm/include/endian.h
==============================================================================
--- head/sys/arm/include/endian.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/endian.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -78,7 +78,7 @@ __bswap64(__uint64_t _x)
return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
- ((_x << 24) & ((__uint64_t)0xff << 40)) |
+ ((_x << 24) & ((__uint64_t)0xff << 40)) |
((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
}
Modified: head/sys/arm/include/fdt.h
==============================================================================
--- head/sys/arm/include/fdt.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/fdt.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -44,7 +44,7 @@
/* Max interrupt number */
#define FDT_INTR_MAX NIRQ
-/* Map phandle/intpin pair to global IRQ number */
+/* Map phandle/intpin pair to global IRQ number */
#define FDT_MAP_IRQ(node, pin) (pin)
/*
Modified: head/sys/arm/include/fp.h
==============================================================================
--- head/sys/arm/include/fp.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/fp.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -77,7 +77,7 @@ struct fpe_sp_state {
* Type for a saved FP context, if we want to translate the context to a
* user-readable form
*/
-
+
typedef struct {
u_int32_t fpsr;
fp_extended_precision_t regs[8];
Modified: head/sys/arm/include/frame.h
==============================================================================
--- head/sys/arm/include/frame.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/frame.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -148,7 +148,7 @@ struct switchframe {
u_int sf_r7;
u_int sf_pc;
};
-
+
/*
* Stack frame. Used during stack traces (db_trace.c)
*/
@@ -162,5 +162,3 @@ struct frame {
#endif /* !_LOCORE */
#endif /* _MACHINE_FRAME_H_ */
-
-/* End of frame.h */
Modified: head/sys/arm/include/ieee.h
==============================================================================
--- head/sys/arm/include/ieee.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/ieee.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -124,7 +124,7 @@ struct ieee_double {
u_int dbl_sign:1;
#if _IEEE_WORD_ORDER == _BIG_ENDIAN
u_int dbl_fracl;
-#endif
+#endif
#endif
};
Modified: head/sys/arm/include/in_cksum.h
==============================================================================
--- head/sys/arm/include/in_cksum.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/in_cksum.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -56,7 +56,7 @@ in_pseudo(u_int sum, u_int b, u_int c)
__asm __volatile("adds %0, %0, %1\n"
"adcs %0, %0, %2\n"
"adc %0, %0, #0\n"
- : "+r" (sum)
+ : "+r" (sum)
: "r" (b), "r" (c));
sum = (sum & 0xffff) + (sum >> 16);
if (sum > 0xffff)
Modified: head/sys/arm/include/intr.h
==============================================================================
--- head/sys/arm/include/intr.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/intr.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -59,8 +59,8 @@
int arm_get_next_irq(int);
void arm_mask_irq(uintptr_t);
void arm_unmask_irq(uintptr_t);
-void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
- void *, int, int, void **);
+void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
+ void *, int, int, void **);
int arm_remove_irqhandler(int, void *);
extern void (*arm_post_filter)(void *);
#endif /* _MACHINE_INTR_H */
Modified: head/sys/arm/include/katelib.h
==============================================================================
--- head/sys/arm/include/katelib.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/katelib.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -43,7 +43,7 @@
*
* This should not really be a separate header file. Eventually I will merge
* this into other header files once I have decided where the declarations
- * should go.
+ * should go.
*
* Created : 18/09/94
*
Modified: head/sys/arm/include/param.h
==============================================================================
--- head/sys/arm/include/param.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/param.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -62,7 +62,7 @@
#define MACHINE_ARCH "arm"
#endif
#endif
-#define MID_MACHINE MID_ARM6
+#define MID_MACHINE MID_ARM6
#if defined(SMP) || defined(KLD_MODULE)
#ifndef MAXCPU
@@ -78,7 +78,7 @@
* ALIGNED_POINTER is a boolean macro that checks whether an address
* is valid to fetch data elements of type t from on this architecture.
* This does not reflect the optimal alignment, just the possibility
- * (within reasonable limits).
+ * (within reasonable limits).
*/
#define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0)
Modified: head/sys/arm/include/pmap.h
==============================================================================
--- head/sys/arm/include/pmap.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/pmap.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -58,7 +58,7 @@
#define PTE_NOCACHE 0
#define PTE_CACHE 1
#define PTE_PAGETABLE 2
-
+
#ifndef LOCORE
#include <sys/queue.h>
@@ -413,7 +413,7 @@ extern pt_entry_t pte_l2_s_cache_mode_p
extern pt_entry_t pte_l2_s_prot_u;
extern pt_entry_t pte_l2_s_prot_w;
extern pt_entry_t pte_l2_s_prot_mask;
-
+
extern pt_entry_t pte_l1_s_proto;
extern pt_entry_t pte_l1_c_proto;
extern pt_entry_t pte_l2_s_proto;
Modified: head/sys/arm/include/profile.h
==============================================================================
--- head/sys/arm/include/profile.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/profile.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -38,7 +38,7 @@
#define _MACHINE_PROFILE_H_
/*
- * Config generates something to tell the compiler to align functions on 32
+ * Config generates something to tell the compiler to align functions on 32
* byte boundaries. A strict alignment is good for keeping the tables small.
*/
#define FUNCTION_ALIGNMENT 16
Modified: head/sys/arm/include/pte.h
==============================================================================
--- head/sys/arm/include/pte.h Wed Jun 13 04:59:55 2012 (r236991)
+++ head/sys/arm/include/pte.h Wed Jun 13 05:02:51 2012 (r236992)
@@ -58,7 +58,7 @@ typedef uint32_t pt_entry_t; /* page
ta
* was allocated for a PT then the other 3KB would also get mapped
* whenever the 1KB was mapped.
*/
-
+
#define PT_RSIZE 0x0400 /* Real page table size */
#define PT_SIZE 0x1000
#define PD_SIZE 0x4000
@@ -315,7 +315,7 @@ typedef uint32_t pt_entry_t; /* page
ta
*
* Cache attributes with L2 present, S = 0
* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
- * 0 0 0 0 0 N N - N N
+ * 0 0 0 0 0 N N - N N
* 0 0 0 0 1 N N - N Y
* 0 0 0 1 0 Y Y WT N Y
* 0 0 0 1 1 Y Y WB Y Y
@@ -342,7 +342,7 @@ typedef uint32_t pt_entry_t; /* page
ta
*
* Cache attributes with L2 present, S = 1
* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
- * 0 0 0 0 0 N N - N N
+ * 0 0 0 0 0 N N - N N
* 0 0 0 0 1 N N - N Y
* 0 0 0 1 0 Y Y - N Y
* 0 0 0 1 1 Y Y WT Y Y
Modified: head/sys/arm/include/resource.h
==============================================================================
--- head/sys/arm/include/resource.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/resource.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -12,7 +12,7 @@
* no representations about the suitability of this software for any
* purpose. It is provided "as is" without express or implied
* warranty.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Modified: head/sys/arm/include/stack.h
==============================================================================
--- head/sys/arm/include/stack.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/stack.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -5,24 +5,24 @@
* Mach Operating System
* Copyright (c) 1991,1990 Carnegie Mellon University
* All Rights Reserved.
- *
+ *
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
- *
+ *
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
+ *
* Carnegie Mellon requests users of this software to return to
- *
+ *
* Software Distribution Coordinator or software.distribut...@cs.cmu.edu
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
- *
+ *
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*
Modified: head/sys/arm/include/vmparam.h
==============================================================================
--- head/sys/arm/include/vmparam.h Wed Jun 13 04:59:55 2012
(r236991)
+++ head/sys/arm/include/vmparam.h Wed Jun 13 05:02:51 2012
(r236992)
@@ -104,7 +104,7 @@
#define VM_MIN_ADDRESS (0x00001000)
#ifdef ARM_USE_SMALL_ALLOC
-/*
+/*
* ARM_KERN_DIRECTMAP is used to make sure there's enough space between
* VM_MAXUSER_ADDRESS and KERNBASE to map the whole memory.
* It has to be a compile-time constant, even if arm_init_smallalloc(),
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