Author: sgalabov
Date: Fri Nov 16 11:17:18 2018
New Revision: 340476
URL: https://svnweb.freebsd.org/changeset/base/340476
Log:
Implement support for sysctl hw.model for Mediatek/Ralink SoCs
These SoCs have CHIPID registers, which store the Chip model, according
to the manufacturer; make use of those in order to better identify
the chip we're actually running on.
If we're unable to read the CHIPID registers for some reason we will
use the string "unknown " as a value for hw.model.
Reported by: yamori...@yahoo.co.jp
Sponsored by: Smartcom - Bulgaria AD
Modified:
head/sys/mips/mediatek/mtk_machdep.c
head/sys/mips/mediatek/mtk_soc.c
head/sys/mips/mediatek/mtk_soc.h
head/sys/mips/mediatek/mtk_sysctl.h
Modified: head/sys/mips/mediatek/mtk_machdep.c
==============================================================================
--- head/sys/mips/mediatek/mtk_machdep.c Fri Nov 16 10:20:35 2018
(r340475)
+++ head/sys/mips/mediatek/mtk_machdep.c Fri Nov 16 11:17:18 2018
(r340476)
@@ -233,6 +233,8 @@ platform_start(__register_t a0 __unused, __register_t
while (1);
mtk_soc_try_early_detect();
+ mtk_soc_set_cpu_model();
+
if ((timer_clk = mtk_soc_get_timerclk()) == 0)
timer_clk = 1000000000; /* no such speed yet */
Modified: head/sys/mips/mediatek/mtk_soc.c
==============================================================================
--- head/sys/mips/mediatek/mtk_soc.c Fri Nov 16 10:20:35 2018
(r340475)
+++ head/sys/mips/mediatek/mtk_soc.c Fri Nov 16 11:17:18 2018
(r340476)
@@ -52,6 +52,9 @@ static uint32_t mtk_soc_uartclk = 0;
static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2;
+static uint32_t mtk_soc_chipid0_3 = MTK_UNKNOWN_CHIPID0_3;
+static uint32_t mtk_soc_chipid4_7 = MTK_UNKNOWN_CHIPID4_7;
+
static const struct ofw_compat_data compat_data[] = {
{ "ralink,rt2880-soc", MTK_SOC_RT2880 },
{ "ralink,rt3050-soc", MTK_SOC_RT3050 },
@@ -295,6 +298,10 @@ mtk_soc_try_early_detect(void)
if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh))
return;
+ /* Get our CHIP ID */
+ mtk_soc_chipid0_3 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
+ mtk_soc_chipid4_7 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID4_7);
+
/* First, figure out the CPU clock */
switch (mtk_soc_socid) {
case MTK_SOC_RT2880:
@@ -387,6 +394,28 @@ mtk_soc_try_early_detect(void)
}
bus_space_unmap(bst, bsh, MTK_DEFAULT_SIZE);
+}
+
+extern char cpu_model[];
+
+void
+mtk_soc_set_cpu_model(void)
+{
+ uint32_t *p_model = (uint32_t *)cpu_model;
+
+ /*
+ * CHIPID is always 2x32 bit registers, containing the ASCII
+ * representation of the chip, so use that directly.
+ *
+ * The info is either pre-populated in mtk_soc_try_early_detect() or
+ * it is left at its default value of "unknown " if it could not be
+ * obtained for some reason.
+ */
+ p_model[0] = mtk_soc_chipid0_3;
+ p_model[1] = mtk_soc_chipid4_7;
+
+ /* Null-terminate the string */
+ cpu_model[8] = 0;
}
uint32_t
Modified: head/sys/mips/mediatek/mtk_soc.h
==============================================================================
--- head/sys/mips/mediatek/mtk_soc.h Fri Nov 16 10:20:35 2018
(r340475)
+++ head/sys/mips/mediatek/mtk_soc.h Fri Nov 16 11:17:18 2018
(r340476)
@@ -122,6 +122,7 @@ enum mtk_soc_id {
#define MTK_DEFAULT_SIZE 0x6000
extern void mtk_soc_try_early_detect(void);
+extern void mtk_soc_set_cpu_model(void);
extern uint32_t mtk_soc_get_uartclk(void);
extern uint32_t mtk_soc_get_cpuclk(void);
extern uint32_t mtk_soc_get_timerclk(void);
Modified: head/sys/mips/mediatek/mtk_sysctl.h
==============================================================================
--- head/sys/mips/mediatek/mtk_sysctl.h Fri Nov 16 10:20:35 2018
(r340475)
+++ head/sys/mips/mediatek/mtk_sysctl.h Fri Nov 16 11:17:18 2018
(r340476)
@@ -54,6 +54,9 @@
#define RT3350_CHIPID0_3 0x33335452
+#define MTK_UNKNOWN_CHIPID0_3 0x6E6B6E75 /* "unkn" */
+#define MTK_UNKNOWN_CHIPID4_7 0x206E776F /* "own " */
+
extern uint32_t mtk_sysctl_get(uint32_t);
extern void mtk_sysctl_set(uint32_t, uint32_t);
extern void mtk_sysctl_clr_set(uint32_t, uint32_t, uint32_t);
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