Author: br
Date: Fri Jun 12 13:59:58 2020
New Revision: 362099
URL: https://svnweb.freebsd.org/changeset/base/362099
Log:
ARM Coresight Trace Memory Controller (TMC):
o Split-out FDT attachment to a separate file;
o Add ACPI attachment.
Sponsored by: DARPA, AFRL
Added:
head/sys/arm64/coresight/coresight_tmc_acpi.c (contents, props changed)
head/sys/arm64/coresight/coresight_tmc_fdt.c (contents, props changed)
Modified:
head/sys/arm64/coresight/coresight_tmc.c
head/sys/arm64/coresight/coresight_tmc.h
head/sys/conf/files.arm64
Modified: head/sys/arm64/coresight/coresight_tmc.c
==============================================================================
--- head/sys/arm64/coresight/coresight_tmc.c Fri Jun 12 13:54:41 2020
(r362098)
+++ head/sys/arm64/coresight/coresight_tmc.c Fri Jun 12 13:59:58 2020
(r362099)
@@ -42,9 +42,6 @@ __FBSDID("$FreeBSD$");
#include <arm64/coresight/coresight.h>
#include <arm64/coresight/coresight_tmc.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
#include "coresight_if.h"
#define TMC_DEBUG
@@ -56,25 +53,6 @@ __FBSDID("$FreeBSD$");
#define dprintf(fmt, ...)
#endif
-static struct ofw_compat_data compat_data[] = {
- { "arm,coresight-tmc", 1 },
- { NULL, 0 }
-};
-
-struct tmc_softc {
- struct resource *res;
- device_t dev;
- uint64_t cycle;
- struct coresight_platform_data *pdata;
- uint32_t dev_type;
-#define CORESIGHT_UNKNOWN 0
-#define CORESIGHT_ETR 1
-#define CORESIGHT_ETF 2
- uint32_t nev;
- struct coresight_event *event;
- boolean_t etf_configured;
-};
-
static struct resource_spec tmc_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
@@ -335,21 +313,6 @@ tmc_read(device_t dev, struct endpoint *endp,
}
static int
-tmc_probe(device_t dev)
-{
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
- return (ENXIO);
-
- device_set_desc(dev, "Coresight Trace Memory Controller (TMC)");
-
- return (BUS_PROBE_DEFAULT);
-}
-
-static int
tmc_attach(device_t dev)
{
struct coresight_desc desc;
@@ -375,7 +338,6 @@ tmc_attach(device_t dev)
static device_method_t tmc_methods[] = {
/* Device interface */
- DEVMETHOD(device_probe, tmc_probe),
DEVMETHOD(device_attach, tmc_attach),
/* Coresight interface */
@@ -386,13 +348,4 @@ static device_method_t tmc_methods[] = {
DEVMETHOD_END
};
-static driver_t tmc_driver = {
- "tmc",
- tmc_methods,
- sizeof(struct tmc_softc),
-};
-
-static devclass_t tmc_devclass;
-
-DRIVER_MODULE(tmc, simplebus, tmc_driver, tmc_devclass, 0, 0);
-MODULE_VERSION(tmc, 1);
+DEFINE_CLASS_0(tmc, tmc_driver, tmc_methods, sizeof(struct tmc_softc));
Modified: head/sys/arm64/coresight/coresight_tmc.h
==============================================================================
--- head/sys/arm64/coresight/coresight_tmc.h Fri Jun 12 13:54:41 2020
(r362098)
+++ head/sys/arm64/coresight/coresight_tmc.h Fri Jun 12 13:59:58 2020
(r362099)
@@ -116,4 +116,20 @@
#define TMC_COMPID2 0xFF8 /* Component ID2 Register */
#define TMC_COMPID3 0xFFC /* Component ID3 Register */
+DECLARE_CLASS(tmc_driver);
+
+struct tmc_softc {
+ struct resource *res;
+ device_t dev;
+ uint64_t cycle;
+ struct coresight_platform_data *pdata;
+ uint32_t dev_type;
+#define CORESIGHT_UNKNOWN 0
+#define CORESIGHT_ETR 1
+#define CORESIGHT_ETF 2
+ uint32_t nev;
+ struct coresight_event *event;
+ boolean_t etf_configured;
+};
+
#endif /* !_ARM64_CORESIGHT_CORESIGHT_TMC_H_ */
Added: head/sys/arm64/coresight/coresight_tmc_acpi.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm64/coresight/coresight_tmc_acpi.c Fri Jun 12 13:59:58
2020 (r362099)
@@ -0,0 +1,79 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Ruslan Bukin <b...@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_acpi.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/memdesc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <contrib/dev/acpica/include/acpi.h>
+#include <dev/acpica/acpivar.h>
+
+#include <arm64/coresight/coresight_tmc.h>
+
+static int
+tmc_acpi_probe(device_t dev)
+{
+ static char *tmc_ids[] = { "ARMHC97C", NULL };
+ int error;
+
+ error = ACPI_ID_PROBE(device_get_parent(dev), dev, tmc_ids, NULL);
+ if (error <= 0)
+ device_set_desc(dev, "ARM Coresight TMC");
+
+ return (error);
+}
+
+static device_method_t tmc_acpi_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, tmc_acpi_probe),
+
+ /* End */
+ DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(tmc, tmc_acpi_driver, tmc_acpi_methods,
+ sizeof(struct tmc_softc), tmc_driver);
+
+static devclass_t tmc_acpi_devclass;
+
+EARLY_DRIVER_MODULE(tmc, acpi, tmc_acpi_driver, tmc_acpi_devclass,
+ 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
Added: head/sys/arm64/coresight/coresight_tmc_fdt.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm64/coresight/coresight_tmc_fdt.c Fri Jun 12 13:59:58
2020 (r362099)
@@ -0,0 +1,82 @@
+/*-
+ * Copyright (c) 2018-2020 Ruslan Bukin <b...@bsdpad.com>
+ * All rights reserved.
+ *
+ * This software was developed by BAE Systems, the University of Cambridge
+ * Computer Laboratory, and Memorial University under DARPA/AFRL contract
+ * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
+ * (TC) research program.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm64/coresight/coresight.h>
+#include <arm64/coresight/coresight_tmc.h>
+
+#include "coresight_if.h"
+
+static struct ofw_compat_data compat_data[] = {
+ { "arm,coresight-tmc", 1 },
+ { NULL, 0 }
+};
+
+static int
+tmc_fdt_probe(device_t dev)
+{
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "ARM Coresight TMC");
+
+ return (BUS_PROBE_DEFAULT);
+}
+
+static device_method_t tmc_fdt_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, tmc_fdt_probe),
+ DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(tmc, tmc_fdt_driver, tmc_fdt_methods,
+ sizeof(struct tmc_softc), tmc_driver);
+
+static devclass_t tmc_fdt_devclass;
+
+EARLY_DRIVER_MODULE(tmc, simplebus, tmc_fdt_driver, tmc_fdt_devclass,
+ 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
Modified: head/sys/conf/files.arm64
==============================================================================
--- head/sys/conf/files.arm64 Fri Jun 12 13:54:41 2020 (r362098)
+++ head/sys/conf/files.arm64 Fri Jun 12 13:59:58 2020 (r362099)
@@ -197,6 +197,8 @@ arm64/coresight/coresight_funnel.c standard
arm64/coresight/coresight_funnel_acpi.c optional acpi
arm64/coresight/coresight_funnel_fdt.c optional fdt
arm64/coresight/coresight_tmc.c standard
+arm64/coresight/coresight_tmc_acpi.c optional acpi
+arm64/coresight/coresight_tmc_fdt.c optional fdt
arm64/intel/firmware.c optional soc_intel_stratix10
arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10
arm64/intel/stratix10-svc.c optional soc_intel_stratix10
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