Author: dim
Date: Wed Sep 9 18:11:04 2020
New Revision: 365507
URL: https://svnweb.freebsd.org/changeset/base/365507
Log:
Merge commit e6bb4c8e7 from llvm git (by Craig Topper):
[X86] SSE4_A should only imply SSE3 not SSSE3 in the frontend.
SSE4_1 and SSE4_2 due imply SSSE3. So I guess I got confused when
switching the code to being table based in D83273.
Fixes PR47464
This should fix builds with -march=amdfam10 emitting SSSE3 instructions
such as pshufb, which lead to programs crashing with SIGILL on such
processors.
Reported by: avg
MFC after: 6 weeks
X-MFC-With: r364284
Modified:
head/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp
Modified: head/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp
==============================================================================
--- head/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp Wed Sep
9 18:07:13 2020 (r365506)
+++ head/contrib/llvm-project/llvm/lib/Support/X86TargetParser.cpp Wed Sep
9 18:11:04 2020 (r365507)
@@ -522,7 +522,7 @@ static constexpr FeatureBitset ImpliedFeaturesAVX5124F
static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
// SSE4_A->FMA4->XOP chain.
-static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3;
+static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX |
FeatureSSE4_A;
static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
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