subject:"svn commit\: r366452 \- in stable\: 11\/contrib\/llvm\-project\/clang\/lib\/Basic\/Targets 11\/contrib\/llvm\-project\/llvm\/lib\/Target\/X86 12\/contrib\/llvm\-project\/clang\/lib\/Basic\/Targets 12\/contrib\/llvm\-project\/..."

svn commit: r366452 - in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/...

2020-10-05 Thread Dimitry Andric

Author: dim
Date: Mon Oct  5 18:08:52 2020
New Revision: 366452
URL: https://svnweb.freebsd.org/changeset/base/366452

Log:
  Merge commit 0fac1c191 from llvm git (by Craig Topper):
  
[X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when
avx/avx512 are enabled and type is 256 or 512 bits
  
gcc supports selecting ymm0/zmm0 for the Yz constraint when used with
256 or 512 bit vector types.
  
Fixes PR45806
  
Differential Revision: https://reviews.llvm.org/D79448
  
  This should fix 'fatal error: error in backend: Cannot select' errors if
  assertions are disabled, or 'Assertion failed: (isVector() && "Invalid
  vector type!"), function getVectorNumElements, file
  /usr/src/contrib/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h,
  line 276.', when building the audio/lsp-plugins-lv2 port.
  
  Direct commit to stable/{11,12} since head has clang 11.0.0, which
  already includes this fix.
  
  Reported by:  yuri
  PR:   232911

Modified:
  stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
  stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in other areas also in this revision:
Modified:
  stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
  stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp

Modified: stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
==
--- stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp  Mon Oct 
 5 16:39:38 2020(r366451)
+++ stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp  Mon Oct 
 5 18:08:52 2020(r366452)
@@ -1772,8 +1772,14 @@ bool X86TargetInfo::validateOperandSize(const llvm::St
   return Size <= 64;
 case 'z':
 case '0':
-  // XMM0
-  if (FeatureMap.lookup("sse"))
+  // XMM0/YMM/ZMM0
+  if (FeatureMap.lookup("avx512f"))
+// ZMM0 can be used if target supports AVX512F.
+return Size <= 512U;
+  else if (FeatureMap.lookup("avx"))
+// YMM0 can be used if target supports AVX.
+return Size <= 256U;
+  else if (FeatureMap.lookup("sse"))
 return Size <= 128U;
   return false;
 case 'i':

Modified: stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp
==
--- stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp  
Mon Oct  5 16:39:38 2020(r366451)
+++ stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp  
Mon Oct  5 18:08:52 2020(r366452)
@@ -46555,7 +46555,9 @@ TargetLowering::ConstraintWeight
   // XMM0
   case 'z':
   case '0':
-if ((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1())
+if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
+((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()) ||
+((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512()))
   return CW_SpecificReg;
 return CW_Invalid;
   // Conditional OpMask regs (AVX512)
@@ -47005,6 +47007,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
 if (Subtarget.hasAVX())
   return std::make_pair(0U, ::VR256RegClass);
 break;
+  case MVT::v64i8:
+  case MVT::v32i16:
   case MVT::v8f64:
   case MVT::v16f32:
   case MVT::v16i32:
@@ -47030,7 +47034,42 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
 case 'z':
 case '0':
   if (!Subtarget.hasSSE1()) break;
-  return std::make_pair(X86::XMM0, ::VR128RegClass);
+  switch (VT.SimpleTy) {
+  default: break;
+  // Scalar SSE types.
+  case MVT::f32:
+  case MVT::i32:
+return std::make_pair(X86::XMM0, ::FR32RegClass);
+  case MVT::f64:
+  case MVT::i64:
+return std::make_pair(X86::XMM0, ::FR64RegClass);
+  case MVT::f128:
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64:
+return std::make_pair(X86::XMM0, ::VR128RegClass);
+  // AVX types.
+  case MVT::v32i8:
+  case MVT::v16i16:
+  case MVT::v8i32:
+  case MVT::v4i64:
+  case MVT::v8f32:
+  case MVT::v4f64:
+if (Subtarget.hasAVX())
+  return std::make_pair(X86::YMM0, ::VR256RegClass);
+break;
+  case MVT::v8f64:
+  case MVT::v16f32:
+  case MVT::v16i32:
+  case MVT::v8i64:
+if (Subtarget.hasAVX512())
+  return std::make_pair(X86::ZMM0, ::VR512_0_15RegClass);
+break;
+  }
+  break;
 case 'k':
   // This register class doesn't allocate k0 for masked vector operation.
   if (Subtarget.hasAVX512()) {
___
svn-src-all@freebsd.org mailing list

svn commit: r366452 - in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/...

2020-10-05 Thread Dimitry Andric

Author: dim
Date: Mon Oct  5 18:08:52 2020
New Revision: 366452
URL: https://svnweb.freebsd.org/changeset/base/366452

Log:
  Merge commit 0fac1c191 from llvm git (by Craig Topper):
  
[X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when
avx/avx512 are enabled and type is 256 or 512 bits
  
gcc supports selecting ymm0/zmm0 for the Yz constraint when used with
256 or 512 bit vector types.
  
Fixes PR45806
  
Differential Revision: https://reviews.llvm.org/D79448
  
  This should fix 'fatal error: error in backend: Cannot select' errors if
  assertions are disabled, or 'Assertion failed: (isVector() && "Invalid
  vector type!"), function getVectorNumElements, file
  /usr/src/contrib/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h,
  line 276.', when building the audio/lsp-plugins-lv2 port.
  
  Direct commit to stable/{11,12} since head has clang 11.0.0, which
  already includes this fix.
  
  Reported by:  yuri
  PR:   232911

Modified:
  stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
  stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in other areas also in this revision:
Modified:
  stable/11/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
  stable/11/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp

Modified: stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp
==
--- stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp  Mon Oct 
 5 16:39:38 2020(r366451)
+++ stable/12/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp  Mon Oct 
 5 18:08:52 2020(r366452)
@@ -1772,8 +1772,14 @@ bool X86TargetInfo::validateOperandSize(const llvm::St
   return Size <= 64;
 case 'z':
 case '0':
-  // XMM0
-  if (FeatureMap.lookup("sse"))
+  // XMM0/YMM/ZMM0
+  if (FeatureMap.lookup("avx512f"))
+// ZMM0 can be used if target supports AVX512F.
+return Size <= 512U;
+  else if (FeatureMap.lookup("avx"))
+// YMM0 can be used if target supports AVX.
+return Size <= 256U;
+  else if (FeatureMap.lookup("sse"))
 return Size <= 128U;
   return false;
 case 'i':

Modified: stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp
==
--- stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp  
Mon Oct  5 16:39:38 2020(r366451)
+++ stable/12/contrib/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp  
Mon Oct  5 18:08:52 2020(r366452)
@@ -46555,7 +46555,9 @@ TargetLowering::ConstraintWeight
   // XMM0
   case 'z':
   case '0':
-if ((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1())
+if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
+((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()) ||
+((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512()))
   return CW_SpecificReg;
 return CW_Invalid;
   // Conditional OpMask regs (AVX512)
@@ -47005,6 +47007,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
 if (Subtarget.hasAVX())
   return std::make_pair(0U, ::VR256RegClass);
 break;
+  case MVT::v64i8:
+  case MVT::v32i16:
   case MVT::v8f64:
   case MVT::v16f32:
   case MVT::v16i32:
@@ -47030,7 +47034,42 @@ X86TargetLowering::getRegForInlineAsmConstraint(const 
 case 'z':
 case '0':
   if (!Subtarget.hasSSE1()) break;
-  return std::make_pair(X86::XMM0, ::VR128RegClass);
+  switch (VT.SimpleTy) {
+  default: break;
+  // Scalar SSE types.
+  case MVT::f32:
+  case MVT::i32:
+return std::make_pair(X86::XMM0, ::FR32RegClass);
+  case MVT::f64:
+  case MVT::i64:
+return std::make_pair(X86::XMM0, ::FR64RegClass);
+  case MVT::f128:
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64:
+return std::make_pair(X86::XMM0, ::VR128RegClass);
+  // AVX types.
+  case MVT::v32i8:
+  case MVT::v16i16:
+  case MVT::v8i32:
+  case MVT::v4i64:
+  case MVT::v8f32:
+  case MVT::v4f64:
+if (Subtarget.hasAVX())
+  return std::make_pair(X86::YMM0, ::VR256RegClass);
+break;
+  case MVT::v8f64:
+  case MVT::v16f32:
+  case MVT::v16i32:
+  case MVT::v8i64:
+if (Subtarget.hasAVX512())
+  return std::make_pair(X86::ZMM0, ::VR512_0_15RegClass);
+break;
+  }
+  break;
 case 'k':
   // This register class doesn't allocate k0 for masked vector operation.
   if (Subtarget.hasAVX512()) {
___
svn-src-all@freebsd.org mailing list

svn commit: r366452 - in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/...

svn commit: r366452 - in stable: 11/contrib/llvm-project/clang/lib/Basic/Targets 11/contrib/llvm-project/llvm/lib/Target/X86 12/contrib/llvm-project/clang/lib/Basic/Targets 12/contrib/llvm-project/...

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