Author: andrew
Date: Fri Mar 6 14:46:50 2020
New Revision: 358703
URL: https://svnweb.freebsd.org/changeset/base/358703
Log:
Update the hypervisor registers
- Add more registers needed by bhyve [1]
- Move EL2 registers from armreg.h to hypervisor.h
- Add the register name to
Author: andrew
Date: Thu Mar 5 10:52:16 2020
New Revision: 358669
URL: https://svnweb.freebsd.org/changeset/base/358669
Log:
Mark the arm64 machdep.h as kernel only
None of this is useful for userspace.
Sponsored by: Innovate UK
Modified:
head/sys/arm64/include/machdep.h
Author: andrew
Date: Tue Mar 3 15:31:40 2020
New Revision: 358584
URL: https://svnweb.freebsd.org/changeset/base/358584
Log:
Fix the spelling of aliasing.
Sponsored by: Innovate UK
Modified:
head/sys/arm64/arm64/identcpu.c
head/sys/arm64/include/cpufunc.h
Modified:
Author: andrew
Date: Tue Mar 3 15:25:01 2020
New Revision: 358583
URL: https://svnweb.freebsd.org/changeset/base/358583
Log:
Move the arm64 cache identification to identcpu.c
This allows us to call it on a per-CPU basis and to warn if the details
are different across CPUs.
While
Author: andrew
Date: Tue Mar 3 12:50:45 2020
New Revision: 358573
URL: https://svnweb.freebsd.org/changeset/base/358573
Log:
Fix the spelling of the VIPT cache type field
Sponsored by: Innovate UK
Modified:
head/sys/arm64/arm64/identcpu.c
head/sys/arm64/include/armreg.h
Modified:
Author: andrew
Date: Tue Mar 3 08:28:16 2020
New Revision: 358567
URL: https://svnweb.freebsd.org/changeset/base/358567
Log:
Store the boot exception level on arm64 so it can be queried later
A hypervisor, e.g. bhyve, will need to know what exception levelthe kernel
was in when it
Author: andrew
Date: Mon Mar 2 14:36:15 2020
New Revision: 358547
URL: https://svnweb.freebsd.org/changeset/base/358547
Log:
Add a space missed in r358545
Sponsored by: Innovate UK
Modified:
head/sys/arm64/arm64/genassym.c
Modified: head/sys/arm64/arm64/genassym.c
Author: andrew
Date: Mon Mar 2 14:06:50 2020
New Revision: 358545
URL: https://svnweb.freebsd.org/changeset/base/358545
Log:
Generate the offsets for struct arm64_bootparams and use it in locore.S
This removes one place with hard coded offsets in locore.S
Sponsored by: Innovate UK
Author: andrew
Date: Wed Feb 26 15:56:07 2020
New Revision: 358338
URL: https://svnweb.freebsd.org/changeset/base/358338
Log:
Fix the cache type identification
DIC and IDC are supported when the field bits are set.
Sponsored by: Innovate UK
Modified:
head/sys/arm64/arm64/identcpu.c
Author: andrew
Date: Wed Feb 26 13:22:23 2020
New Revision: 358330
URL: https://svnweb.freebsd.org/changeset/base/358330
Log:
Teach the arm64 ident CPU code to print non-ID registers
Add support for non-ID registers when printing CPU information. This is
used with the cache type register
Author: andrew
Date: Wed Feb 26 11:50:24 2020
New Revision: 358328
URL: https://svnweb.freebsd.org/changeset/base/358328
Log:
Generalise the arm64 ASID allocator.
The requirements of an Address Space ID allocator and a Virtual Machine ID
allocator are similar. Generalise the former code
Author: andrew
Date: Wed Feb 26 11:47:24 2020
New Revision: 358327
URL: https://svnweb.freebsd.org/changeset/base/358327
Log:
Start to support multiple stages in the arm64 pmap.
On arm64 the stage 1 and stage 2 pte formats are similar enough we can
reuse the pmap code for both. As they
Author: andrew
Date: Wed Feb 26 11:29:03 2020
New Revision: 358326
URL: https://svnweb.freebsd.org/changeset/base/358326
Log:
Add more arm64 CTR_EL0 register fields
While here make the _SIZE macros return the size in bytes, not the log2
of the size
Sponsored by: Innovate UK
Author: andrew
Date: Mon Feb 24 16:45:31 2020
New Revision: 358294
URL: https://svnweb.freebsd.org/changeset/base/358294
Log:
Split out the stage 1 pte bits and add the stage 2 bits
In preperation for adding bhyve support to arm64 we need to split the
stage 1 and stage 2 pte fields to
Author: andrew
Date: Mon Feb 17 15:32:21 2020
New Revision: 358027
URL: https://svnweb.freebsd.org/changeset/base/358027
Log:
Use EARLY_DRIVER_MODULE in the acpi bus.
We need this to use EARLY_DRIVER_MODULE in child drivers on arm64. This
should be a no-op on x86 as it has DRIVER_MODULE
/arm64/linux/linux_locore.asm Sat Feb 8 13:35:56 2020
(r357677)
@@ -2,6 +2,7 @@
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (C) 2018 Turing Robotic Industries Inc.
+ * Copyright (C) 2020 Andrew Turner
*
* Redistribution and use in source and binary forms
Author: andrew
Date: Tue Feb 4 12:33:00 2020
New Revision: 357499
URL: https://svnweb.freebsd.org/changeset/base/357499
Log:
Print useful debug data on unhandled kernel fault on arm64
When panicing because of an unhandled data abort from the kernel it is
useful to know the register
Author: andrew
Date: Mon Feb 3 14:38:19 2020
New Revision: 357448
URL: https://svnweb.freebsd.org/changeset/base/357448
Log:
Remove the GICv3 ITS irq and replace it with an ID
In r357324 most of the use of gi_irq was moved to gi_lpi. Complete this
with the last few places we need the
Author: andrew
Date: Mon Feb 3 13:50:55 2020
New Revision: 357445
URL: https://svnweb.freebsd.org/changeset/base/357445
Log:
Use a unique name for the GICv3 ITS vmem
When there are multiple GICv3 ITS devices we don't know which vmem is for
which device. Use device_get_nameunit to get a
Author: andrew
Date: Mon Feb 3 13:47:41 2020
New Revision: 357443
URL: https://svnweb.freebsd.org/changeset/base/357443
Log:
Disable the use of the quantum cache in the GICv3 ITS
This uses UMA to allocate space. It causes issues when there are multiple
ITS devices in the system where
Author: andrew
Date: Fri Jan 31 11:33:11 2020
New Revision: 357330
URL: https://svnweb.freebsd.org/changeset/base/357330
Log:
Call the MAPTI command earlier in the ITS driver
The GICv3 Software Overview suggests when allocating a new MSI/MSI-X
interrupt we need to call MAPD followed by
Author: andrew
Date: Fri Jan 31 10:30:13 2020
New Revision: 357324
URL: https://svnweb.freebsd.org/changeset/base/357324
Log:
Only create one ITS configuration table
When there are multiple ITS devices in the system we would allocate a
configuration table for each, however only one table
Author: andrew
Date: Fri Jan 31 09:51:38 2020
New Revision: 357323
URL: https://svnweb.freebsd.org/changeset/base/357323
Log:
Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables
When mapping MSI/MSI-X interrupts throught he Arm IORT ACPI tables we may
need to ignore an
Author: andrew
Date: Thu Jan 30 18:49:19 2020
New Revision: 357304
URL: https://svnweb.freebsd.org/changeset/base/357304
Log:
Shift the ITS processor ID after reading it.
When using the processor ID value we mask off the low and high bits that
should be zero. Unfortunatly we don't shift
Author: andrew
Date: Thu Jan 9 10:26:36 2020
New Revision: 356550
URL: https://svnweb.freebsd.org/changeset/base/356550
Log:
Add atomic_testandset/clear on arm64.
These will reportedly be used in future uma changes.
MFC after:2 weeks
Sponsored by: DARPA, AFRL
Differential
Author: andrew
Date: Mon Jan 6 20:57:59 2020
New Revision: 356426
URL: https://svnweb.freebsd.org/changeset/base/356426
Log:
Add more Arm arm64 CPU identification values
- Add all the Cortex-A CPU ID register values I can find.
- Add the Neoverse-N1 ID regiser value [1]
- Sort
Author: andrew
Date: Fri Jan 3 10:03:36 2020
New Revision: 356316
URL: https://svnweb.freebsd.org/changeset/base/356316
Log:
Add the 8 and 16 bit atomic load/store functions with a barrier on arm64.
Reviewed by: cem
MFC after:2 weeks
Sponsored by: DARPA, AFRL
Differential
Author: andrew
Date: Thu Jan 2 11:02:09 2020
New Revision: 356269
URL: https://svnweb.freebsd.org/changeset/base/356269
Log:
Add the missing trailing '/' when setting TARGET_ARCH from TARGET
This should fix the build when setting TARGET but not TARGET_ARCH.
Sponsored by: DARPA, AFRL
Author: andrew
Date: Thu Dec 19 08:52:16 2019
New Revision: 355907
URL: https://svnweb.freebsd.org/changeset/base/355907
Log:
Stop speculation past an eret instruction
On arm64 the eret instruction is used to return from an exception handler.
Some implementations may speculate past this
Author: andrew
Date: Thu Dec 12 18:27:54 2019
New Revision: 355659
URL: https://svnweb.freebsd.org/changeset/base/355659
Log:
Add comments and macros to the tcr_el1 setting code to help understand it.
This code is non-obvious when reading for the first time. To help with
understanding of
Author: andrew
Date: Wed Dec 4 18:40:05 2019
New Revision: 355398
URL: https://svnweb.freebsd.org/changeset/base/355398
Log:
Fix the signature for zone_import and zone_release
These are cast to uma_import and uma_release functions. Use the signature
for these in the zone functions.
Author: andrew
Date: Fri Nov 29 16:14:32 2019
New Revision: 355213
URL: https://svnweb.freebsd.org/changeset/base/355213
Log:
Use the VM_MEMATTR macros to describe the MAIR offsets.
Remove the duplicate macros that defined a subset of the VM_MEMATTR values.
While here use VM_MEMATTR
> On 28 Nov 2019, at 08:48, Michal Meloun wrote:
>
>
>
> On 27.11.2019 21:33, Alan Cox wrote:
>> Author: alc
>> Date: Wed Nov 27 20:33:49 2019
>> New Revision: 355145
>> URL: https://svnweb.freebsd.org/changeset/base/355145
>>
>> Log:
>> There is no reason why we need to pin the
Author: andrew
Date: Wed Nov 27 16:52:46 2019
New Revision: 355132
URL: https://svnweb.freebsd.org/changeset/base/355132
Log:
Support kernels larger than EFI_STAGING_SIZE in loader.efi
With a very large kernel or module the staging area may be too small to
hold it. When this is the case
Author: andrew
Date: Thu Nov 21 13:59:01 2019
New Revision: 354952
URL: https://svnweb.freebsd.org/changeset/base/354952
Log:
Disable KCSAN within a panic.
The kernel is single threaded at this point and the panic is more
important.
Sponsored by: DARPA, AFRL
Modified:
Author: andrew
Date: Thu Nov 21 13:22:23 2019
New Revision: 354947
URL: https://svnweb.freebsd.org/changeset/base/354947
Log:
Add kcsan_md_unsupported from NetBSD.
It's used to ignore virtual addresses that may have a different physical
address depending on the CPU.
Sponsored by:
Author: andrew
Date: Thu Nov 21 13:12:58 2019
New Revision: 354946
URL: https://svnweb.freebsd.org/changeset/base/354946
Log:
Fix the bus_space functions with KCSAN on arm64.
Arm64 doesn't define the bus_space_set_multi_stream and
bus_space_set_region_stream functions. Don't try to
Author: andrew
Date: Thu Nov 21 12:29:20 2019
New Revision: 354945
URL: https://svnweb.freebsd.org/changeset/base/354945
Log:
Fix for style(9): use parentheses around return statements.
Reported by: kib
Sponsored by: DARPA, AFRL
Modified:
head/sys/amd64/amd64/machdep.c
Modified:
opt_global.h
KUBSAN opt_global.h
# POSIX kernel options
Modified: head/sys/kern/subr_csan.c
==========
--- head/sys/kern/subr_csan.c Thu Nov 21 08:20:05 2019(r354941)
+++ head/sys/kern/s
Author: andrew
Date: Wed Nov 20 18:00:43 2019
New Revision: 354907
URL: https://svnweb.freebsd.org/changeset/base/354907
Log:
As with r354905 use uint16_t to store aflags on the stack and as function
arguments as the aflags size in vm_page_t has increased.
Sponsored by: DARPA, AFRL
Author: andrew
Date: Wed Nov 20 17:49:58 2019
New Revision: 354905
URL: https://svnweb.freebsd.org/changeset/base/354905
Log:
Use atomic_load_16 to load aflags as it's a uint16_t after r354820.
Sponsored by: DARPA, AFRL
Modified:
head/sys/vm/vm_page.c
Modified: head/sys/vm/vm_page.c
Author: andrew
Date: Wed Nov 20 14:37:48 2019
New Revision: 354894
URL: https://svnweb.freebsd.org/changeset/base/354894
Log:
Import the NetBSD Kernel Concurrency Sanitizer (KCSAN) runtime.
KCSAN is a tool to find concurrent memory access that may race each other.
After a determined
Author: andrew
Date: Tue Nov 19 13:28:59 2019
New Revision: 354853
URL: https://svnweb.freebsd.org/changeset/base/354853
Log:
Return 0 from ptrace_set_pc as it now completes successfully.
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/machdep.c
Modified:
Author: andrew
Date: Tue Nov 19 13:25:46 2019
New Revision: 354852
URL: https://svnweb.freebsd.org/changeset/base/354852
Log:
Allow ptrace to set the probram counter on arm64.
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/machdep.c
Modified: head/sys/arm64/arm64/machdep.c
Author: andrew
Date: Tue Nov 19 10:57:44 2019
New Revision: 354851
URL: https://svnweb.freebsd.org/changeset/base/354851
Log:
Fix the definition of bus_space_read_stream_8 on arm64.
This is currently unused, however will be when the Kernel Concurrency
Sanitizer (KCSAN) is imported from
Author: andrew
Date: Thu Nov 7 17:34:44 2019
New Revision: 354452
URL: https://svnweb.freebsd.org/changeset/base/354452
Log:
Add more 8 and 16 bit variants of the the atomic(9) functions on arm64.
These are direct copies of the 32 bit functions, adjusted ad needed.
While here fix
Author: andrew
Date: Thu Nov 7 17:21:17 2019
New Revision: 354451
URL: https://svnweb.freebsd.org/changeset/base/354451
Log:
Add the missing volatile qualifier in atomic_store_ptr
MFC after:1 week
Sponsored by: DARPA, AFRL
Modified:
head/sys/sys/atomic_common.h
Modified:
Author: andrew
Date: Sun Nov 3 22:17:49 2019
New Revision: 354325
URL: https://svnweb.freebsd.org/changeset/base/354325
Log:
Move the struct debug_monitor_state out of _KERNEL.
Some userland libraries incude machine/pcb.h and this needs the full
definition of struct debug_monitor_state.
Author: andrew
Date: Sun Nov 3 15:42:08 2019
New Revision: 354285
URL: https://svnweb.freebsd.org/changeset/base/354285
Log:
Add support for setting hardware breakpoints from ptrace on arm64.
Implement get/fill_dbregs on arm64. This is used by ptrace with the
PT_GETDBREGS and
Author: andrew
Date: Wed Oct 30 17:32:35 2019
New Revision: 354193
URL: https://svnweb.freebsd.org/changeset/base/354193
Log:
Set the userspace execute never bit on kernel mappings.
Arm64 allows us to create execute only mappings. To make sure userspace is
unable to accidentally execute
Author: andrew
Date: Wed Oct 30 14:05:50 2019
New Revision: 354179
URL: https://svnweb.freebsd.org/changeset/base/354179
Log:
Allow exceptions to be masked when in userspace
We may want to mask exceptions when in userspace. This was previously
impossible as threads are created with all
Author: andrew
Date: Wed Oct 30 13:45:40 2019
New Revision: 354178
URL: https://svnweb.freebsd.org/changeset/base/354178
Log:
Allow the userspace ID register fields to be read from the kernel
To allow consistent values to be used in both the kernel and userspace
create a function for
Author: andrew
Date: Wed Oct 30 12:47:00 2019
New Revision: 354177
URL: https://svnweb.freebsd.org/changeset/base/354177
Log:
Use a lowercase name for arm64 special registers so they don't conflict
with macros of the same name.
Sponsored by: DARPA, AFRL
Modified:
Author: andrew
Date: Wed Oct 30 12:33:36 2019
New Revision: 354176
URL: https://svnweb.freebsd.org/changeset/base/354176
Log:
Move the MRS instruction decode macros to armreg.h
These instructions are used to access the registers described in armreg.h,
and will be used in a future change
Author: andrew
Date: Wed Oct 30 10:51:24 2019
New Revision: 354175
URL: https://svnweb.freebsd.org/changeset/base/354175
Log:
Update the debug monitor handling to work after userspace has started
The debug monitor register state is now stored in a struct and updated
when required.
Author: andrew
Date: Wed Oct 30 10:42:52 2019
New Revision: 354174
URL: https://svnweb.freebsd.org/changeset/base/354174
Log:
Use an array of handlers in the data and instruction aborts
Previously we would call data_abort on all data and instruction aborts
however this is incorrect for
Author: andrew
Date: Wed Oct 30 10:41:10 2019
New Revision: 354173
URL: https://svnweb.freebsd.org/changeset/base/354173
Log:
Fix the armv8 crypto driver after r354170.
Sponsored by: DARPA, AFRL
Modified:
head/sys/crypto/armv8/armv8_crypto.c
Modified:
Author: andrew
Date: Wed Oct 30 10:13:14 2019
New Revision: 354171
URL: https://svnweb.freebsd.org/changeset/base/354171
Log:
Add two files missed in r354170
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/identcpu.c
head/sys/arm64/arm64/machdep.c
Modified:
Author: andrew
Date: Wed Oct 30 10:06:57 2019
New Revision: 354170
URL: https://svnweb.freebsd.org/changeset/base/354170
Log:
Rename the macros to extract a single arm64 ID field.
Because of the previous naming scheme the old ID_AA64PFR0_EL1 macro
collided with a potential macro for the
Author: andrew
Date: Fri Oct 25 14:46:09 2019
New Revision: 354072
URL: https://svnweb.freebsd.org/changeset/base/354072
Log:
Remove the arm4 ID register masks, they are not needed after r353641.
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/include/armreg.h
Modified:
Author: andrew
Date: Fri Oct 25 14:30:27 2019
New Revision: 354070
URL: https://svnweb.freebsd.org/changeset/base/354070
Log:
Make special register names lowercase so they don't conflict with future
ID register macros.
MFC after:2 weeks
Sponsored by: DARPA, AFRL
Modified:
Author: andrew
Date: Wed Oct 23 13:21:15 2019
New Revision: 353920
URL: https://svnweb.freebsd.org/changeset/base/353920
Log:
Stop enabling interrupts when reentering kdb on arm64
When we raise a data abort from the kernel we need to enable interrupts,
however we shouldn't be doing this
> On 22 Oct 2019, at 16:50, Alan Somers <mailto:asom...@freebsd.org>> wrote:
>
> On Wed, Oct 16, 2019 at 7:21 AM Andrew Turner <mailto:and...@freebsd.org>> wrote:
> Author: andrew
> Date: Wed Oct 16 13:21:01 2019
> New Revision: 353640
> URL: https://s
Author: andrew
Date: Wed Oct 16 13:30:28 2019
New Revision: 353641
URL: https://svnweb.freebsd.org/changeset/base/353641
Log:
Use tables to store the information to decode the arm64 ID registers.
Arm updates these with each new architecture revision. To help keep them
updated use a
Author: andrew
Date: Wed Oct 16 13:21:01 2019
New Revision: 353640
URL: https://svnweb.freebsd.org/changeset/base/353640
Log:
Stop leaking information from the kernel through timespec
The timespec struct holds a seconds value in a time_t and a nanoseconds
value in a long. On most
Author: andrew
Date: Mon Oct 14 09:29:56 2019
New Revision: 353487
URL: https://svnweb.freebsd.org/changeset/base/353487
Log:
Sort the id_aa64*_fields arrays to be in alphanumerical order.
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/identcpu.c
Modified:
Author: andrew
Date: Fri Sep 27 16:22:28 2019
New Revision: 352796
URL: https://svnweb.freebsd.org/changeset/base/352796
Log:
Check the vfs option length is valid before accessing through
When a VFS option passed to nmount is present but NULL the kernel will
place an empty option in its
> On 4 Sep 2019, at 21:55, Rebecca Cran wrote:
>
> Author: bcran
> Date: Wed Sep 4 20:55:48 2019
> New Revision: 351831
> URL: https://svnweb.freebsd.org/changeset/base/351831
>
> Log:
> The efifat files are no longer used: remove the code to build them
I use them in a Jenkins instance to
> On 17 Apr 2019, at 17:52, Ian Lepore wrote:
>
> On Wed, 2019-04-17 at 11:23 +0200, Andrew Turner wrote:
>>> On 16 Apr 2019, at 22:04, Emmanuel Vadot wrote:
>>>
>>> Author: manu
>>> Date: Tue Apr 16 20:04:22 2019
>>> New Revision: 346
> On 16 Apr 2019, at 22:04, Emmanuel Vadot wrote:
>
> Author: manu
> Date: Tue Apr 16 20:04:22 2019
> New Revision: 346295
> URL: https://svnweb.freebsd.org/changeset/base/346295
>
> Log:
> arm: Add kern_clocksource.c directly in files.arm
>
> This files is needed and included in all our
Author: andrew
Date: Wed Aug 14 14:31:17 2019
New Revision: 351027
URL: https://svnweb.freebsd.org/changeset/base/351027
Log:
Enable BSD_CRTBEGIN on powerpc
In r342974 jhibbits added support to build crtsavres.o. This was the
blocker for BSD_CRTBEGIN to be enabled there. As such enable
Author: andrew
Date: Tue Jul 23 14:52:46 2019
New Revision: 350242
URL: https://svnweb.freebsd.org/changeset/base/350242
Log:
As with r350241 use the new UL macro on the main register mask.
MFC after:1 week
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/include/armreg.h
Author: andrew
Date: Tue Jul 23 14:40:37 2019
New Revision: 350241
URL: https://svnweb.freebsd.org/changeset/base/350241
Log:
Ensure the arm64 ID register fields are 64 bit types.
Previously only some of the ID register fields were 64 bit. To allow
for a script to generate these mark
Author: andrew
Date: Thu Jul 18 13:58:04 2019
New Revision: 350112
URL: https://svnweb.freebsd.org/changeset/base/350112
Log:
Rename arm64 macros in preperation for a script to generate them.
I have a script to generate most of the ID_AA64* macros from the Arm
XML source [1]. In
> On 3 Jun 2019, at 00:38, Maxim Sobolev wrote:
>
> Author: sobomax
> Date: Sun Jun 2 23:38:19 2019
> New Revision: 348521
> URL: https://svnweb.freebsd.org/changeset/base/348521
>
> Log:
> Fix several places where tool name has been hardcoded:
>
> install -> ${INSTALL}
> mtree
Author: andrew
Date: Tue May 28 10:55:59 2019
New Revision: 348323
URL: https://svnweb.freebsd.org/changeset/base/348323
Log:
The alignment is passed into contigmalloc_domainset in the 7th argument.
KUBSAN was complaining the pointer contigmalloc_domainset returned was
misaligned. Fix
Author: andrew
Date: Tue May 28 09:12:15 2019
New Revision: 348322
URL: https://svnweb.freebsd.org/changeset/base/348322
Log:
Teach the kernel KUBSAN runtime about alignment_assumption
This checks the alignment of a given pointer is sufficient for the
requested alignment asked for. This
Author: andrew
Date: Wed May 1 17:12:49 2019
New Revision: 346996
URL: https://svnweb.freebsd.org/changeset/base/346996
Log:
Restore x18 in efi_arch_leave.
Some UEFI implementations trash this register and, as we use it as a
platform register, the kernel doesn't save it before calling
> On 17 Apr 2019, at 17:52, Ian Lepore wrote:
>
> On Wed, 2019-04-17 at 11:23 +0200, Andrew Turner wrote:
>>> On 16 Apr 2019, at 22:04, Emmanuel Vadot wrote:
>>>
>>> Author: manu
>>> Date: Tue Apr 16 20:04:22 2019
>>> New Revision: 346
> On 16 Apr 2019, at 22:04, Emmanuel Vadot wrote:
>
> Author: manu
> Date: Tue Apr 16 20:04:22 2019
> New Revision: 346295
> URL: https://svnweb.freebsd.org/changeset/base/346295
>
> Log:
> arm: Add kern_clocksource.c directly in files.arm
>
> This files is needed and included in all our
Author: andrew
Date: Mon Mar 25 18:02:04 2019
New Revision: 345510
URL: https://svnweb.freebsd.org/changeset/base/345510
Log:
Sort printing of the ID registers on arm64 to be identical to the
documentation. This will simplify checking new fields when they are added.
MFC after:2 weeks
Author: andrew
Date: Thu Feb 28 14:40:43 2019
New Revision: 344659
URL: https://svnweb.freebsd.org/changeset/base/344659
Log:
Add the hw.ncpu tunable to arm64.
This allows us to limit the number of CPUs to use, e.g. to debug problems
seen when enabling multiple clusters.
Reviewed
Author: andrew
Date: Mon Feb 25 13:15:34 2019
New Revision: 344517
URL: https://svnweb.freebsd.org/changeset/base/344517
Log:
Check the index hasn't changed after writing the cmp entry.
If an interrupt fires while writing the cmp entry we may have a partial
entry. Work around this by
Author: andrew
Date: Thu Feb 21 10:11:15 2019
New Revision: 344432
URL: https://svnweb.freebsd.org/changeset/base/344432
Log:
Allow the kcov buffer to be mmaped multiple times.
After r344391 this restriction is no longer needed.
Sponsored by: DARPA, AFRL
Modified:
Author: andrew
Date: Thu Feb 21 09:43:14 2019
New Revision: 344429
URL: https://svnweb.freebsd.org/changeset/base/344429
Log:
Use KCOV_ENTRY_SIZE for the entry size.
Previously it was sizeof(uint64_t). While this is currently true, it may
not be on all future architectures.
Author: andrew
Date: Wed Feb 20 22:41:14 2019
New Revision: 344391
URL: https://svnweb.freebsd.org/changeset/base/344391
Log:
Unwire the kcov buffer when freeing the info struct.
Without this the physical memory will not be returned to the kernel.
While here call vm_object_reference
Author: andrew
Date: Wed Feb 20 22:32:28 2019
New Revision: 344390
URL: https://svnweb.freebsd.org/changeset/base/344390
Log:
Call pmap_qenter for each page when creating the kcov buffer.
This removes the need to allocate a buffer to hold the vm_page_t objects
at the cost of extra IPIs
Author: andrew
Date: Tue Feb 19 17:03:34 2019
New Revision: 344279
URL: https://svnweb.freebsd.org/changeset/base/344279
Log:
Create a common function to handle freeing the kcov info struct.
Both places that may free the kcov info struct are identical. Create a new
common function to
Author: andrew
Date: Fri Feb 8 16:18:17 2019
New Revision: 343913
URL: https://svnweb.freebsd.org/changeset/base/343913
Log:
Fix the spelling of cov_unregister_pc.
When unregistering kcov from the coverage interface we should use the
unregister function, not the register function.
Author: andrew
Date: Thu Feb 7 20:58:45 2019
New Revision: 343876
URL: https://svnweb.freebsd.org/changeset/base/343876
Log:
Add missing data barriers after storeing a new valid pagetable entry.
When moving from an invalid to a valid entry we don't need to invalidate
the tlb, however we
Author: andrew
Date: Thu Feb 7 20:50:39 2019
New Revision: 343875
URL: https://svnweb.freebsd.org/changeset/base/343875
Log:
Add a missing data barrier to the start of arm64_tlb_flushID.
We need to ensure the page table store has happened before the tlbi.
Reported by: jchandra
This should be fixed in r343746.
Andrew
> On 4 Feb 2019, at 05:28, Li-Wen Hsu wrote:
>
> On Sun, Feb 3, 2019 at 8:46 PM Andrew Turner wrote:
>>
>> Author: andrew
>> Date: Sun Feb 3 12:46:27 2019
>> New Revision: 343713
>> URL: https://svnweb.freeb
Author: andrew
Date: Mon Feb 4 16:55:24 2019
New Revision: 343746
URL: https://svnweb.freebsd.org/changeset/base/343746
Log:
Only enable trace-cmp on Clang and modern GCC.
It's was only added to GCC 8.1 so don't try to enable it for earlier
releases.
Reported by: lwhsu
Sponsored
Author: andrew
Date: Sun Feb 3 12:46:27 2019
New Revision: 343713
URL: https://svnweb.freebsd.org/changeset/base/343713
Log:
Enable COVERAGE and KCOV by default on arm64 and amd64.
This allows userspace to trace the kernel using the coverage sanitizer
found in clang. It will also allow
Author: andrew
Date: Tue Jan 29 11:04:17 2019
New Revision: 343550
URL: https://svnweb.freebsd.org/changeset/base/343550
Log:
Extract the coverage sanitizer KPI to a new file.
This will allow multiple consumers of the coverage data to be compiled
into the kernel together. The only
Author: andrew
Date: Tue Jan 15 09:48:18 2019
New Revision: 343042
URL: https://svnweb.freebsd.org/changeset/base/343042
Log:
Ensure the I-Cache is correctly handled in arm64_icache_sync_range
The cache_handle_range macro to handle the arm64 instruction and data
cache operations would
Author: andrew
Date: Sat Jan 12 20:41:57 2019
New Revision: 342973
URL: https://svnweb.freebsd.org/changeset/base/342973
Log:
Fix the check for the offset of td_frame and td_emuldata in struct thread.
Pointy hat: andrew
Sponsored by: DARPA, AFRL
Modified:
head/sys/kern/kern_thread.c
Author: andrew
Date: Sat Jan 12 11:50:39 2019
New Revision: 342963
URL: https://svnweb.freebsd.org/changeset/base/342963
Log:
Temporarily disable the kcov tests. Not all architectures have
atomic_store_64 and atomic_store_64.
Sponsored by: DARPA, AFRL
Modified:
"struct thread KBI td_frame");
-_Static_assert(offsetof(struct thread, td_emuldata) == 0x528,
+_Static_assert(offsetof(struct thread, td_emuldata) == 0x530,
"struct thread KBI td_emuldata");
_Static_assert(offsetof(struct proc, p_flag) == 0xb0,
"struct proc KBI
Author: andrew
Date: Fri Jan 11 11:32:46 2019
New Revision: 342937
URL: https://svnweb.freebsd.org/changeset/base/342937
Log:
Fix the location of td->td_frame at the top of the kernel stack.
In cpu_thread_alloc we would allocate space for the trap frame at the top of
the kernel stack.
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