svn commit: r346016 - in head: lib/clang lib/clang/include/llvm/Config lib/clang/libllvm share/man/man5 share/mk tools/build/options

Author: mhorne Date: Sun Apr 7 18:24:26 2019 New Revision: 346016 URL: https://svnweb.freebsd.org/changeset/base/346016 Log: Add option to build LLVM RISC-V target Reviewed by: emaste, dim Approved by: markj (mentor) MFC after:3 weeks Differential Revision:

svn commit: r346021 - in head/sys/riscv: include riscv

Author: mhorne Date: Sun Apr 7 20:12:24 2019 New Revision: 346021 URL: https://svnweb.freebsd.org/changeset/base/346021 Log: RISC-V: initialize pcpu slightly earlier In certain scenarios, it is possible for PCPU data to be accessed before it has been initialized (e.g. during printf if

svn commit: r345417 - in head: share/misc usr.bin/calendar/calendars

ov\nmelif...@freebsd.org\n2011/10/04"] +mhorne [label="Mitchell Horne\nmho...@freebsd.org\n2019/03/20"] miwi [label="Martin Wilke\nm...@freebsd.org\n2011/02/18\n2018/06/14"] mizhka [label="Michael Zhilin\nmiz...@freebsd.org\n2016/07/19"] mjacob [label="M

Re: svn commit: r348886 - in head/sys/riscv: include riscv

On Mon, Jun 10, 2019 at 9:12 PM Ian Lepore wrote: > > On Tue, 2019-06-11 at 00:55 +, Mitchell Horne wrote: > > Author: mhorne > > Date: Tue Jun 11 00:55:54 2019 > > New Revision: 348886 > > URL: https://svnweb.freebsd.org/changeset/base/348886 > > > >

svn commit: r348887 - head/usr.bin/procstat

Author: mhorne Date: Tue Jun 11 00:59:46 2019 New Revision: 348887 URL: https://svnweb.freebsd.org/changeset/base/348887 Log: procstat: Recognize HWCAP and HWCAP2 with auxv command The two most recent additions to the elf auxiliary vector are HWCAP and HWCAP2 which describe platform

svn commit: r348886 - in head/sys/riscv: include riscv

Author: mhorne Date: Tue Jun 11 00:55:54 2019 New Revision: 348886 URL: https://svnweb.freebsd.org/changeset/base/348886 Log: RISC-V: expose extension bits in AT_HWCAP AT_HWCAP is a field in the elf auxiliary vector meant to describe cpu-specific hardware features. For RISC-V we want to

svn commit: r348838 - head/sys/riscv/riscv

Author: mhorne Date: Sun Jun 9 15:48:36 2019 New Revision: 348838 URL: https://svnweb.freebsd.org/changeset/base/348838 Log: RISC-V: Announce real and available memory at boot Most architectures print their total (real) and available memory during boot. Properly initialize the realmem

svn commit: r348840 - head/sys/riscv/riscv

Author: mhorne Date: Sun Jun 9 15:52:26 2019 New Revision: 348840 URL: https://svnweb.freebsd.org/changeset/base/348840 Log: Remove unused mcall_trap() function The mcall_trap() dummy function is unused, and should be removed as we are unlikely to support M-mode traps any time soon.

svn commit: r348836 - in head/sys: conf riscv/include riscv/riscv

Author: mhorne Date: Sun Jun 9 15:43:38 2019 New Revision: 348836 URL: https://svnweb.freebsd.org/changeset/base/348836 Log: Fix global pointer relaxations in the RISC-V kernel The gp register is intended to used by the linker as another means of performing relaxations, and should point

svn commit: r348835 - head/sys/riscv/riscv

Author: mhorne Date: Sun Jun 9 15:36:51 2019 New Revision: 348835 URL: https://svnweb.freebsd.org/changeset/base/348835 Log: Remove block of dead code Approved by: markj (mentor) Modified: head/sys/riscv/riscv/exception.S Modified: head/sys/riscv/riscv/exception.S

svn commit: r348837 - head/sys/riscv/riscv

Author: mhorne Date: Sun Jun 9 15:45:48 2019 New Revision: 348837 URL: https://svnweb.freebsd.org/changeset/base/348837 Log: Add TSLOG events to initriscv() Add the enter and exit events, similar to what's found in hammer_time() on amd64. We must use TSRAW as the pcpu isn't yet

svn commit: r348839 - head/sys/riscv/conf

Author: mhorne Date: Sun Jun 9 15:50:35 2019 New Revision: 348839 URL: https://svnweb.freebsd.org/changeset/base/348839 Log: RISC-V: Clean up some GENERIC options Some of the config options that are disabled by default seem to be only for historical reasons. Enable those that appear to

svn commit: r349481 - head/sys/sys

Author: mhorne Date: Fri Jun 28 00:03:29 2019 New Revision: 349481 URL: https://svnweb.freebsd.org/changeset/base/349481 Log: Add some missing RISC-V ELF defines This adds defines for the RISC-V specific e_flags values, and some of the missing static relocations. Reviewed by: markj

svn commit: r349482 - in head/contrib/elftoolchain: common readelf

Author: mhorne Date: Fri Jun 28 00:10:26 2019 New Revision: 349482 URL: https://svnweb.freebsd.org/changeset/base/349482 Log: readelf: Add support for RISC-V specific e_flags Reviewed by: markj Approved by: markj (mentor) MFC after:3 days Differential Revision:

svn commit: r349483 - head/contrib/elftoolchain/libelftc

Author: mhorne Date: Fri Jun 28 00:14:12 2019 New Revision: 349483 URL: https://svnweb.freebsd.org/changeset/base/349483 Log: libelftc: add RISC-V bfd targets This adds the following targets: elf32-riscv, elf64-riscv, elf64-riscv-freebsd Reviewed by: emaste, markj,

Re: svn commit: r349482 - in head/contrib/elftoolchain: common readelf

On Fri, Jun 28, 2019 at 12:45 PM John Baldwin wrote: > > On 6/27/19 5:10 PM, Mitchell Horne wrote: > > Author: mhorne > > Date: Fri Jun 28 00:10:26 2019 > > New Revision: 349482 > > URL: https://svnweb.freebsd.org/changeset/base/349482 > > > > Log: >

svn commit: r346016 - in head: lib/clang lib/clang/include/llvm/Config lib/clang/libllvm share/man/man5 share/mk tools/build/options

Author: mhorne Date: Sun Apr 7 18:24:26 2019 New Revision: 346016 URL: https://svnweb.freebsd.org/changeset/base/346016 Log: Add option to build LLVM RISC-V target Reviewed by: emaste, dim Approved by: markj (mentor) MFC after:3 weeks Differential Revision:

svn commit: r346021 - in head/sys/riscv: include riscv

Author: mhorne Date: Sun Apr 7 20:12:24 2019 New Revision: 346021 URL: https://svnweb.freebsd.org/changeset/base/346021 Log: RISC-V: initialize pcpu slightly earlier In certain scenarios, it is possible for PCPU data to be accessed before it has been initialized (e.g. during printf if

svn commit: r352430 - in head/sys/riscv: conf riscv

Author: mhorne Date: Mon Sep 16 22:17:16 2019 New Revision: 352430 URL: https://svnweb.freebsd.org/changeset/base/352430 Log: RISC-V: Support EARLY_AP_STARTUP The EARLY_AP_STARTUP option initializes non-boot processors much sooner during startup. This adds support for this option on

svn commit: r352033 - head/share/mk

Author: mhorne Date: Sun Sep 8 19:40:52 2019 New Revision: 352033 URL: https://svnweb.freebsd.org/changeset/base/352033 Log: Allow for compiler versions >= 10 Both clang and gcc development branches have reached version 10. Since we only parse for a single digit in the major version

svn commit: r352034 - head/sys/conf

Author: mhorne Date: Sun Sep 8 19:44:21 2019 New Revision: 352034 URL: https://svnweb.freebsd.org/changeset/base/352034 Log: RISC-V: fix kernel CFLAGS with clang Use the -march and -mabi flags for both gcc and clang as they are compatible. Specify the "medium" code model separately as

svn commit: r352035 - head/sys/riscv/riscv

Author: mhorne Date: Sun Sep 8 19:46:34 2019 New Revision: 352035 URL: https://svnweb.freebsd.org/changeset/base/352035 Log: Remove a duplicate KTR entry Reviewed by: markj Approved by: markj (mentor) Differential Revision:https://reviews.freebsd.org/D21438 Modified:

svn commit: r352036 - head/sys/riscv/riscv

Author: mhorne Date: Sun Sep 8 19:53:11 2019 New Revision: 352036 URL: https://svnweb.freebsd.org/changeset/base/352036 Log: Fix compilation of locore.S with clang The branch from _start to mpentry has to cross a large section of data; an offset larger than can be specified with a

svn commit: r352048 - head/lib/libc/sys

Author: mhorne Date: Sun Sep 8 21:37:52 2019 New Revision: 352048 URL: https://svnweb.freebsd.org/changeset/base/352048 Log: Fix cpuwhich_t column width Not bumping .Dd since this is purely a format change. Approved by: markj (mentor) Modified: head/lib/libc/sys/cpuset.2

svn commit: r352729 - head/sys/riscv/riscv

Author: mhorne Date: Thu Sep 26 00:54:07 2019 New Revision: 352729 URL: https://svnweb.freebsd.org/changeset/base/352729 Log: Cleanup of elf_machdep.c Fix some style(9) violations. This also changes the name of the machine-dependent sysctl kern.debug_kld to debug.kld_reloc, and

svn commit: r352730 - head/sys/riscv/riscv

Author: mhorne Date: Thu Sep 26 00:58:47 2019 New Revision: 352730 URL: https://svnweb.freebsd.org/changeset/base/352730 Log: Fix some broken relocation handling In a few cases, the symbol lookup is missing before attempting to perform the relocation. While the relocation types affected

svn commit: r349562 - head/contrib/elftoolchain/common

Author: mhorne Date: Sun Jun 30 19:43:13 2019 New Revision: 349562 URL: https://svnweb.freebsd.org/changeset/base/349562 Log: elftoolchain: fix an incorrect e_flags description r349482 introduced the definitions and descriptions of the RISC-V specific e_flags values to elftoolchain.

svn commit: r349563 - head/contrib/elftoolchain/readelf

Author: mhorne Date: Sun Jun 30 19:47:15 2019 New Revision: 349563 URL: https://svnweb.freebsd.org/changeset/base/349563 Log: readelf: Add RISC-V DWARF register aliases This allows DWARF debugging output to use the common register mneumonics, such as ra, sp, or t0. DWARF registers

svn commit: r354259 - head/sys/riscv/conf

Author: mhorne Date: Sat Nov 2 19:33:02 2019 New Revision: 354259 URL: https://svnweb.freebsd.org/changeset/base/354259 Log: RISC-V: Remove EARLY_AP_STARTUP from GENERIC This option is causing boot to fail for the Hifive Unleashed and older versions of QEMU (3.1.1). Remove it from the

svn commit: r354604 - head/sys/riscv/riscv

Author: mhorne Date: Mon Nov 11 01:39:06 2019 New Revision: 354604 URL: https://svnweb.freebsd.org/changeset/base/354604 Log: plic: check for sifive compatible string The Linux dts for the HiFive Unleashed does not contain the usual "riscv,plic0" compat string, but our PLIC driver is

svn commit: r354603 - head/sys/riscv/riscv

Author: mhorne Date: Mon Nov 11 01:35:50 2019 New Revision: 354603 URL: https://svnweb.freebsd.org/changeset/base/354603 Log: plic: fix PLIC_MAX_IRQS The maximum number of PLIC interrupts is defined in the PLIC spec[1] as 1024. [1]

svn commit: r354765 - head/sys/riscv/riscv

Author: mhorne Date: Sat Nov 16 01:25:51 2019 New Revision: 354765 URL: https://svnweb.freebsd.org/changeset/base/354765 Log: RISC-V: busdma_bounce: fix BUS_DMA_ALLOCNOW for non-paged aligned sizes RISC-V inherited this code from arm64, so implement the fix from r354712. See the revision

svn commit: r354717 - head/sys/riscv/riscv

Author: mhorne Date: Fri Nov 15 03:15:14 2019 New Revision: 354717 URL: https://svnweb.freebsd.org/changeset/base/354717 Log: plic: fix context calculation The RISC-V PLIC (platform level interrupt controller) registers are divided up by "context", which is purposefully left ambiguous in

svn commit: r354718 - head/sys/riscv/riscv

(c) 2018 Ruslan Bukin * All rights reserved. + * Copyright (c) 2019 Mitchell Horne * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory (Department of Computer Science and - * Technology) under DARPA contract HR0011-18-C-0016 ("

svn commit: r354719 - head/sys/riscv/include

Author: mhorne Date: Fri Nov 15 03:22:08 2019 New Revision: 354719 URL: https://svnweb.freebsd.org/changeset/base/354719 Log: RISC-V: pass arg6 in sbi_call Allow for an additional argument to sbi_call which will be passed in a6. This is required for SBI spec 0.2 support, as a6 will

svn commit: r354720 - in head/sys: conf riscv/riscv

--- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/riscv/riscv/sbi.c Fri Nov 15 03:34:27 2019(r354720) @@ -0,0 +1,127 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Mitchell Horne + * + * Red

svn commit: r354721 - head/sys/riscv/include

Bukin * All rights reserved. + * Copyright (c) 2019 Mitchell Horne * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract @@ -37,6 +38,35 @@ #ifndef _MACHINE_SBI_H_ #define_MACHINE_SBI_H_

svn commit: r354722 - in head/sys/riscv: include riscv

Author: mhorne Date: Fri Nov 15 03:40:02 2019 New Revision: 354722 URL: https://svnweb.freebsd.org/changeset/base/354722 Log: RISC-V: Print SBI info at startup SBI version 0.2 introduces functions for obtaining the details of the SBI implementation, such as version and implemntation ID.

svn commit: r353711 - head/lib/clang/libllvm

Author: mhorne Date: Fri Oct 18 01:46:38 2019 New Revision: 353711 URL: https://svnweb.freebsd.org/changeset/base/353711 Log: Fix build of LLVM RISC-V backend Reviewed by: dim MFC with: r353358 Differential Revision:https://reviews.freebsd.org/D21963 Modified:

svn commit: r354104 - head/sys/riscv/riscv

Author: mhorne Date: Fri Oct 25 21:39:29 2019 New Revision: 354104 URL: https://svnweb.freebsd.org/changeset/base/354104 Log: RISC-V: skip cpu-map when parsing elf_hwcap The fill_elf_hwcap() function expects to find only cpu nodes under the /cpus entry of the device tree. Newer versions

svn commit: r353334 - head/lib/libthr/arch/riscv/include

Author: mhorne Date: Wed Oct 9 02:02:22 2019 New Revision: 353334 URL: https://svnweb.freebsd.org/changeset/base/353334 Log: RISC-V: Fix an alignment warning in libthr Compiling with clang gives a loss-of-alignment error due the cast to uint8_t *. Since the TLS is always tcb aligned and

svn commit: r357820 - head/sys/riscv/riscv

Author: mhorne Date: Wed Feb 12 13:58:37 2020 New Revision: 357820 URL: https://svnweb.freebsd.org/changeset/base/357820 Log: RISC-V: un-ifdef vm.kvm_size and vm.kvm_free Fix formatting and add CTLFLAG_MPSAFE. Reviewed by: markj Differential Revision:

svn commit: r357821 - head/sys/riscv/riscv

Author: mhorne Date: Wed Feb 12 14:06:02 2020 New Revision: 357821 URL: https://svnweb.freebsd.org/changeset/base/357821 Log: Implement vm.pmap.kernel_maps for RISC-V This is taken from the arm64 version, with the following simplifications: - Our current pmap implementation uses a

svn commit: r357256 - head/sys/dev/cadence

Author: mhorne Date: Wed Jan 29 15:58:19 2020 New Revision: 357256 URL: https://svnweb.freebsd.org/changeset/base/357256 Log: cgem: Add another compat string for the SiFive fu540 Newer device trees use "sifive,fu540-c000-gem" instead of "cdns,macb". Reviewed by: br, kp Differential

svn commit: r357255 - head/sys/riscv/include

Author: mhorne Date: Wed Jan 29 15:50:48 2020 New Revision: 357255 URL: https://svnweb.freebsd.org/changeset/base/357255 Log: Fix definition of SSTATUS_SD The SD bit is defined as the MSB of the sstatus register, meaning its position will vary depending on the CSR's length. Previously,

svn commit: r357371 - head/sys/riscv/sifive

Author: mhorne Date: Sat Feb 1 17:13:52 2020 New Revision: 357371 URL: https://svnweb.freebsd.org/changeset/base/357371 Log: prci: register tlclk as a fixed clock The PRCI exports tlclk as a constant fixed divisor clock, defined as 1/2 of the coreclk frequency. In older FU540 device

svn commit: r357370 - head/sys/riscv/sifive

Author: mhorne Date: Sat Feb 1 17:12:15 2020 New Revision: 357370 URL: https://svnweb.freebsd.org/changeset/base/357370 Log: prci: fix up compat Add two additional compat strings that can be used to identify the PRCI. With newer device trees the PRCI has two parents, hfclk and

svn commit: r357369 - head/sys/riscv/sifive

Author: mhorne Date: Sat Feb 1 17:09:56 2020 New Revision: 357369 URL: https://svnweb.freebsd.org/changeset/base/357369 Log: prci: register the DDR and GEMGX PLLs The PRCI module exports three PLLs. Currently only the coreclk/corepll is registered, so add the logic to register the DDR

Re: svn commit: r357740 - head/usr.sbin/ntp

On Mon, Feb 10, 2020 at 12:17 PM Warner Losh wrote: > > Author: imp > Date: Mon Feb 10 17:17:03 2020 > New Revision: 357740 > URL: https://svnweb.freebsd.org/changeset/base/357740 > > Log: > Refresh architecture list with latest: > > Remove: sparc, sparc64 (twice), ia64, alpha > Add:

svn commit: r356675 - head/sys/riscv/riscv

Author: mhorne Date: Mon Jan 13 03:39:02 2020 New Revision: 356675 URL: https://svnweb.freebsd.org/changeset/base/356675 Log: RISC-V: fix global symbol lookups for mpentry with lld This is a follow up to r356481. In locore.S, before virtual memory is set up, we should avoid using

svn commit: r356835 - head/sys/riscv/riscv

Author: mhorne Date: Fri Jan 17 17:03:25 2020 New Revision: 356835 URL: https://svnweb.freebsd.org/changeset/base/356835 Log: RISC-V: fix global pointer assignment at boot As part of the RISC-V ABI, the gp register is expected to initialized with the address of __global_pointer$ as early

svn commit: r356592 - head/sys/riscv/riscv

Author: mhorne Date: Fri Jan 10 03:17:28 2020 New Revision: 356592 URL: https://svnweb.freebsd.org/changeset/base/356592 Log: Replace inline assembly with rdtime macro This macro is used elsewhere and is slightly cleaner. NFC. Modified: head/sys/riscv/riscv/timer.c Modified:

Re: svn commit: r358556 - in head: libexec/tftpd libexec/tftpd/tests usr.bin/tftp

On Mon, Mar 2, 2020 at 5:19 PM John Baldwin wrote: > > Author: jhb > Date: Mon Mar 2 22:19:30 2020 > New Revision: 358556 > URL: https://svnweb.freebsd.org/changeset/base/358556 > > Log: > Add support for the TFTP windowsize option described in RFC 7440. > > The windowsize option permits

svn commit: r359673 - in head/sys/riscv: include riscv

(empty, because file is newly added) +++ head/sys/riscv/include/metadata.h Mon Apr 6 22:48:43 2020 (r359673) @@ -0,0 +1,35 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Mitchell Horne + * + * Redistribution and use in source and binary forms

svn commit: r360082 - in head/sys: arm/arm arm/include arm64/arm64 conf kern sys

Author: mhorne Date: Sun Apr 19 00:12:30 2020 New Revision: 360082 URL: https://svnweb.freebsd.org/changeset/base/360082 Log: Convert arm's physmem interface to MI code The arm_physmem interface found in arm's MD code provides a convenient set of routines for adding/excluding physical

svn commit: r360083 - in head/sys: conf riscv/include riscv/riscv

Author: mhorne Date: Sun Apr 19 00:18:16 2020 New Revision: 360083 URL: https://svnweb.freebsd.org/changeset/base/360083 Log: RISC-V: use physmem to manage physical memory Replace our hand-rolled functions with the generic ones provided by kern/subr_physmem.c. This greatly simplifies the

svn commit: r360085 - head/sys/riscv/riscv

Author: mhorne Date: Sun Apr 19 00:34:49 2020 New Revision: 360085 URL: https://svnweb.freebsd.org/changeset/base/360085 Log: RISC-V: provide the correct value for kernstart pmap_bootstrap() expects the kernel's physical load address, but we have been providing the start of physical

svn commit: r360084 - head/sys/riscv/riscv

Author: mhorne Date: Sun Apr 19 00:33:05 2020 New Revision: 360084 URL: https://svnweb.freebsd.org/changeset/base/360084 Log: RISC-V: exclude reserved memory regions The device tree may contain a "reserved-memory" node, whose purpose is to communicate sections of physical memory that

svn commit: r360519 - head/usr.sbin/binmiscctl

Author: mhorne Date: Fri May 1 01:31:19 2020 New Revision: 360519 URL: https://svnweb.freebsd.org/changeset/base/360519 Log: Add RISC-V interpreter example Now that RISC-V support has landed in qemu-user-static, add to the list of examples in the binmiscctl(8) manpage. Reviewed by:

svn commit: r360553 - head/sys/riscv/riscv

Author: mhorne Date: Fri May 1 21:58:19 2020 New Revision: 360553 URL: https://svnweb.freebsd.org/changeset/base/360553 Log: Use the HSM SBI extension to start APs The addition of the HSM SBI extension to OpenSBI introduces a new breaking change: secondary harts will remain parked in

svn commit: r360554 - head/sys/riscv/riscv

Author: mhorne Date: Fri May 1 21:59:47 2020 New Revision: 360554 URL: https://svnweb.freebsd.org/changeset/base/360554 Log: Use the HSM SBI extension to halt CPUs Differential Revision:https://reviews.freebsd.org/D24498 Modified: head/sys/riscv/riscv/machdep.c Modified:

svn commit: r360552 - in head/sys/riscv: include riscv

Author: mhorne Date: Fri May 1 21:55:51 2020 New Revision: 360552 URL: https://svnweb.freebsd.org/changeset/base/360552 Log: Add support for HSM SBI extension The Hardware State Management (HSM) extension provides a set of SBI calls that allow the supervisor software to start and stop

svn commit: r360551 - head/sys/riscv/riscv

Author: mhorne Date: Fri May 1 21:52:29 2020 New Revision: 360551 URL: https://svnweb.freebsd.org/changeset/base/360551 Log: Make mpentry independent of _start APs enter the kernel at the same point as the BSP, the _start routine. They then jump to mpentry, but not before storing the

svn commit: r359218 - head/sys/riscv/riscv

Author: mhorne Date: Sun Mar 22 17:59:36 2020 New Revision: 359218 URL: https://svnweb.freebsd.org/changeset/base/359218 Log: Fix ordering of machine includes Remove machine/asm.h since it is unused. Modified: head/sys/riscv/riscv/machdep.c Modified: head/sys/riscv/riscv/machdep.c

svn commit: r359289 - head

Author: mhorne Date: Tue Mar 24 23:25:54 2020 New Revision: 359289 URL: https://svnweb.freebsd.org/changeset/base/359289 Log: Makefile.inc1: override MACHINE for native-xtools For the final step of the native-xtools target, "everything" is built with TARGET and TARGET_ARCH set to the

svn commit: r360826 - head/sys/sys

Author: mhorne Date: Fri May 8 22:21:56 2020 New Revision: 360826 URL: https://svnweb.freebsd.org/changeset/base/360826 Log: Sync relocation definitions Add the most recent relocation types from the RISC-V ELF psABI spec. MFC after:3 days Modified: head/sys/sys/elf_common.h

svn commit: r365304 - head/sys/arm64/include

Author: mhorne Date: Thu Sep 3 17:07:58 2020 New Revision: 365304 URL: https://svnweb.freebsd.org/changeset/base/365304 Log: arm64: update the set of HWCAP definitions This is in sync with what is defined for Linux 5.8. Note that all bits in HWCAP are exhausted, and HWCAP2 has been

svn commit: r365316 - head/sys/rpc/rpcsec_tls

Author: mhorne Date: Thu Sep 3 22:40:51 2020 New Revision: 365316 URL: https://svnweb.freebsd.org/changeset/base/365316 Log: Remove a duplicate declaration This is already declared in sys/file.h, which is included directly. Compiling with GCC9 emits an error. Discussed with:

svn commit: r365455 - in head/sys: dev/xilinx riscv/riscv

Author: mhorne Date: Tue Sep 8 13:21:13 2020 New Revision: 365455 URL: https://svnweb.freebsd.org/changeset/base/365455 Log: RISC-V: fix some mismatched format specifiers RISC-V is currently built with -Wno-format, which is how these went undetected. Address them now before re-enabling

svn commit: r365456 - head/sys/conf

Author: mhorne Date: Tue Sep 8 13:24:44 2020 New Revision: 365456 URL: https://svnweb.freebsd.org/changeset/base/365456 Log: RISC-V: enable MK_FORMAT_EXTENSIONS This option was marked as broken because our riscv64-xtoolchain-gcc package lacked support. Since we are moving away from

Re: svn commit: r365460 - in head/sys/arm64: arm64 include

On Tue, Sep 8, 2020 at 12:36 PM Mitchell Horne wrote: > > Author: mhorne > Date: Tue Sep 8 15:36:38 2020 > New Revision: 365460 > URL: https://svnweb.freebsd.org/changeset/base/365460 > > Log: > arm64: export new HWCAP features > > Expose some of the new

svn commit: r365460 - in head/sys/arm64: arm64 include

Author: mhorne Date: Tue Sep 8 15:36:38 2020 New Revision: 365460 URL: https://svnweb.freebsd.org/changeset/base/365460 Log: arm64: export new HWCAP features Expose some of the new HWCAP features added in r65304. This includes the addition of elf_hwcap2 into the sysvec, and a separate

Re: svn commit: r365449 - head/sbin/rcorder

Hi, I think this change warrants an entry in RELNOTES. Cheers, Mitchell On Tue, Sep 8, 2020 at 7:36 AM Andrey V. Elsukov wrote: > > Author: ae > Date: Tue Sep 8 10:36:11 2020 > New Revision: 365449 > URL: https://svnweb.freebsd.org/changeset/base/365449 > > Log: > Add a few features to

svn commit: r365461 - head/sys/libkern

Author: mhorne Date: Tue Sep 8 15:39:19 2020 New Revision: 365461 URL: https://svnweb.freebsd.org/changeset/base/365461 Log: arm64: check for CRC32 support via HWCAP Doing it this way eliminates the assumption about homogeneous support for the feature, since HWCAP values are only set if

svn commit: r365459 - in head/sys: arm64/include sys

Author: mhorne Date: Tue Sep 8 15:08:20 2020 New Revision: 365459 URL: https://svnweb.freebsd.org/changeset/base/365459 Log: arm64: fix incorrect HWCAP definitions FreeBSD exports CPU features as bits in the AT_HWCAP and AT_HWCAP2 vectors via elf_aux_info(3). This interface is similar

Re: svn commit: r366542 - in head/sys: amd64/amd64 arm/arm arm64/arm64 kern riscv/riscv sys

On Thu, Oct 8, 2020 at 3:15 PM Kyle Evans wrote: > > On Thu, Oct 8, 2020 at 1:02 PM Mitchell Horne wrote: > > > > Author: mhorne > > Date: Thu Oct 8 18:02:05 2020 > > New Revision: 366542 > > URL: https://svnweb.freebsd.org/changeset/base/366542 > >

svn commit: r366542 - in head/sys: amd64/amd64 arm/arm arm64/arm64 kern riscv/riscv sys

Author: mhorne Date: Thu Oct 8 18:02:05 2020 New Revision: 366542 URL: https://svnweb.freebsd.org/changeset/base/366542 Log: Add a routine to dump boot metadata The boot metadata (also referred to as modinfo, or preload metadata) provides information about the size and location of the

Re: svn commit: r366542 - in head/sys: amd64/amd64 arm/arm arm64/arm64 kern riscv/riscv sys

f(sbp, "\tlen:\t%u\n", len); > + sbuf_cat(sbp, "\tvalue:\t"); > + preload_modinfo_value(sbp, bptr, type, len); > + sbuf_putc(sbp, '\n'); > + > + bptr += roundup(len, sizeof(u_long)) / sizeof(uint32_t); &g

svn commit: r366543 - head/sys/kern

Author: mhorne Date: Thu Oct 8 18:29:17 2020 New Revision: 366543 URL: https://svnweb.freebsd.org/changeset/base/366543 Log: Fix a loop condition The correct way to identify the end of the metadata is two adjacent entries set to zero/MODINFO_END. I made a typo and this was checking the

svn commit: r366519 - in head/sys: amd64/amd64 arm/arm arm64/arm64 i386/i386 mips/mips powerpc/powerpc riscv/riscv

Author: mhorne Date: Wed Oct 7 18:48:10 2020 New Revision: 366519 URL: https://svnweb.freebsd.org/changeset/base/366519 Log: Print symbol index for unsupported relocation types It is unlikely, but possible, that an unrecognized or unsupported relocation type is encountered while trying

svn commit: r366737 - in head/sys: amd64/amd64 arm/arm arm64/arm64 riscv/riscv

Author: mhorne Date: Thu Oct 15 20:21:15 2020 New Revision: 366737 URL: https://svnweb.freebsd.org/changeset/base/366737 Log: Simplify preload_dump() condition Hiding this feature behind RB_VERBOSE is gratuitous. The tunable is enough to limit its use to only those who explicitly request

svn commit: r366763 - in head/sys/arm64: arm64 include

Author: mhorne Date: Fri Oct 16 13:35:29 2020 New Revision: 366763 URL: https://svnweb.freebsd.org/changeset/base/366763 Log: Update the ID_AA64MMFR2_EL1 register definitions This brings these definitions in sync with the ARMv8.6 version of the architecture reference manual.

svn commit: r366764 - head/sys/arm64/arm64

Author: mhorne Date: Fri Oct 16 13:37:58 2020 New Revision: 366764 URL: https://svnweb.freebsd.org/changeset/base/366764 Log: arm64: export a few more HWCAPs These were missed in the previous pass. The extensions (partially) supported by this change are: - ARMv8.2-FHM, Floating-point

svn commit: r366794 - head/sys/riscv/riscv

Author: mhorne Date: Sat Oct 17 17:31:06 2020 New Revision: 366794 URL: https://svnweb.freebsd.org/changeset/base/366794 Log: riscv: zero reserved PTE bits for L2 PTEs As was done for L3 PTEs in r362853, mask out the reserved bits when extracting the physical address from an L2 PTE.

svn commit: r366503 - in head/sys: kern sys x86/x86

Author: mhorne Date: Tue Oct 6 23:16:56 2020 New Revision: 366503 URL: https://svnweb.freebsd.org/changeset/base/366503 Log: Remove unused function cpu_boot() The prototype was added with the creation of kern_shutdown.c in r17658, but it appears to have never been implemented. Remove it

svn commit: r366526 - head/sys/kern

Author: mhorne Date: Wed Oct 7 23:14:49 2020 New Revision: 366526 URL: https://svnweb.freebsd.org/changeset/base/366526 Log: Handle kmod local relocation failures gracefully It is possible for elf_reloc_local() to fail in the unlikely case of an unsupported relocation type. If this

svn commit: r366574 - head/sys/riscv/conf

Author: mhorne Date: Fri Oct 9 14:45:41 2020 New Revision: 366574 URL: https://svnweb.freebsd.org/changeset/base/366574 Log: RISC-V LINT kernel config Create the RISC-V NOTES and LINT files. As of r366559, LINT configs are no longer generated but checked in to the tree. Reviewed

svn commit: r364255 - head/sys/arm64/arm64

Author: mhorne Date: Sat Aug 15 15:06:39 2020 New Revision: 364255 URL: https://svnweb.freebsd.org/changeset/base/364255 Log: arm64: parse HWCAP values using user_cpu_desc The hard work of parsing fields per-CPU, handling heterogeneous features, and excluding features from userspace is

svn commit: r364254 - in head/sys/arm64: arm64 include

Author: mhorne Date: Sat Aug 15 14:57:53 2020 New Revision: 364254 URL: https://svnweb.freebsd.org/changeset/base/364254 Log: arm64: update instruction set attribute register definitions This adds definitions for the latest additions to the AA64ISAR[01] ID registers. This brings these

svn commit: r364256 - head/sys/riscv/riscv

Author: mhorne Date: Sat Aug 15 16:15:34 2020 New Revision: 364256 URL: https://svnweb.freebsd.org/changeset/base/364256 Log: RISC-V: copy kernelname from the environment This is allows kern.bootfile to report the correct value. Modified: head/sys/riscv/riscv/machdep.c Modified:

svn commit: r366271 - head/sys/arm64/arm64

Author: mhorne Date: Tue Sep 29 23:21:56 2020 New Revision: 366271 URL: https://svnweb.freebsd.org/changeset/base/366271 Log: arm64: set the correct HWCAP This appears to be a typo. The AdvSIMD field encodes support for half-precision floating point SIMD instructions, which corresponds

svn commit: r365995 - head/sys/riscv/conf

Author: mhorne Date: Tue Sep 22 13:00:02 2020 New Revision: 365995 URL: https://svnweb.freebsd.org/changeset/base/365995 Log: RISC-V: build SiFive drivers and DTB in GENERIC In the spirit of the GENERIC config, we should include the drivers required to run on most supported platforms.

svn commit: r365955 - head/sys/sys

Author: mhorne Date: Mon Sep 21 17:28:41 2020 New Revision: 365955 URL: https://svnweb.freebsd.org/changeset/base/365955 Log: Hide tunable definitions behind _KERNEL Some userspace code include sys/kernel.h. Namely, some OpenZFS tests do this, and it was causing breakage after r365945

svn commit: r365945 - in head: share/man/man9 sys/kern sys/sys

Author: mhorne Date: Mon Sep 21 15:24:44 2020 New Revision: 365945 URL: https://svnweb.freebsd.org/changeset/base/365945 Log: Add getenv(9) boolean parsing functions This adds the getenv_bool() function, to parse a boolean value from a kernel environment variable or tunable. This works

svn commit: r365947 - head/sys/kern

Author: mhorne Date: Mon Sep 21 15:44:23 2020 New Revision: 365947 URL: https://svnweb.freebsd.org/changeset/base/365947 Log: Use getenv_is_true() in init_static_kenv() A small example of how these functions can be used to simplify checks of this nature. Sponsored by: Klara, Inc.

svn commit: r366351 - head/contrib/netbsd-tests/fs

Author: mhorne Date: Fri Oct 2 00:52:31 2020 New Revision: 366351 URL: https://svnweb.freebsd.org/changeset/base/366351 Log: tmpfs tests: check for built-in tmpfs module As of r363471, tmpfs is included in all GENERIC kernel configs. This results in a warning being emitted for each call

svn commit: r365835 - head/sys/modules/dtb/sifive

Author: mhorne Date: Thu Sep 17 14:58:30 2020 New Revision: 365835 URL: https://svnweb.freebsd.org/changeset/base/365835 Log: Add dtb/sifive module This allows building the HiFive Unleashed device tree blob. Reviewed by: manu Differential Revision:

svn commit: r361587 - in head/sys/riscv: include riscv

Author: mhorne Date: Thu May 28 14:56:11 2020 New Revision: 361587 URL: https://svnweb.freebsd.org/changeset/base/361587 Log: Add macros simplifying the fake preload setup This is in preparation for booting via loader(8). Lift these macros from arm64 so we don't need to worry about the

svn commit: r361661 - in head/sys: arm/arm arm/include arm64/arm64 riscv/riscv

Author: mhorne Date: Sun May 31 14:43:04 2020 New Revision: 361661 URL: https://svnweb.freebsd.org/changeset/base/361661 Log: Remove remnant of arm's ELF trampoline The trampoline code used for loading gzipped a.out kernels on arm was removed in r350436. A portion of this code allowed

svn commit: r361402 - head/sys/conf

Author: mhorne Date: Fri May 22 18:54:56 2020 New Revision: 361402 URL: https://svnweb.freebsd.org/changeset/base/361402 Log: Simplify the RISC-V kernel linker invocation Remove our custom SYSTEM_LD definition. This generates program headers that are more consistent with other

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