Author: mmel
Date: Mon Nov 30 17:09:25 2015
New Revision: 291492
URL: https://svnweb.freebsd.org/changeset/base/291492
Log:
ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT
Hiya!
What's the semantics of this?
The mips24k/mips74k cores support a kind of write combining but only
within a cache line - ie, it buffers writes to the same cache line,
then the first non-cacheline access flushes it out. It's for things
like accelerated framebuffer writes. Is this similar to
