Author: mmel
Date: Wed Feb 3 09:15:44 2016
New Revision: 295200
URL: https://svnweb.freebsd.org/changeset/base/295200
Log:
ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.
Deleted:
head/sys/arm/xscale/i80321/
Modified:
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/elf_trampoline.c
head/sys/arm/conf/NOTES
head/sys/arm/include/cpuconf.h
head/sys/arm/include/cpufunc.h
head/sys/arm/xscale/i8134x/i80321reg.h
head/sys/conf/files.arm
head/sys/conf/options.arm
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Wed Feb 3 08:59:12 2016 (r295199)
+++ head/sys/arm/arm/cpufunc.c Wed Feb 3 09:15:44 2016 (r295200)
@@ -60,18 +60,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpuconf.h>
#include <machine/cpufunc.h>
-#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#endif
-
-/*
- * Some definitions in i81342reg.h clash with i80321reg.h.
- * This only happens for the LINT kernel. As it happens,
- * we don't need anything from i81342reg.h that we already
- * got from somewhere else during a LINT compile.
- */
-#if defined(CPU_XSCALE_81342) && !defined(COMPILING_LINT)
+#if defined(CPU_XSCALE_81342)
#include <arm/xscale/i8134x/i81342reg.h>
#endif
@@ -306,9 +295,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
};
#endif /* CPU_MV_PJ4B */
-#if defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
struct cpu_functions xscale_cpufuncs = {
/* CPU functions */
@@ -359,8 +346,7 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */
};
#endif
-/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
- CPU_XSCALE_80219 */
+/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#ifdef CPU_XSCALE_81342
struct cpu_functions xscalec3_cpufuncs = {
@@ -588,10 +574,10 @@ u_int cpu_reset_needs_v4_MMU_disable; /*
#if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || \
- defined(CPU_ARM1176) || defined(CPU_XSCALE_80321) || \
+ defined(CPU_ARM1176) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
+ defined(CPU_XSCALE_81342) || \
defined(CPU_CORTEXA) || defined(CPU_KRAIT)
/* Global cache line sizes, use 32 as default */
@@ -829,18 +815,6 @@ set_cpufuncs()
}
#endif /* CPU_FA526 */
-#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
- if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
- cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
- cputype == CPU_ID_80219_400 || cputype == CPU_ID_80219_600) {
- cpufuncs = xscale_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
- get_cachetype_cp15();
- pmap_pte_init_xscale();
- goto out;
- }
-#endif /* CPU_XSCALE_80321 */
-
#if defined(CPU_XSCALE_81342)
if (cputype == CPU_ID_81342) {
cpufuncs = xscalec3_cpufuncs;
@@ -1207,9 +1181,8 @@ fa526_setup(void)
}
#endif /* CPU_FA526 */
-#if defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_XSCALE_81342)
void
xscale_setup(void)
{
@@ -1276,5 +1249,4 @@ xscale_setup(void)
__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl));
}
-#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
- CPU_XSCALE_80219 */
+#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
Modified: head/sys/arm/arm/elf_trampoline.c
==============================================================================
--- head/sys/arm/arm/elf_trampoline.c Wed Feb 3 08:59:12 2016
(r295199)
+++ head/sys/arm/arm/elf_trampoline.c Wed Feb 3 09:15:44 2016
(r295200)
@@ -67,9 +67,7 @@ extern void fa526_idcache_wbinv_all(void
extern void armv5_ec_idcache_wbinv_all(void);
#elif defined(CPU_ARM1176)
#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
-#elif defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219)
+#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
#define cpu_idcache_wbinv_all xscale_cache_purgeID
extern void xscale_cache_purgeID(void);
#elif defined(CPU_XSCALE_81342)
Modified: head/sys/arm/conf/NOTES
==============================================================================
--- head/sys/arm/conf/NOTES Wed Feb 3 08:59:12 2016 (r295199)
+++ head/sys/arm/conf/NOTES Wed Feb 3 09:15:44 2016 (r295200)
@@ -5,8 +5,6 @@ machine arm
cpu CPU_ARM9
cpu CPU_ARM9E
cpu CPU_FA526
-cpu CPU_XSCALE_80219
-cpu CPU_XSCALE_80321
cpu CPU_XSCALE_81342
cpu CPU_XSCALE_IXP425
cpu CPU_XSCALE_IXP435
Modified: head/sys/arm/include/cpuconf.h
==============================================================================
--- head/sys/arm/include/cpuconf.h Wed Feb 3 08:59:12 2016
(r295199)
+++ head/sys/arm/include/cpuconf.h Wed Feb 3 09:15:44 2016
(r295200)
@@ -53,7 +53,6 @@
#define CPU_NTYPES (defined(CPU_ARM9) +
\
defined(CPU_ARM9E) + \
defined(CPU_ARM1176) + \
- defined(CPU_XSCALE_80321) + \
defined(CPU_XSCALE_PXA2X0) + \
defined(CPU_FA526) + \
defined(CPU_XSCALE_IXP425)) + \
@@ -71,8 +70,7 @@
#endif
#if (defined(CPU_ARM9E) || \
- defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
+ defined(CPU_XSCALE_81342) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
#define ARM_ARCH_5 1
#else
@@ -163,9 +161,8 @@
#define ARM_MMU_V7 0
#endif
-#if (defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
+#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_XSCALE_81342))
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0
@@ -180,11 +177,10 @@
/*
* Step 4: Define features that may be present on a subset of CPUs
*
- * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
+ * ARM_XSCALE_PMU Performance Monitoring Unit on 81342
*/
-#if (defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
+#if (defined(CPU_XSCALE_81342))
#define ARM_XSCALE_PMU 1
#else
#define ARM_XSCALE_PMU 0
Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h Wed Feb 3 08:59:12 2016
(r295199)
+++ head/sys/arm/include/cpufunc.h Wed Feb 3 09:15:44 2016
(r295200)
@@ -342,10 +342,9 @@ void armv5_ec_idcache_wbinv_range(vm_off
#endif
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
- defined(CPU_XSCALE_80321) || \
defined(CPU_FA526) ||
\
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+ defined(CPU_XSCALE_81342)
void armv4_tlb_flushID (void);
void armv4_tlb_flushD (void);
@@ -355,9 +354,8 @@ void armv4_drain_writebuf (void);
void armv4_idcache_inv_all (void);
#endif
-#if defined(CPU_XSCALE_80321) || \
- defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||
\
+ defined(CPU_XSCALE_81342)
void xscale_cpwait (void);
void xscale_cpu_sleep (int mode);
@@ -395,8 +393,7 @@ void xscale_cache_flushD_rng (vm_offset_
void xscale_context_switch (void);
void xscale_setup (void);
-#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
- CPU_XSCALE_80219 */
+#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#ifdef CPU_XSCALE_81342
Modified: head/sys/arm/xscale/i8134x/i80321reg.h
==============================================================================
--- head/sys/arm/xscale/i8134x/i80321reg.h Wed Feb 3 08:59:12 2016
(r295199)
+++ head/sys/arm/xscale/i8134x/i80321reg.h Wed Feb 3 09:15:44 2016
(r295200)
@@ -91,19 +91,9 @@
#define VERDE_MCU_BASE 0x0500
#define VERDE_MCU_SIZE 0x0100
-#if defined(CPU_XSCALE_80321)
-#define VERDE_SSP_BASE 0x0600
-#define VERDE_SSP_SIZE 0x0080
-#endif
-
#define VERDE_PBIU_BASE 0x0680
#define VERDE_PBIU_SIZE 0x0080
-#if defined(CPU_XSCALE_80321)
-#define VERDE_AAU_BASE 0x0800
-#define VERDE_AAU_SIZE 0x0100
-#endif
-
#define VERDE_I2C_BASE 0x1680
#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)
#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20)
@@ -340,21 +330,13 @@
#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0)
#define ICU_INT_bit26 26
-#if defined (CPU_XSCALE_80219)
-#define ICU_INT_bit25 25 /* reserved */
-#else
/* CPU_XSCALE_80321 */
-#define ICU_INT_SSP 25 /* SSP serial port */
-#endif
+//#define ICU_INT_SSP 25 /* SSP serial port */
#define ICU_INT_MUE 24 /* msg unit error */
-#if defined (CPU_XSCALE_80219)
-#define ICU_INT_bit23 23 /* reserved */
-#else
/* CPU_XSCALE_80321 */
-#define ICU_INT_AAUE 23 /* AAU error */
-#endif
+//#define ICU_INT_AAUE 23 /* AAU error */
#define ICU_INT_bit22 22
#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */
@@ -372,14 +354,9 @@
#define ICU_INT_TMR0 9 /* timer 0 */
#define ICU_INT_CPPM 8 /* core processor PMU */
-#if defined(CPU_XSCALE_80219)
-#define ICU_INT_bit7 7 /* reserved */
-#define ICU_INT_bit6 6 /* reserved */
-#else
/* CPU_XSCALE_80321 */
-#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
-#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
-#endif
+//#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
+//#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
#define ICU_INT_bit5 5
#define ICU_INT_bit4 4
@@ -388,81 +365,12 @@
#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */
#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */
-#if defined (CPU_XSCALE_80219)
-#define ICU_INT_HWMASK (0xffffffff & \
- ~((1 << ICU_INT_bit26)
| \
- (1 << ICU_INT_bit25)
| \
- (1 << ICU_INT_bit23)
| \
- (1 << ICU_INT_bit22)
| \
- (1 << ICU_INT_bit7)
| \
- (1 << ICU_INT_bit6)
| \
- (1 << ICU_INT_bit5)
| \
- (1 << ICU_INT_bit4)))
-
-#else
/* CPU_XSCALE_80321 */
-#define ICU_INT_HWMASK (0xffffffff & \
- ~((1 << ICU_INT_bit26) | \
- (1 << ICU_INT_bit22) | \
- (1 << ICU_INT_bit5) | \
- (1 << ICU_INT_bit4)))
-#endif
-
-/*
- * SSP Serial Port
- */
-#if defined (CPU_XSCALE_80321)
-
-#define SSP_SSCR0 0x00 /* SSC control 0 */
-#define SSP_SSCR1 0x04 /* SSC control 1 */
-#define SSP_SSSR 0x08 /* SSP status */
-#define SSP_SSITR 0x0c /* SSP interrupt test */
-#define SSP_SSDR 0x10 /* SSP data */
-
-#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */
-#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph
Iface */
-#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */
-#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */
-#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */
-#define SSP_SSCR0_ECS (1U << 6)/* external clock select */
-#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */
-#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */
- /* bit rate = 3.6864 * 10e6 /
- (2 * (SCR + 1)) */
-
-#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */
-#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */
-#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */
-#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 =
high) */
-#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase:
- 0 = inactive full at start,
- 1/2 at end of frame
- 1 = inactive 1/2 at start,
- full at end of frame */
-#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size:
- 0 = 8 bit
- 1 = 16 bit */
-#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */
-#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */
-#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */
-#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO
select:
- 0 = Tx FIFO
- 1 = Rx FIFO */
-
-#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */
-#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */
-#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */
-#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */
-#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */
-#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */
-#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */
-#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */
-
-#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */
-#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */
-#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */
-
-#endif /* CPU_XSCALE_80321 */
+//#define ICU_INT_HWMASK (0xffffffff & \
+// ~((1 << ICU_INT_bit26) | \
+// (1 << ICU_INT_bit22) | \
+// (1 << ICU_INT_bit5) | \
+// (1 << ICU_INT_bit4)))
/*
* Peripheral Bus Interface Unit
Modified: head/sys/conf/files.arm
==============================================================================
--- head/sys/conf/files.arm Wed Feb 3 08:59:12 2016 (r295199)
+++ head/sys/conf/files.arm Wed Feb 3 09:15:44 2016 (r295200)
@@ -14,14 +14,14 @@ arm/arm/cpufunc_asm.S standard
arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e
arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176
arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176
-arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e |
cpu_fa526 | cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 |
cpu_xscale_80219 | cpu_xscale_81342
+arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e |
cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342
arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e
arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176
arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait |
cpu_mv_pj4b
arm/arm/cpufunc_asm_fa526.S optional cpu_fa526
arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b
arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e
-arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_80321 |
cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
+arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 |
cpu_xscale_ixp425 | cpu_xscale_81342
arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342
arm/arm/cpuinfo.c standard
arm/arm/cpu_asm-v6.S optional armv6
Modified: head/sys/conf/options.arm
==============================================================================
--- head/sys/conf/options.arm Wed Feb 3 08:59:12 2016 (r295199)
+++ head/sys/conf/options.arm Wed Feb 3 09:15:44 2016 (r295200)
@@ -15,8 +15,6 @@ CPU_CORTEXA opt_global.h
CPU_KRAIT opt_global.h
CPU_FA526 opt_global.h
CPU_MV_PJ4B opt_global.h
-CPU_XSCALE_80219 opt_global.h
-CPU_XSCALE_80321 opt_global.h
CPU_XSCALE_81342 opt_global.h
CPU_XSCALE_IXP425 opt_global.h
CPU_XSCALE_IXP435 opt_global.h
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