Re: svn commit: r355188 - in head/riscv: . sifive

2019-12-03 Thread Ravi Pokala 
-Original Message-
From: Emmanuel Vadot 
Date: 2019-12-03, Tuesday at 01:13
To: Ravi Pokala 
Cc: Emmanuel Vadot , , 
, 
Subject: Re: svn commit: r355188 - in head/riscv: . sifive

On Mon, 02 Dec 2019 13:36:06 -0800
Ravi Pokala  wrote:

> Hi Manu,
> 
> This creates a top-level "riscv" directory, but there are no other 
top-level ${TARGET} directories.
> 
> It looks like other *.dts and *.dtsi files live in either
> 
> sys/dts/${TARGET}
> 
> or
> 
> sys/gnu/dts/${TARGET}/(vendor/)?
> 
> So perhaps these should be moved to one of those directories, as 
appropriate?
> 
> Thanks,
> 
> Ravi (rpokala@)

 Thanks, I don't know how I didn't see that ... fixed with revert +
r355324.

Thank you!

-Ravi (rpokala@)

> ?-Original Message-
> From:  on behalf of Emmanuel Vadot 

> Date: 2019-11-28, Thursday at 11:38
> To: , , 

> Subject: svn commit: r355188 - in head/riscv: . sifive
> 
> Author: manu
> Date: Thu Nov 28 19:38:57 2019
> New Revision: 355188
> URL: https://svnweb.freebsd.org/changeset/base/355188
> 
> Log:
>   Import riscv DTS files
>   
>   Requested by: mhorne
> 
> Added:
>   head/riscv/
>  - copied from r355184, vendor/device-tree/dist/src/riscv/
> Replaced:
>   head/riscv/sifive/fu540-c000.dtsi
>  - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi
>   head/riscv/sifive/hifive-unleashed-a00.dts
>  - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts
> 
> Copied: head/riscv/sifive/fu540-c000.dtsi (from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
> 
==
> --- /dev/null 00:00:00 1970   (empty, because file is newly added)
> +++ head/riscv/sifive/fu540-c000.dtsi Thu Nov 28 19:38:57 2019
(r355188, copy of r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include 
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu540-c000", "sifive,fu540";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + ethernet0 = ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,e51", "sifive,rocket0", 
"riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,u54-mc", "sifive,rocket0", 
"riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
>

Re: svn commit: r355188 - in head/riscv: . sifive

2019-12-03 Thread Emmanuel Vadot 
On Mon, 02 Dec 2019 13:36:06 -0800
Ravi Pokala  wrote:

> Hi Manu,
> 
> This creates a top-level "riscv" directory, but there are no other top-level 
> ${TARGET} directories.
> 
> It looks like other *.dts and *.dtsi files live in either
> 
> sys/dts/${TARGET}
> 
> or
> 
> sys/gnu/dts/${TARGET}/(vendor/)?
> 
> So perhaps these should be moved to one of those directories, as appropriate?
> 
> Thanks,
> 
> Ravi (rpokala@)

 Thanks, I don't know how I didn't see that ... fixed with revert +
r355324.

> ?-Original Message-
> From:  on behalf of Emmanuel Vadot 
> 
> Date: 2019-11-28, Thursday at 11:38
> To: , , 
> 
> Subject: svn commit: r355188 - in head/riscv: . sifive
> 
> Author: manu
> Date: Thu Nov 28 19:38:57 2019
> New Revision: 355188
> URL: https://svnweb.freebsd.org/changeset/base/355188
> 
> Log:
>   Import riscv DTS files
>   
>   Requested by: mhorne
> 
> Added:
>   head/riscv/
>  - copied from r355184, vendor/device-tree/dist/src/riscv/
> Replaced:
>   head/riscv/sifive/fu540-c000.dtsi
>  - copied unchanged from r355185, 
> vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi
>   head/riscv/sifive/hifive-unleashed-a00.dts
>  - copied unchanged from r355185, 
> vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts
> 
> Copied: head/riscv/sifive/fu540-c000.dtsi (from r355185, 
> vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
> 
> ==
> --- /dev/null 00:00:00 1970   (empty, because file is newly added)
> +++ head/riscv/sifive/fu540-c000.dtsi Thu Nov 28 19:38:57 2019
> (r355188, copy of r355185, 
> vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include 
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu540-c000", "sifive,fu540";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + ethernet0 = ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,e51", "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-cont

Re: svn commit: r355188 - in head/riscv: . sifive

2019-12-02 Thread Ravi Pokala 
Hi Manu,

This creates a top-level "riscv" directory, but there are no other top-level 
${TARGET} directories.

It looks like other *.dts and *.dtsi files live in either

sys/dts/${TARGET}

or

sys/gnu/dts/${TARGET}/(vendor/)?

So perhaps these should be moved to one of those directories, as appropriate?

Thanks,

Ravi (rpokala@)

-Original Message-
From:  on behalf of Emmanuel Vadot 

Date: 2019-11-28, Thursday at 11:38
To: , , 

Subject: svn commit: r355188 - in head/riscv: . sifive

Author: manu
Date: Thu Nov 28 19:38:57 2019
New Revision: 355188
URL: https://svnweb.freebsd.org/changeset/base/355188

Log:
  Import riscv DTS files
  
  Requested by: mhorne

Added:
  head/riscv/
 - copied from r355184, vendor/device-tree/dist/src/riscv/
Replaced:
  head/riscv/sifive/fu540-c000.dtsi
 - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi
  head/riscv/sifive/hifive-unleashed-a00.dts
 - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts

Copied: head/riscv/sifive/fu540-c000.dtsi (from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)

==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/riscv/sifive/fu540-c000.dtsi   Thu Nov 28 19:38:57 2019
(r355188, copy of r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include 
+
+/ {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "sifive,fu540-c000", "sifive,fu540";
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart1;
+   ethernet0 = ð0;
+   };
+
+   chosen {
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu0: cpu@0 {
+   compatible = "sifive,e51", "sifive,rocket0", "riscv";
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <16384>;
+   reg = <0>;
+   riscv,isa = "rv64imac";
+   status = "disabled";
+   cpu0_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   };
+   };
+   cpu1: cpu@1 {
+   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <32768>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <32768>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <1>;
+   riscv,isa = "rv64imafdc";
+   tlb-split;
+   cpu1_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   };
+   };
+   cpu2: cpu@2 {
+   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <32768>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <32768>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <2>;
+   riscv,isa = "rv64imafdc";
+   tlb-split;
+   cpu2_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   };
+   };
+   cpu3: cpu@3 {
+