I inadvertently replied just to Peter. Sending to the list to archive
the conversation.
Forwarded Message
Subject: Re: [Cryptech Tech] keystore flash performance
Date: Thu, 23 Feb 2017 13:51:25 -0500
From: Paul Selkirk
To: Peter Stuge
On 02/22/2017 07:57 PM, Peter Stuge wrote
Paul Selkirk wrote:
> I'm not an expert, and I haven't fully re-read the 84 page data sheet
> for the chip, but looking at the timing diagrams, there doesn't seem to
> be any need for a delay between transmitting the command and receiving
> the result, or for a delay before de-selecting the chip,
On måndag 20 februari 2017 kl. 18:14:20 CET Paul Selkirk wrote:
> In the course of reviewing Rob's new keystore architecture (ksng
> branches in the libhal, pkcs11, and stm32 repos), I've been looking at
> performance of the SPI flash chip. In short, most of the poor
> performance is self-inflicted
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Aloha!
Wow, pretty impressive improvement.
Paul Selkirk wrote:
> In the course of reviewing Rob's new keystore architecture (ksng
> branches in the libhal, pkcs11, and stm32 repos), I've been looking
> at performance of the SPI flash chip. In sho
In the course of reviewing Rob's new keystore architecture (ksng
branches in the libhal, pkcs11, and stm32 repos), I've been looking at
performance of the SPI flash chip. In short, most of the poor
performance is self-inflicted.
As originally coded, there were 1ms delays after every SPI operation
