On this -lightly loaded- machine a second lasts two or three seconds
$ while sleep 1; do date; done Tue Oct 28 04:34:04 CST 2014 Tue Oct 28 04:34:06 CST 2014 Tue Oct 28 04:34:08 CST 2014 Tue Oct 28 04:34:11 CST 2014 Tue Oct 28 04:34:13 CST 2014 Tue Oct 28 04:34:15 CST 2014 Tue Oct 28 04:34:17 CST 2014 Tue Oct 28 04:34:20 CST 2014 Tue Oct 28 04:34:22 CST 2014 Tue Oct 28 04:34:24 CST 2014 Tue Oct 28 04:34:26 CST 2014 Tue Oct 28 04:34:28 CST 2014 Tue Oct 28 04:34:31 CST 2014 Tue Oct 28 04:34:33 CST 2014 ^C $ on another machine - the expected: $ while sleep 1; do date; done Tue Oct 28 04:36:34 CST 2014 Tue Oct 28 04:36:35 CST 2014 Tue Oct 28 04:36:36 CST 2014 Tue Oct 28 04:36:37 CST 2014 ^C $ $ top | head load averages: 0.32, 0.35, 0.16repo.neuroservices.com.mx 04:34:46 46 processes: 44 idle, 1 zombie, 1 on processor CPU0 states: 0.0% user, 0.0% nice, 0.7% system, 0.0% interrupt, 99.3% idle CPU1 states: 0.0% user, 0.0% nice, 0.0% system, 0.0% interrupt, 99.9% idle CPU2 states: 0.0% user, 0.0% nice, 0.2% system, 0.0% interrupt, 99.8% idle CPU3 states: 0.0% user, 0.0% nice, 0.1% system, 0.0% interrupt, 99.9% idle Memory: Real: 23M/74M act/tot Free: 1905M Cache: 22M Swap: 0K/2303M PID USERNAME PRI NICE SIZE RES STATE WAIT TIMECPU COMMAND 17912 root 20 1652K 1804K sleep/3 select0:06 0.00% sendmail $ This machine is also an ntp server: $ cat /etc/ntpd.conf # $OpenBSD: ntpd.conf,v 1.11 2009/05/18 16:13:48 stevesk Exp $ # sample ntpd configuration file, see ntpd.conf(5) # Addresses to listen on (ntpd does not listen by default) listen on * # sync to a single server #server ntp.example.org # use a random selection of NTP Pool Time Servers # see http://support.ntp.org/bin/view/Servers/NTPPoolServers servers pool.ntp.org # use a specific local timedelta sensor (radio clock, etc) #sensor nmea0 # use all detected timedelta sensors #sensor * $ any ideas about how to further debug? Thanks dmesg: OpenBSD 5.2 (GENERIC.MP) #368: Wed Aug 1 10:04:49 MDT 2012 dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 2146172928 (2046MB) avail mem = 2066731008 (1970MB) mainbus0 at root bios0 at mainbus0: SMBIOS rev. 2.4 @ 0xfa5b0 (48 entries) bios0: vendor Dell Computer Corporation version A05 date 10/04/2007 bios0: Dell Computer Corporation PowerEdge 860 acpi0 at bios0: rev 2 acpi0: sleep states S0 S4 S5 acpi0: tables DSDT FACP APIC SPCR HPET MCFG SLIC acpi0: wakeup devices PCI0(S5) PES1(S5) PEP0(S5) PXHA(S5) PEP1(S5) PEP2(S5) PCIS(S5) acpitimer0 at acpi0: 3579545 Hz, 24 bits acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 2133.68 MHz cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu0: 4MB 64b/line 16-way L2 cache cpu0: apic clock running at 586MHz cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu1: 4MB 64b/line 16-way L2 cache cpu2 at mainbus0: apid 2 (application processor) cpu2: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu2: 4MB 64b/line 16-way L2 cache cpu3 at mainbus0: apid 3 (application processor) cpu3: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu3: 4MB 64b/line 16-way L2 cache ioapic0 at mainbus0: apid 4 pa 0xfec0, version 20, 24 pins ioapic0: misconfigured as apic 0, remapped to apid 4 acpihpet0 at acpi0: 14318179 Hz acpimcfg0 at acpi0 addr 0xf000, bus 0-63 acpiprt0 at acpi0: bus 0 (PCI0) acpiprt1 at acpi0: bus 1 (PES1) acpiprt2 at acpi0: bus 2 (PEP0) acpiprt3 at acpi0: bus -1 (PXHA) acpiprt4 at acpi0: bus 3 (PEP1) acpiprt5 at acpi0: bus 4 (PEP2) acpiprt6 at acpi0: bus 5 (PCIS) acpicpu0 at acpi0 acpicpu1 at acpi0 acpicpu2 at acpi0 acpicpu3 at acpi0 ipmi at mainbus0 not configured pci0 at mainbus0 bus 0 pchb0 at pci0 dev 0 function 0 Intel E7230 Host rev 0x00 ppb0 at pci0 dev 1 function 0 Intel E7230 PCIE rev 0x00: msi pci1 at ppb0 bus 1 ppb1 at pci0 dev 28 function 0 Intel 82801GB PCIE rev 0x01: msi pci2 at ppb1 bus 2 ppb2 at pci0 dev 28 function 4 Intel 82801G PCIE rev 0x01 pci3 at ppb2 bus 3 bge0 at pci3 dev 0 function 0 Broadcom BCM5721 rev 0x11, BCM5750 B1 (0x4101): apic 4 int 16, address 00:1d:09:f0:f9:83 brgphy0 at bge0 phy 1: BCM5750 10/100/1000baseT PHY, rev. 0 ppb3 at pci0 dev 28 function 5 Intel 82801G
Should we allow to configure twice the same IP?
There's nothing that prevent you to configure the same IPv4 address on different interfaces in the same routing domain. But does it make sense? Index: netinet/in.c === RCS file: /home/ncvs/src/sys/netinet/in.c,v retrieving revision 1.106 diff -u -p -r1.106 in.c --- netinet/in.c7 Oct 2014 08:47:28 - 1.106 +++ netinet/in.c28 Oct 2014 10:23:07 - @@ -616,6 +616,10 @@ in_ifinit(struct ifnet *ifp, struct in_i splsoftassert(IPL_SOFTNET); + /* Make sure this address does not exist in the given rdomain. */ + if (ifa_ifwithaddr(sintosa(sin), ifp-if_rdomain)) + return (EEXIST); + if (newaddr) TAILQ_INSERT_TAIL(in_ifaddr, ia, ia_list);
Re: More than just rtalloc1() - rtalloc(9) + man
On 15/10/14(Wed) 14:20, Martin Pieuchot wrote: So I'd appreciates some eyes on the diff below that touches all the existing rtalloc1() queries. The main change is indeed a rename to finally come back to a function with a sexy name introduced in 4.2BSD but with more goodies: rtalloc(9). But this diff also changes the meaning of the flags passed to this function, in order to simplify the various call afterward. See the manpage below. Here's the conversion observed: rtalloc1() rtalloc(9)What for? -- --- 0 0 no effect RT_NOCLONING 0 no effect RT_REPORT|RT_NOCLONING RT_REPORT notify sockets RT_REPORT RT_REPORT|RT_RESOLVE notify sockets + clone The rational for such change is to have only one flag to *enable* a functionality in order to remove non wanted flags where applicable. Nobody? Index: share/man/man9/Makefile === RCS file: /home/ncvs/src/share/man/man9/Makefile,v retrieving revision 1.220 diff -u -p -r1.220 Makefile --- share/man/man9/Makefile 8 Oct 2014 07:39:46 - 1.220 +++ share/man/man9/Makefile 15 Oct 2014 12:18:38 - @@ -26,8 +26,8 @@ MAN=aml_evalnode.9 atomic_add_int.9 ato panic.9 pci_conf_read.9 pci_intr_map.9 pfind.9 physio.9 pmap.9 \ pool.9 powerhook_establish.9 ppsratecheck.9 printf.9 psignal.9 \ radio.9 arc4random.9 rasops.9 ratecheck.9 resettodr.9 rssadapt.9 \ - rt_ifa_add.9 rt_timer_add.9 route.9 rtable_add.9 rtlabel_id2name.9 \ - rtrequest1.9 rwlock.9 sensor_attach.9 \ + route.9 rt_ifa_add.9 rt_timer_add.9 rtalloc.9 rtable_add.9 \ + rtlabel_id2name.9 rtrequest1.9 rwlock.9 sensor_attach.9 \ shutdownhook_establish.9 tsleep.9 spl.9 startuphook_establish.9 \ socreate.9 sosplice.9 style.9 syscall.9 systrace.9 sysctl_int.9 \ task_add.9 tc_init.9 time.9 timeout.9 tvtohz.9 uiomove.9 uvm.9 \ @@ -323,7 +323,7 @@ MLINKS+=rssadapt.9 ieee80211_rssadapt_ch rssadapt.9 ieee80211_rssadapt_lower_rate.9 \ rssadapt.9 ieee80211_rssadapt_raise_rate.9 \ rssadapt.9 ieee80211_rssadapt_updatestats.9 -MLINKS+=route.9 rt_lookup.9 route.9 rtalloc1.9 route.9 rtfree.9 \ +MLINKS+=route.9 rt_lookup.9 \ route.9 rt_setgate.9 route.9 rtredirect.9 route.9 rtdeletemsg.9 MLINKS+=rt_ifa_add.9 rt_ifa_del.9 rt_ifa_add.9 rt_ifa_addloop.9 \ rt_ifa_add.9 rt_ifa_delloop.9 @@ -332,6 +332,7 @@ MLINKS+=rt_timer_add.9 rt_timer_queue_cr rt_timer_add.9 rt_timer_queue_change.9 \ rt_timer_add.9 rt_timer_queue_destroy.9 \ rt_timer_add.9 rt_timer_remove_all.9 +MLINKS+=rtalloc.9 rtalloc_mpath.9 rtalloc.9 rtfree.9 MLINKS+=rtable_add.9 rtable_exists.9 rtable_add.9 rtable_get.9 \ rtable_add.9 rtable_l2.9 rtable_add.9 rtable_l2set.9 MLINKS+=rtlabel_id2name.9 rtlabel_name2id.9 \ Index: share/man/man9/route.9 === RCS file: /home/ncvs/src/share/man/man9/route.9,v retrieving revision 1.12 diff -u -p -r1.12 route.9 --- share/man/man9/route.914 Oct 2014 10:56:10 - 1.12 +++ share/man/man9/route.915 Oct 2014 12:18:38 - @@ -25,10 +25,6 @@ .In net/route.h .Ft struct rtentry * .Fn rt_lookup struct sockaddr *dst struct sockaddr *mask u_int tableid -.Ft struct rtentry * -.Fn rtalloc1 struct sockaddr *dst int flags u_int tableid -.Ft void -.Fn rtfree struct rtentry *rt .Ft int .Fn rt_setgate struct rtentry *rt0 struct sockaddr *dst \ struct sockaddr *gate u_int tableid @@ -82,10 +78,6 @@ from table and forward a notification message to all .Fa AF_ROUTE sockets. -.It Fn rtfree struct rtentry *rt -Release a reference to -.Fa rt , -freeing it if the reference count drops to 0. .El .Sh RETURN VALUES .Fn rt_setgate @@ -106,7 +98,7 @@ No routing entry for could be found. .It Bq Er ESRCH .Fa rt -is a multipath route that conflicts with existing multipath route. +is a multipath routing entry that conflicts with an existing one. .El .Sh SEE ALSO .Xr route 4 , Index: share/man/man9/rtalloc.9 === RCS file: share/man/man9/rtalloc.9 diff -N share/man/man9/rtalloc.9 --- /dev/null 1 Jan 1970 00:00:00 - +++ share/man/man9/rtalloc.9 15 Oct 2014 12:18:38 - @@ -0,0 +1,78 @@ +.\ $OpenBSD$ +.\ +.\ Copyright (c) 2014 Martin Pieuchot +.\ +.\ Permission to use, copy, modify, and distribute this software for any +.\ purpose with or without fee is hereby granted, provided that the above +.\ copyright notice and this permission notice appear in all copies. +.\ +.\ THE SOFTWARE IS PROVIDED AS IS AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\ WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
Re: On this -lightly loaded- machine a second lasts two or three seconds
On Tue, Oct 28, 2014 at 04:42:55AM -0600, Abel Abraham Camarillo Ojeda wrote: $ while sleep 1; do date; done Tue Oct 28 04:34:04 CST 2014 Tue Oct 28 04:34:06 CST 2014 Tue Oct 28 04:34:08 CST 2014 Tue Oct 28 04:34:11 CST 2014 Tue Oct 28 04:34:13 CST 2014 Tue Oct 28 04:34:15 CST 2014 Tue Oct 28 04:34:17 CST 2014 Tue Oct 28 04:34:20 CST 2014 Tue Oct 28 04:34:22 CST 2014 Tue Oct 28 04:34:24 CST 2014 Tue Oct 28 04:34:26 CST 2014 Tue Oct 28 04:34:28 CST 2014 Tue Oct 28 04:34:31 CST 2014 Tue Oct 28 04:34:33 CST 2014 ^C $ on another machine - the expected: $ while sleep 1; do date; done Tue Oct 28 04:36:34 CST 2014 Tue Oct 28 04:36:35 CST 2014 Tue Oct 28 04:36:36 CST 2014 Tue Oct 28 04:36:37 CST 2014 ^C $ $ top | head load averages: 0.32, 0.35, 0.16repo.neuroservices.com.mx 04:34:46 46 processes: 44 idle, 1 zombie, 1 on processor CPU0 states: 0.0% user, 0.0% nice, 0.7% system, 0.0% interrupt, 99.3% idle CPU1 states: 0.0% user, 0.0% nice, 0.0% system, 0.0% interrupt, 99.9% idle CPU2 states: 0.0% user, 0.0% nice, 0.2% system, 0.0% interrupt, 99.8% idle CPU3 states: 0.0% user, 0.0% nice, 0.1% system, 0.0% interrupt, 99.9% idle Memory: Real: 23M/74M act/tot Free: 1905M Cache: 22M Swap: 0K/2303M PID USERNAME PRI NICE SIZE RES STATE WAIT TIMECPU COMMAND 17912 root 20 1652K 1804K sleep/3 select0:06 0.00% sendmail $ This machine is also an ntp server: $ cat /etc/ntpd.conf # $OpenBSD: ntpd.conf,v 1.11 2009/05/18 16:13:48 stevesk Exp $ # sample ntpd configuration file, see ntpd.conf(5) # Addresses to listen on (ntpd does not listen by default) listen on * # sync to a single server #server ntp.example.org # use a random selection of NTP Pool Time Servers # see http://support.ntp.org/bin/view/Servers/NTPPoolServers servers pool.ntp.org # use a specific local timedelta sensor (radio clock, etc) #sensor nmea0 # use all detected timedelta sensors #sensor * $ any ideas about how to further debug? Thanks dmesg: OpenBSD 5.2 (GENERIC.MP) #368: Wed Aug 1 10:04:49 MDT 2012 Unsupported, upgrade and check again. -Otto dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 2146172928 (2046MB) avail mem = 2066731008 (1970MB) mainbus0 at root bios0 at mainbus0: SMBIOS rev. 2.4 @ 0xfa5b0 (48 entries) bios0: vendor Dell Computer Corporation version A05 date 10/04/2007 bios0: Dell Computer Corporation PowerEdge 860 acpi0 at bios0: rev 2 acpi0: sleep states S0 S4 S5 acpi0: tables DSDT FACP APIC SPCR HPET MCFG SLIC acpi0: wakeup devices PCI0(S5) PES1(S5) PEP0(S5) PXHA(S5) PEP1(S5) PEP2(S5) PCIS(S5) acpitimer0 at acpi0: 3579545 Hz, 24 bits acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 2133.68 MHz cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu0: 4MB 64b/line 16-way L2 cache cpu0: apic clock running at 586MHz cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu1: 4MB 64b/line 16-way L2 cache cpu2 at mainbus0: apid 2 (application processor) cpu2: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu2: 4MB 64b/line 16-way L2 cache cpu3 at mainbus0: apid 3 (application processor) cpu3: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,NXE,LONG,LAHF cpu3: 4MB 64b/line 16-way L2 cache ioapic0 at mainbus0: apid 4 pa 0xfec0, version 20, 24 pins ioapic0: misconfigured as apic 0, remapped to apid 4 acpihpet0 at acpi0: 14318179 Hz acpimcfg0 at acpi0 addr 0xf000, bus 0-63 acpiprt0 at acpi0: bus 0 (PCI0) acpiprt1 at acpi0: bus 1 (PES1) acpiprt2 at acpi0: bus 2 (PEP0) acpiprt3 at acpi0: bus -1 (PXHA) acpiprt4 at acpi0: bus 3 (PEP1) acpiprt5 at acpi0: bus 4 (PEP2) acpiprt6 at acpi0: bus 5 (PCIS) acpicpu0 at acpi0 acpicpu1 at acpi0 acpicpu2 at acpi0 acpicpu3 at acpi0 ipmi at mainbus0 not configured pci0 at mainbus0 bus 0 pchb0 at pci0 dev 0 function 0 Intel E7230 Host rev 0x00 ppb0 at pci0 dev 1 function 0 Intel E7230 PCIE rev 0x00: msi pci1 at ppb0 bus 1 ppb1 at pci0 dev 28 function 0 Intel 82801GB PCIE rev 0x01: msi pci2 at ppb1 bus 2 ppb2 at pci0 dev 28 function 4 Intel
Re: On this -lightly loaded- machine a second lasts two or three seconds
dmesg: OpenBSD 5.2 (GENERIC.MP) #368: Wed Aug 1 10:04:49 MDT 2012 Unsupported, upgrade and check again. -Otto If there are still problems after upgrading, show output of sysctl kern.timecounter.
wrong mac address used with carp and unnumbered carpdevs
so, carp interface with underlaying unnumbered carpdev, i. e.
ifconfig em1 up
ifconfig carp0 carpdev em1 vhid 0 ... 10.0.0.1/24
carp announcements and some stuff like arp goes out with the carp
interface mac address, fine.
however, IP traffic goes out with the carpdev's mac, which is wrong
and leads to problems in places with a strict mac address regime -
exchange points are a typical case.
the culprit is sys/net/if_ethersubr.c ether_output().
The ifp passed to ether_output is (usually) determined by looking up
the route to the destination and grabbing the ifp from it. So in the
numbered carpdev case (em1 10.0.0.x/24, carp 10.0.0.y/32) it'll be the
carpdev (em1 here) right away. In the unnumbered carpdev case, it'll be
the carp interface itself. ether_output has a hack to exchange the carp
ifp with the carpdev's one, to send out the frame on the carpdev and
not the carp if. This little hack is before the src mac address is
determined tho, and that is the bug.
ok?
Index: if_ethersubr.c
===
RCS file: /cvs/src/sys/net/if_ethersubr.c,v
retrieving revision 1.175
diff -u -p -r1.175 if_ethersubr.c
--- if_ethersubr.c 7 Oct 2014 20:23:32 - 1.175
+++ if_ethersubr.c 28 Oct 2014 12:18:36 -
@@ -270,6 +270,8 @@ ether_output(struct ifnet *ifp0, struct
senderr(EBUSY);
#endif
+ esrc = ac-ac_enaddr;
+
#if NCARP 0
if (ifp-if_type == IFT_CARP) {
ifp = ifp-if_carpdev;
@@ -310,7 +312,6 @@ ether_output(struct ifnet *ifp0, struct
time_second rt-rt_rmx.rmx_expire)
senderr(rt == rt0 ? EHOSTDOWN : EHOSTUNREACH);
}
- esrc = ac-ac_enaddr;
switch (dst-sa_family) {
#ifdef INET
--
Henning Brauer, h...@bsws.de, henn...@openbsd.org
BS Web Services GmbH, http://bsws.de, Full-Service ISP
Secure Hosting, Mail and DNS. Virtual Dedicated Servers, Root to Fully Managed
Henning Brauer Consulting, http://henningbrauer.com/
Re: Should we allow to configure twice the same IP?
On 14-10-28 05:55 AM, Martin Pieuchot wrote: There's nothing that prevent you to configure the same IPv4 address on different interfaces in the same routing domain. But does it make sense? Index: netinet/in.c === RCS file: /home/ncvs/src/sys/netinet/in.c,v retrieving revision 1.106 diff -u -p -r1.106 in.c --- netinet/in.c7 Oct 2014 08:47:28 - 1.106 +++ netinet/in.c28 Oct 2014 10:23:07 - @@ -616,6 +616,10 @@ in_ifinit(struct ifnet *ifp, struct in_i splsoftassert(IPL_SOFTNET); + /* Make sure this address does not exist in the given rdomain. */ + if (ifa_ifwithaddr(sintosa(sin), ifp-if_rdomain)) + return (EEXIST); + if (newaddr) TAILQ_INSERT_TAIL(in_ifaddr, ia, ia_list); It might be needful when reconfiguring networks; if I swap two interfaces' IP addresses in /etc/hostname.* and re-run /etc/netstart instead of rebooting, I suspect this might break - I believe there would be a very brief overlap where two interfaces had the same IP address. Come to think of it, I'm not even sure whether this even works or not as-is; any opinions on what would be the canonical approach to swapping IPs between interfaces on a live system? Just do it by hand? Write your own script? Use netstart? Or just reboot? -- -Adam Thompson athom...@athompso.net
Re: On this -lightly loaded- machine a second lasts two or three seconds
On Tue, Oct 28, 2014 at 04:42, Abel Abraham Camarillo Ojeda wrote: $ while sleep 1; do date; done Tue Oct 28 04:34:04 CST 2014 Tue Oct 28 04:34:06 CST 2014 cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 2133.68 MHz One normal CPU. cpu0: apic clock running at 586MHz One crazy fast apic. cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz One crazy fast CPU. Upgrade to a version that has the apic latching bug fixed. Or reboot until the apic is detected properly.
Re: Should we allow to configure twice the same IP?
On 28/10/14(Tue) 08:57, Adam Thompson wrote: On 14-10-28 05:55 AM, Martin Pieuchot wrote: There's nothing that prevent you to configure the same IPv4 address on different interfaces in the same routing domain. But does it make sense? Index: netinet/in.c === RCS file: /home/ncvs/src/sys/netinet/in.c,v retrieving revision 1.106 diff -u -p -r1.106 in.c --- netinet/in.c 7 Oct 2014 08:47:28 - 1.106 +++ netinet/in.c 28 Oct 2014 10:23:07 - @@ -616,6 +616,10 @@ in_ifinit(struct ifnet *ifp, struct in_i splsoftassert(IPL_SOFTNET); +/* Make sure this address does not exist in the given rdomain. */ +if (ifa_ifwithaddr(sintosa(sin), ifp-if_rdomain)) +return (EEXIST); + if (newaddr) TAILQ_INSERT_TAIL(in_ifaddr, ia, ia_list); It might be needful when reconfiguring networks; if I swap two interfaces' IP addresses in /etc/hostname.* and re-run /etc/netstart instead of rebooting, I suspect this might break - I believe there would be a very brief overlap where two interfaces had the same IP address. The scenario you're describing is already broken :) Did you try? Come to think of it, I'm not even sure whether this even works or not as-is; any opinions on what would be the canonical approach to swapping IPs between interfaces on a live system? Just do it by hand? Write your own script? Use netstart? Or just reboot? Nobody published a tool that would do that properly, so for the moment do it by hand or reboot your machine.
Re: pool page colouring
On Tue, Oct 28, 2014 at 16:49, David Gwynne wrote: when i shuffled the locking in pools around, page colouring was left behind. page colouring is where you offset items within a page if you have enough slack space. the previous implementation simply incremented the colour so each new page got the next offset. i didnt do this because the page and its items are now initted outside the lock, so maintaining that curcolour iterator wasnt as easy. this sidesteps the curcolor maintenance by just having each page randomly pick a colour when it's set up. Would it make more sense to use the page address to pick the color?
Re: pool page colouring
On 28 October 2014 17:02, Ted Unangst t...@tedunangst.com wrote: On Tue, Oct 28, 2014 at 16:49, David Gwynne wrote: when i shuffled the locking in pools around, page colouring was left behind. page colouring is where you offset items within a page if you have enough slack space. the previous implementation simply incremented the colour so each new page got the next offset. i didnt do this because the page and its items are now initted outside the lock, so maintaining that curcolour iterator wasnt as easy. this sidesteps the curcolor maintenance by just having each page randomly pick a colour when it's set up. Would it make more sense to use the page address to pick the color? Does it actually still make sense to keep page coloring? Is there still benefit on modern hardware?
Re: pool page colouring
On 29 Oct 2014, at 2:44 am, Mike Belopuhov m...@belopuhov.com wrote: On 28 October 2014 17:02, Ted Unangst t...@tedunangst.com wrote: On Tue, Oct 28, 2014 at 16:49, David Gwynne wrote: when i shuffled the locking in pools around, page colouring was left behind. page colouring is where you offset items within a page if you have enough slack space. the previous implementation simply incremented the colour so each new page got the next offset. i didnt do this because the page and its items are now initted outside the lock, so maintaining that curcolour iterator wasnt as easy. this sidesteps the curcolor maintenance by just having each page randomly pick a colour when it's set up. Would it make more sense to use the page address to pick the color? yeah. or we could derive it from a counter in the pool like the item or page get counters Does it actually still make sense to keep page coloring? Is there still benefit on modern hardware? if you want it to go fast, it would make more sense to set the item alignment in pool_init to the size of the cacheline. colouring would then become irrelevant from a speed perspective. however, if colouring is more about perturbing item addresses then it may still be worth it. eg, if you only fit one item on a page, without colouring your item addresses will always be on a page boundary. moving it around might flush out assumptions about low bits in addresses. i dunno. im fine with either removing colouring altogether or setting it from something else completely. i just want a decision to be made cos right now ph_color isnt set, which is a bug.
Re: On this -lightly loaded- machine a second lasts two or three seconds
On Tue, Oct 28, 2014 at 8:22 AM, Ted Unangst t...@tedunangst.com wrote: On Tue, Oct 28, 2014 at 04:42, Abel Abraham Camarillo Ojeda wrote: $ while sleep 1; do date; done Tue Oct 28 04:34:04 CST 2014 Tue Oct 28 04:34:06 CST 2014 cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 2133.68 MHz One normal CPU. cpu0: apic clock running at 586MHz One crazy fast apic. cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Xeon(R) CPU X3210 @ 2.13GHz, 4693.46 MHz One crazy fast CPU. Upgrade to a version that has the apic latching bug fixed. Or reboot until the apic is detected properly. Will try to update after 5.6 is released :-) Thanks to everyone
