Re: More pchgpio(4)

2022-02-27 Thread James Hastings
On Sun, Oct 10, 2021 at 11:42:31PM +0200, Mark Kettenis wrote:
> > Date: Sat, 9 Oct 2021 22:27:52 +0200 (CEST)
> > From: Mark Kettenis 
> >
> > > Date: Sat, 9 Oct 2021 20:55:10 +0200 (CEST)
> > > From: Mark Kettenis 
> > >
> > > This time adding support for Sunrisepoint-H and Sunrisepoint-LP.
> > > Because of all the failed attempts by Intel to get their 10nm process
> > > under control, this may cover Intel Mobile CPUs marketed as 6th, 7th,
> > > 8th, 9th and 10th generation.  So if you have a Laptop that isn't at
> > > least 5 years old, give this a try if pchgpio(4) doesn't attach.  This
> > > may fix all sorts of issues with keyboards, touchpads or
> > > suspend/resume.
> > >
> > > ok?
> >
> > Updated diff that masks unhandled interrupts like we do in amdgpio(4).
>
> And another update to fix a typo in the pin groups for Sunrisepoint-LP.

Updated again for correct pad size (8 bytes instead of 16).

Index: dev/acpi/pchgpio.c
===
RCS file: /cvs/src/sys/dev/acpi/pchgpio.c,v
retrieving revision 1.10
diff -u -p -r1.10 pchgpio.c
--- dev/acpi/pchgpio.c  21 Dec 2021 20:53:46 -  1.10
+++ dev/acpi/pchgpio.c  27 Feb 2022 09:29:17 -
@@ -107,13 +107,76 @@ struct cfdriver pchgpio_cd = {
 };
 
 const char *pchgpio_hids[] = {
+   "INT344B",
"INT3450",
+   "INT3451",
+   "INT345D",
"INT34BB",
"INT34C5",
"INT34C6",
NULL
 };
 
+/* Sunrisepoint-LP */
+
+const struct pchgpio_group spt_lp_groups[] =
+{
+   /* Community 0 */
+   { 0, 0, 0, 23, 0 }, /* GPP_A */
+   { 0, 1, 24, 47, 24 },   /* GPP_B */
+
+   /* Community 1 */
+   { 1, 0, 48, 71, 48 },   /* GPP_C */
+   { 1, 1, 72, 95, 72 },   /* GPP_D */
+   { 1, 2, 96, 119, 96 },  /* GPP_E */
+   
+   /* Community 3 */
+   { 2, 0, 120, 143, 120 },/* GPP_F */
+   { 2, 1, 144, 151, 144 },/* GPP_G */
+};
+
+const struct pchgpio_device spt_lp_device =
+{
+   .pad_size = 8,
+   .gpi_is = 0x100,
+   .gpi_ie = 0x120,
+   .groups = spt_lp_groups,
+   .ngroups = nitems(spt_lp_groups),
+   .npins = 176,
+};
+
+/* Sunrisepoint-H */
+
+const struct pchgpio_group spt_h_groups[] =
+{
+   /* Community 0 */
+   { 0, 0, 0, 23, 0 }, /* GPP_A */
+   { 0, 1, 24, 47, 24 },   /* GPP_B */
+
+   /* Community 1 */
+   { 1, 0, 48, 71, 48 },   /* GPP_C */
+   { 1, 1, 72, 95, 72 },   /* GPP_D */
+   { 1, 2, 96, 108, 96 },  /* GPP_E */
+   { 1, 3, 109, 132, 120 },/* GPP_F */
+   { 1, 4, 133, 156, 144 },/* GPP_G */
+   { 1, 5, 157, 180, 168 },/* GPP_H */
+
+   /* Community 3 */
+   { 2, 0, 181, 191, 192 },/* GPP_I */
+};
+
+const struct pchgpio_device spt_h_device =
+{
+   .pad_size = 8,
+   .gpi_is = 0x100,
+   .gpi_ie = 0x120,
+   .groups = spt_h_groups,
+   .ngroups = nitems(spt_h_groups),
+   .npins = 224,
+};
+
+/* Cannon Lake-H */
+
 const struct pchgpio_group cnl_h_groups[] =
 {
/* Community 0 */
@@ -146,6 +209,8 @@ const struct pchgpio_device cnl_h_device
.npins = 384,
 };
 
+/* Cannon Lake-LP */
+
 const struct pchgpio_group cnl_lp_groups[] =
 {
/* Community 0 */
@@ -173,6 +238,8 @@ const struct pchgpio_device cnl_lp_devic
.npins = 320,
 };
 
+/* Tiger Lake-LP */
+
 const struct pchgpio_group tgl_lp_groups[] =
 {
/* Community 0 */
@@ -205,6 +272,8 @@ const struct pchgpio_device tgl_lp_devic
.npins = 360,
 };
 
+/* Tiger Lake-H */
+
 const struct pchgpio_group tgl_h_groups[] =
 {
/* Community 0 */
@@ -242,7 +311,10 @@ const struct pchgpio_device tgl_h_device
 };
 
 struct pchgpio_match pchgpio_devices[] = {
+   { "INT344B", _lp_device },
{ "INT3450", _h_device },
+   { "INT3451", _h_device },
+   { "INT345D", _h_device },
{ "INT34BB", _lp_device },
{ "INT34C5", _lp_device },
{ "INT34C6", _h_device },
@@ -465,11 +537,38 @@ pchgpio_intr_establish(void *cookie, int
 }
 
 int
+pchgpio_intr_handle(struct pchgpio_softc *sc, int group, int bit)
+{
+   uint32_t enable;
+   int gpiobase, pin, handled = 0;
+   uint8_t bank, bar;
+
+   bar = sc->sc_device->groups[group].bar;
+   bank = sc->sc_device->groups[group].bank;
+   gpiobase = sc->sc_device->groups[group].gpiobase;
+
+   pin = gpiobase + bit;
+   if (sc->sc_pin_ih[pin].ih_func) {
+   sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
+   handled = 1;
+   } else {
+   /* Mask unhandled interrupt */
+   enable = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
+   sc->sc_device->gpi_ie + bank * 4);
+   enable &= ~(1 << bit);
+   bus_space_write_4(sc->sc_memt[bar], sc->sc_memh[bar],
+   sc->sc_device->gpi_ie + 

patch: ifq_enqueue.9 ifq_deq_begin.9 typo

2021-03-20 Thread James Hastings
Spotted this one while reading ifq_enqueue(9). s/struft/struct.

I grepped the tree for "struft" and found one more in ifq_deq_begin(9).


Index: share/man/man9/ifq_deq_begin.9
===
RCS file: /cvs/src/share/man/man9/ifq_deq_begin.9,v
retrieving revision 1.4
diff -u -p -r1.4 ifq_deq_begin.9
--- share/man/man9/ifq_deq_begin.9  29 May 2020 03:06:09 -  1.4
+++ share/man/man9/ifq_deq_begin.9  20 Mar 2021 18:50:38 -
@@ -24,7 +24,7 @@
 .Nd dequeue an mbuf from an interface sending queue
 .Sh SYNOPSIS
 .In net/if_var.h
-.Ft struft mbuf *
+.Ft struct mbuf *
 .Fn ifq_deq_begin "struct ifqueue *ifq"
 .Ft void
 .Fn ifq_deq_commit "struct ifqueue *ifq" "struct mbuf *m"
Index: share/man/man9/ifq_enqueue.9
===
RCS file: /cvs/src/share/man/man9/ifq_enqueue.9,v
retrieving revision 1.11
diff -u -p -r1.11 ifq_enqueue.9
--- share/man/man9/ifq_enqueue.928 Aug 2020 09:15:16 -  1.11
+++ share/man/man9/ifq_enqueue.920 Mar 2021 18:50:38 -
@@ -34,7 +34,7 @@
 .In net/if_var.h
 .Ft int
 .Fn ifq_enqueue "struct ifqueue *ifq" "struct mbuf *m"
-.Ft struft mbuf *
+.Ft struct mbuf *
 .Fn ifq_dequeue "struct ifqueue *ifq"
 .Ft unsigned int
 .Fn ifq_purge "struct ifqueue *ifq"



Re: Lenovo X1 gen 8 touchpad interrupt: pchgpio(4)

2020-11-03 Thread James Hastings
On 10/14/20, Mark Kettenis  wrote:
>> From: James Hastings 
>> Date: Sun, 11 Oct 2020 03:49:11 -0400 (EDT)
>> 
>> On Thu, 08 Oct 2020 20:29:38 + Mark Kettenis wrote:
>> > Diff below adds a driver for the GPIO controller found on the Intel
>> > 400 Series PCH as found on (for example) the Lenovo X1 gen 8 laptop.
>> > Since I don't have such hardware, I'd appreciate some tests on laptops
>> > that current show:
>> > 
>> > "INT34BB" at acpi0 not configured
>> > 
>> 
>> Thanks for the driver Mark! Compiles fine here but panics like this:
>> ihidev0 at iic0 addr 0x2c gpio 291panic: kernel diagnostic assertion "pin
>> >= 0 && pin < sc->sc_npins" failed: file
>> "/usr/src/sys/dev/acpi/pchgpio.c", line 335
>> 
>> Let me know any way I can help.
> 
> Can you figure out what pin number it is trying to use?
> 
> Thanks,
> 
> Mark
> 
> P.S. Feel free to finish the driver yourself if you have time.  This
>  sort of thing is way easier if you have the hardware.  The
>  hardware itself should be very similar to aplgpio(4).  It's just
>  that the registers moved around a bit and there is a single ACPI
>  device for all the pin "communities" instead of the model of
>  separate ACPI devices for each community that aplgpio(4) uses.
>

Election day surprise! Touchpad now works on my 400 Series laptop INT34BB.

Please test on Sunrisepoint/100 Series INT344B as I do not have that hardware.

The Cannonlake INT34BB controller is numbered as if there are 32 GPIO pins
per group. The real pins are packed together and vary from 8 to 25 pins per
group. In my case, GPIO 291 maps to pin 208, offset 27, bank 1, bar 2 (GPP_E).

dmesg and vmstat -zi included. Interrupt count is after moving cursor to xterm.

Index: arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.494
diff -u -p -u -r1.494 GENERIC
--- arch/amd64/conf/GENERIC 27 Oct 2020 02:39:07 -  1.494
+++ arch/amd64/conf/GENERIC 4 Nov 2020 02:03:06 -
@@ -66,6 +66,7 @@ aplgpio*  at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
 glkgpio*   at acpi?
+pchgpio*   at acpi?
 sdhc*  at acpi?
 acpicbkbd* at acpi?
 acpials*   at acpi?
Index: dev/acpi/files.acpi
===
RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
retrieving revision 1.58
diff -u -p -u -r1.58 files.acpi
--- dev/acpi/files.acpi 27 Oct 2020 02:39:07 -  1.58
+++ dev/acpi/files.acpi 4 Nov 2020 02:03:07 -
@@ -151,6 +151,11 @@ device glkgpio
 attach glkgpio at acpi
 file   dev/acpi/glkgpio.c  glkgpio
 
+# Intel PCH GPIO
+device pchgpio
+attach pchgpio at acpi
+file   dev/acpi/pchgpio.c  pchgpio
+
 # "Intel" Dollar Cove TI PMIC
 device tipmic
 attach tipmic at i2c
Index: dev/acpi/pchgpio.c
===
RCS file: dev/acpi/pchgpio.c
diff -N dev/acpi/pchgpio.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ dev/acpi/pchgpio.c  4 Nov 2020 02:03:07 -
@@ -0,0 +1,415 @@
+/* $OpenBSD$   */
+/*
+ * Copyright (c) 2020 Mark Kettenis
+ * Copyright (c) 2020 James Hastings
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCHGPIO_MAXCOM 4
+
+#define PCHGPIO_CONF_TXSTATE   0x0001
+#define PCHGPIO_CONF_RXSTATE   0x0002
+#define PCHGPIO_CONF_RXINV 0x0080
+#define PCHGPIO_CONF_RXEV_EDGE 0x0200
+#define PCHGPIO_CONF_RXEV_ZERO 0x0400
+#define PCHGPIO_CONF_RXEV_MASK 0x0600
+
+#define PCHGPIO_PADBAR 0x00c
+
+struct pchgpio_group {
+   uint8_t bar;
+   uint8_t bank;
+   uint16_tbase;
+   uint16_tlimit;
+   uint16_toffset;
+   int16_t gpiobase;
+};
+
+struct pchgpio_device {
+   uint16_tpad_own;
+   uint16_tpad_size;
+   uint16_t 

amdgpio(4): acpi_attach_args resources

2020-05-21 Thread James Hastings
correction, s/aaa_memt/aaa_bst[0]/

> stop parsing _CRS and use resources from struct acpi_attach_args.

Index: dev/acpi/amdgpio.c
===
RCS file: /cvs/src/sys/dev/acpi/amdgpio.c,v
retrieving revision 1.2
diff -u -p -r1.2 amdgpio.c
--- dev/acpi/amdgpio.c  26 Jan 2020 00:11:42 -  1.2
+++ dev/acpi/amdgpio.c  22 May 2020 05:22:11 -
@@ -55,11 +55,7 @@ struct amdgpio_softc {
 
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
-   bus_addr_t sc_addr;
-   bus_size_t sc_size;
 
-   int sc_irq;
-   int sc_irq_flags;
void *sc_ih;
 
int sc_npins;
@@ -85,7 +81,6 @@ const char *amdgpio_hids[] = {
NULL
 };
 
-intamdgpio_parse_resources(int, union acpi_resource *, void *);
 intamdgpio_read_pin(void *, int);
 void   amdgpio_write_pin(void *, int, int);
 void   amdgpio_intr_establish(void *, int, int, int (*)(), void *);
@@ -106,13 +101,22 @@ amdgpio_attach(struct device *parent, st
 {
struct acpi_attach_args *aaa = aux;
struct amdgpio_softc *sc = (struct amdgpio_softc *)self;
-   struct aml_value res;
int64_t uid;
 
sc->sc_acpi = (struct acpi_softc *)parent;
sc->sc_node = aaa->aaa_node;
printf(": %s", sc->sc_node->name);
 
+   if (aaa->aaa_naddr < 1) {
+   printf(", no registers\n");
+   return;
+   }
+
+   if (aaa->aaa_nirq < 1) {
+   printf(", no interrupt\n");
+   return;
+   }
+
if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, )) {
printf(", can't find uid\n");
return;
@@ -129,19 +133,6 @@ amdgpio_attach(struct device *parent, st
return;
}
 
-   if (aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, )) {
-   printf(", can't find registers\n");
-   return;
-   }
-
-   aml_parse_resource(, amdgpio_parse_resources, sc);
-   aml_freevalue();
-   printf(" addr 0x%lx/0x%lx", sc->sc_addr, sc->sc_size);
-   if (sc->sc_addr == 0 || sc->sc_size == 0) {
-   printf("\n");
-   return;
-   }
-
sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
M_DEVBUF, M_NOWAIT | M_ZERO);
if (sc->sc_pin_ih == NULL) {
@@ -149,17 +140,18 @@ amdgpio_attach(struct device *parent, st
return;
}
 
-   printf(" irq %d", sc->sc_irq);
+   printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]);
+   printf(" irq %d", aaa->aaa_irq[0]);
 
-   sc->sc_memt = aaa->aaa_memt;
-   if (bus_space_map(sc->sc_memt, sc->sc_addr, sc->sc_size, 0,
+   sc->sc_memt = aaa->aaa_bst[0];
+   if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 0,
>sc_memh)) {
printf(", can't map registers\n");
goto free;
}
 
-   sc->sc_ih = acpi_intr_establish(sc->sc_irq, sc->sc_irq_flags, IPL_BIO,
-   amdgpio_intr, sc, sc->sc_dev.dv_xname);
+   sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0],
+   IPL_BIO, amdgpio_intr, sc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(", can't establish interrupt\n");
goto unmap;
@@ -177,32 +169,9 @@ amdgpio_attach(struct device *parent, st
return;
 
 unmap:
-   bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
+   bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]);
 free:
free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
-}
-
-int
-amdgpio_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
-{
-   struct amdgpio_softc *sc = arg;
-   int type = AML_CRSTYPE(crs);
-
-   switch (type) {
-   case LR_MEM32FIXED:
-   sc->sc_addr = crs->lr_m32fixed._bas;
-   sc->sc_size = crs->lr_m32fixed._len;
-   break;
-   case LR_EXTIRQ:
-   sc->sc_irq = crs->lr_extirq.irq[0];
-   sc->sc_irq_flags = crs->lr_extirq.flags;
-   break;
-   default:
-   printf(" type 0x%x\n", type);
-   break;
-   }
-
-   return 0;
 }
 
 int



amdgpio(4): acpi_attach_args resources

2020-05-21 Thread James Hastings
stop parsing _CRS and use resources from struct acpi_attach_args.

Index: dev/acpi/amdgpio.c
===
RCS file: /cvs/src/sys/dev/acpi/amdgpio.c,v
retrieving revision 1.2
diff -u -p -r1.2 amdgpio.c
--- dev/acpi/amdgpio.c  26 Jan 2020 00:11:42 -  1.2
+++ dev/acpi/amdgpio.c  21 May 2020 04:31:52 -
@@ -55,11 +55,7 @@ struct amdgpio_softc {
 
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
-   bus_addr_t sc_addr;
-   bus_size_t sc_size;
 
-   int sc_irq;
-   int sc_irq_flags;
void *sc_ih;
 
int sc_npins;
@@ -85,7 +81,6 @@ const char *amdgpio_hids[] = {
NULL
 };
 
-intamdgpio_parse_resources(int, union acpi_resource *, void *);
 intamdgpio_read_pin(void *, int);
 void   amdgpio_write_pin(void *, int, int);
 void   amdgpio_intr_establish(void *, int, int, int (*)(), void *);
@@ -106,13 +101,22 @@ amdgpio_attach(struct device *parent, st
 {
struct acpi_attach_args *aaa = aux;
struct amdgpio_softc *sc = (struct amdgpio_softc *)self;
-   struct aml_value res;
int64_t uid;
 
sc->sc_acpi = (struct acpi_softc *)parent;
sc->sc_node = aaa->aaa_node;
printf(": %s", sc->sc_node->name);
 
+   if (aaa->aaa_naddr < 1) {
+   printf(", no registers\n");
+   return;
+   }
+
+   if (aaa->aaa_nirq < 1) {
+   printf(", no interrupt\n");
+   return;
+   }
+
if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, )) {
printf(", can't find uid\n");
return;
@@ -129,19 +133,6 @@ amdgpio_attach(struct device *parent, st
return;
}
 
-   if (aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, )) {
-   printf(", can't find registers\n");
-   return;
-   }
-
-   aml_parse_resource(, amdgpio_parse_resources, sc);
-   aml_freevalue();
-   printf(" addr 0x%lx/0x%lx", sc->sc_addr, sc->sc_size);
-   if (sc->sc_addr == 0 || sc->sc_size == 0) {
-   printf("\n");
-   return;
-   }
-
sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
M_DEVBUF, M_NOWAIT | M_ZERO);
if (sc->sc_pin_ih == NULL) {
@@ -149,17 +140,18 @@ amdgpio_attach(struct device *parent, st
return;
}
 
-   printf(" irq %d", sc->sc_irq);
+   printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]);
+   printf(" irq %d", aaa->aaa_irq[0]);
 
sc->sc_memt = aaa->aaa_memt;
-   if (bus_space_map(sc->sc_memt, sc->sc_addr, sc->sc_size, 0,
+   if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 0,
>sc_memh)) {
printf(", can't map registers\n");
goto free;
}
 
-   sc->sc_ih = acpi_intr_establish(sc->sc_irq, sc->sc_irq_flags, IPL_BIO,
-   amdgpio_intr, sc, sc->sc_dev.dv_xname);
+   sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0],
+   IPL_BIO, amdgpio_intr, sc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(", can't establish interrupt\n");
goto unmap;
@@ -177,32 +169,9 @@ amdgpio_attach(struct device *parent, st
return;
 
 unmap:
-   bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size);
+   bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]);
 free:
free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
-}
-
-int
-amdgpio_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
-{
-   struct amdgpio_softc *sc = arg;
-   int type = AML_CRSTYPE(crs);
-
-   switch (type) {
-   case LR_MEM32FIXED:
-   sc->sc_addr = crs->lr_m32fixed._bas;
-   sc->sc_size = crs->lr_m32fixed._len;
-   break;
-   case LR_EXTIRQ:
-   sc->sc_irq = crs->lr_extirq.irq[0];
-   sc->sc_irq_flags = crs->lr_extirq.flags;
-   break;
-   default:
-   printf(" type 0x%x\n", type);
-   break;
-   }
-
-   return 0;
 }
 
 int



dwiic(4): add gemini lake

2020-04-11 Thread James Hastings
attach dwiic(4) to I2C controllers on intel gemini lake.
tested on an acer spin SP111-33.


Index: dev/pci/dwiic_pci.c
===
RCS file: /cvs/src/sys/dev/pci/dwiic_pci.c,v
retrieving revision 1.10
diff -u -p -u -r1.10 dwiic_pci.c
--- dev/pci/dwiic_pci.c 18 Feb 2020 12:13:40 -  1.10
+++ dev/pci/dwiic_pci.c 10 Apr 2020 06:29:04 -
@@ -77,6 +77,14 @@ const struct pci_matchid dwiic_pci_ids[]
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_1 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_2 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_3 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_4 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_5 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_6 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_7 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_8 },
 };
 
 int



Re: [PATCH] Gemini Lake SoC pcidevs and eMMC

2020-02-05 Thread James Hastings
On 2/4/20, Patrick Wildt  wrote:
> On Wed, Jan 02, 2019 at 08:11:25PM -0500, James Hastings wrote:
>> Hello tech@
>> 
>> I would like to add PCI devices for latest Intel SoC (Gemini Lake).
>> 
>> Included a patch for sdhc(4) too that depends on this to enable eMMC.
>> The Intel eMMC controller does not like bus power going to 0V. There
>> may be other systems (Apollo Lake) that need this quirk too.
>> 
>> With both patches I am booting from internal eMMC on HP Stream 14.
>> 
>> Comments? ok?
> 
> Looks like we forgot this one year old diff.  I think the pcidevs
> change is probably fine.  I will cross-check it and put it in.
> 
> For the sdhc change the diff doesn't apply anymore since we added
> the same if-condition for 100series and apollo lake already.  I
> guess it's time to add gemini lake there as well.
> 

Thanks patrick@ for picking this up.

sdhc(4) changes for gemini lake have already been made.

Rebased diff with additional I2C devices.


Index: dev/pci/pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1915
diff -u -p -r1.1915 pcidevs
--- dev/pci/pcidevs 23 Jan 2020 04:33:54 -  1.1915
+++ dev/pci/pcidevs 5 Feb 2020 04:48:02 -
@@ -4587,9 +4587,40 @@ product INTEL WL_3165_1  0x3165  Dual Ban
 product INTEL WL_3165_20x3166  Dual Band Wireless AC 3165
 product INTEL GLK_UHD_605  0x3184  UHD Graphics 605
 product INTEL GLK_UHD_600  0x3185  UHD Graphics 600
+product INTEL GLK_DPTF 0x318c  Gemini Lake DPTF
+product INTEL GLK_GNA  0x3190  Gemini Lake GNA
+product INTEL GLK_PMC  0x3194  Gemini Lake PMC
+product INTEL GLK_HDA  0x3198  Gemini Lake HD Audio
+product INTEL GLK_XHCI 0x31a8  Gemini Lake xHCI
+product INTEL GLK_I2C_10x31ac  Gemini Lake I2C
+product INTEL GLK_I2C_20x31ae  Gemini Lake I2C
+product INTEL GLK_I2C_30x31b0  Gemini Lake I2C
+product INTEL GLK_I2C_40x31b2  Gemini Lake I2C
+product INTEL GLK_I2C_50x31b4  Gemini Lake I2C
+product INTEL GLK_I2C_60x31b6  Gemini Lake I2C
+product INTEL GLK_I2C_70x31b8  Gemini Lake I2C
+product INTEL GLK_I2C_80x31ba  Gemini Lake I2C
+product INTEL GLK_UART_1   0x31bc  Gemini Lake HSUART
+product INTEL GLK_UART_2   0x31be  Gemini Lake HSUART
+product INTEL GLK_UART_3   0x31c0  Gemini Lake HSUART
+product INTEL GLK_SPI_10x31c2  Gemini Lake SPI
+product INTEL GLK_SPI_20x31c4  Gemini Lake SPI
+product INTEL GLK_SPI_30x31c6  Gemini Lake SPI
 product INTEL GLK_SDMMC0x31ca  Gemini Lake SD/MMC
 product INTEL GLK_EMMC 0x31cc  Gemini Lake eMMC
 product INTEL GLK_SDIO 0x31d0  Gemini Lake SDIO
+product INTEL GLK_SMB  0x31d4  Gemini Lake SMBus
+product INTEL GLK_PCIE_1   0x31d6  Gemini Lake PCIE
+product INTEL GLK_PCIE_2   0x31d7  Gemini Lake PCIE
+product INTEL GLK_PCIE_3   0x31d8  Gemini Lake PCIE
+product INTEL GLK_PCIE_4   0x31d9  Gemini Lake PCIE
+product INTEL GLK_PCIE_5   0x31da  Gemini Lake PCIE
+product INTEL GLK_PCIE_6   0x31db  Gemini Lake PCIE
+product INTEL GLK_WL   0x31dc  Gemini Lake CNVi
+product INTEL GLK_AHCI 0x31e3  Gemini Lake AHCI
+product INTEL GLK_LPC  0x31e8  Gemini Lake LPC
+product INTEL GLK_UART_4   0x31ee  Gemini Lake HSUART
+product INTEL GLK_PCI_HB   0x31f0  Gemini Lake Host
 product INTEL 312440x3200  31244 SATA
 product INTEL 82855PM_HB   0x3340  82855PM Host
 product INTEL 82855PM_AGP  0x3341  82855PM AGP



amd gpio controller

2019-12-21 Thread James Hastings
Hi,

New driver for AMD GPIO controller.

Datasheet is BKDG for AMD family 16h models 30h-3Fh processors.

Testing and feedback appreciated.


Index: share/man/man4/Makefile
===
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.746
diff -u -p -u -r1.746 Makefile
--- share/man/man4/Makefile 17 Dec 2019 23:05:45 -  1.746
+++ share/man/man4/Makefile 21 Dec 2019 08:03:32 -
@@ -10,7 +10,7 @@ MAN=  aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 \
aggr.4 agp.4 \
ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
-   akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 \
+   akbd.4 alipm.4 amas.4 amdgpio.4 amdiic.4 amdpm.4 ami.4 \
amlclock.4 amldwusb.4 amliic.4 amlmmc.4 amlpciephy.4 amlpinctrl.4 \
amlpwm.4 amlreset.4 amlrng.4 amluart.4 amlusbphy.4 \
amphy.4 ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
Index: share/man/man4/acpi.4
===
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.59
diff -u -p -u -r1.59 acpi.4
--- share/man/man4/acpi.4   24 Jun 2019 21:33:27 -  1.59
+++ share/man/man4/acpi.4   21 Dec 2019 08:03:32 -
@@ -90,6 +90,8 @@ ACPI video
 ACPI video output
 .It Xr aibs 4
 ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
+.It Xr amdgpio 4
+AMD GPIO controller
 .It Xr aplgpio 4
 Intel Apollo Lake GPIO controller
 .It Xr bytgpio 4
Index: share/man/man4/amdgpio.4
===
RCS file: share/man/man4/amdgpio.4
diff -N share/man/man4/amdgpio.4
--- /dev/null   1 Jan 1970 00:00:00 -
+++ share/man/man4/amdgpio.421 Dec 2019 08:03:32 -
@@ -0,0 +1,49 @@
+.\"$OpenBSD$
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt AMDGPIO 4
+.Os
+.Sh NAME
+.Nm amdgpio
+.Nd AMD GPIO controller
+.Sh SYNOPSIS
+.Cd "amdgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controller found on AMD chipsets. 
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.7 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt kette...@openbsd.org .
Index: sys/arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.483
diff -u -p -u -r1.483 GENERIC
--- sys/arch/amd64/conf/GENERIC 17 Dec 2019 13:08:54 -  1.483
+++ sys/arch/amd64/conf/GENERIC 21 Dec 2019 08:03:33 -
@@ -60,6 +60,7 @@ acpivideo*at acpi?
 acpivout*  at acpivideo?
 acpipwrres*at acpi?
 aibs*  at acpi?
+amdgpio*   at acpi?
 aplgpio*   at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.186
diff -u -p -u -r1.186 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD  19 Nov 2019 02:01:58 -  1.186
+++ sys/arch/amd64/conf/RAMDISK_CD  21 Dec 2019 08:03:33 -
@@ -40,6 +40,7 @@ acpiec*   at acpi?
 acpiprt*   at acpi?
 acpimadt0  at acpi?
 #acpitz*   at acpi?
+amdgpio*   at acpi?
 aplgpio*   at acpi?
 bytgpio*   at acpi?
 sdhc*  at acpi?
Index: sys/dev/acpi/amdgpio.c
===
RCS file: sys/dev/acpi/amdgpio.c
diff -N sys/dev/acpi/amdgpio.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ sys/dev/acpi/amdgpio.c  21 Dec 2019 08:03:33 -
@@ -0,0 +1,312 @@
+/*     $OpenBSD$   */
+/*
+ * Copyright (c) 2016 Mark Kettenis
+ * Copyright (c) 2019 James Hastings
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or wi

Re: pci_sdhc: Intel eMMC controller fix

2019-11-21 Thread James Hastings
On 11/20/19, Patrick Wildt  wrote:
>
> A bit late, but committed, thanks!  By the way, now that we
> have your glkgpio(4), does that make the SD controller work?
>
> Patrick
>
Thanks.  The SD slot does not work yet.
Needs ACPI gpio bits in pci frontend for card detect.



acpivout(4): fix brightness not going up

2019-11-02 Thread James Hastings
Hi,

Backlight on multiple laptops will go down but not up when using brightness 
keys.
Compare new brightness level to min/max values in sc_bcl[] instead.
Diff below restores backlight up function.

Index: dev/acpi/acpivout.c
===
RCS file: /cvs/src/sys/dev/acpi/acpivout.c,v
retrieving revision 1.14
diff -u -p -u -r1.14 acpivout.c
--- dev/acpi/acpivout.c 21 Oct 2019 16:32:51 -  1.14
+++ dev/acpi/acpivout.c 3 Nov 2019 01:04:27 -
@@ -175,9 +175,9 @@ acpivout_brightness_step(struct acpivout
 
nlevel = acpivout_find_brightness(sc, level + (dir * BRIGHTNESS_STEP));
if (nlevel == level) {
-   if (dir == 1 && (nlevel + 1 < sc->sc_bcl_len))
+   if (dir == 1 && (nlevel + 1 < sc->sc_bcl[sc->sc_bcl_len - 1]))
nlevel++;
-   else if (dir == -1 && (nlevel - 1 >= 0))
+   else if (dir == -1 && (nlevel - 1 >= sc->sc_bcl[0]))
nlevel--;
}
if (nlevel == level)



gemini lake gpio

2019-06-23 Thread James Hastings
New driver for Gemini Lake GPIO controller.

Nearly identical to Apollo Lake with few changes.
Pad configuration is now 16 bytes starting at offset 0x600.

Index: share/man/man4/Makefile
===
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.714
diff -u -p -u -r1.714 Makefile
--- share/man/man4/Makefile 17 Jun 2019 18:28:17 -  1.714
+++ share/man/man4/Makefile 22 Jun 2019 08:49:36 -
@@ -27,7 +27,8 @@ MAN=  aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
eso.4 ess.4 et.4 etherip.4 etphy.4 ex.4 exphy.4 exrtc.4 \
fanpwr.4 fd.4 fdc.4 fec.4 fins.4 fintek.4 fms.4 fusbtc.4 fuse.4 \
fxp.4 gdt.4 gentbi.4 gem.4 gif.4 \
-   glenv.4 gpio.4 gpiodcf.4 gpioiic.4 gpioow.4 gpr.4 gre.4 gscsio.4 \
+   glenv.4 glkgpio.4 gpio.4 gpiodcf.4 gpioiic.4 gpioow.4 \
+   gpr.4 gre.4 gscsio.4 \
hds.4 hiclock.4 hidwusb.4 hifn.4 hil.4 hilid.4 hilkbd.4 hilms.4 \
hireset.4 hitemp.4 hme.4 hotplug.4 hsq.4 \
hvn.4 hvs.4 hyperv.4 \
Index: share/man/man4/acpi.4
===
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.58
diff -u -p -u -r1.58 acpi.4
--- share/man/man4/acpi.4   17 Jun 2019 18:28:17 -  1.58
+++ share/man/man4/acpi.4   22 Jun 2019 08:49:36 -
@@ -100,6 +100,8 @@ AMD cryptographic co-processor
 Intel Cherry View GPIO controller
 .It Xr dwiic 4
 Synopsys DesignWare I2C controller
+.It Xr glkgpio 4
+Intel Gemini Lake GPIO controller
 .It Xr tpm 4
 Trusted Platform Module device
 .El
Index: share/man/man4/glkgpio.4
===
RCS file: share/man/man4/glkgpio.4
diff -N share/man/man4/glkgpio.4
--- /dev/null   1 Jan 1970 00:00:00 -
+++ share/man/man4/glkgpio.422 Jun 2019 08:49:36 -
@@ -0,0 +1,50 @@
+.\"$OpenBSD$
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt GLKGPIO 4
+.Os
+.Sh NAME
+.Nm glkgpio
+.Nd Intel Gemini Lake GPIO controller
+.Sh SYNOPSIS
+.Cd "glkgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controllers found on Intel's Gemini
+Lake SoC.
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt kette...@openbsd.org .
Index: sys/arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.474
diff -u -p -u -r1.474 GENERIC
--- sys/arch/amd64/conf/GENERIC 17 Jun 2019 18:28:17 -  1.474
+++ sys/arch/amd64/conf/GENERIC 22 Jun 2019 08:49:37 -
@@ -64,6 +64,7 @@ aibs* at acpi?
 aplgpio*   at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
+glkgpio*   at acpi?
 sdhc*  at acpi?
 acpicbkbd* at acpi?
 acpials*   at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.180
diff -u -p -u -r1.180 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD  17 Jun 2019 18:28:18 -  1.180
+++ sys/arch/amd64/conf/RAMDISK_CD  22 Jun 2019 08:49:37 -
@@ -47,6 +47,7 @@ bytgpio*  at acpi?
 sdhc*  at acpi?
 acpihve*   at acpi?
 chvgpio*at acpi?
+glkgpio*   at acpi?
 
 mpbios0at bios0
 
Index: sys/dev/acpi/files.acpi
===
RCS file: /cvs/src/sys/dev/acpi/files.acpi,v
retrieving revision 1.51
diff -u -p -u -r1.51 files.acpi
--- sys/dev/acpi/files.acpi 17 Jun 2019 18:28:18 -  1.51
+++ sys/dev/acpi/files.acpi 22 Jun 2019 08:49:39 -
@@ -131,6 +131,11 @@ device chvgpio
 attach chvgpio at acpi
 file   dev/acpi/chvgpio.c  ch

apollo lake gpio

2019-06-17 Thread James Hastings
Index: share/man/man4/Makefile
===
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.713
diff -u -p -u -r1.713 Makefile
--- share/man/man4/Makefile 7 Jun 2019 16:06:59 -   1.713
+++ share/man/man4/Makefile 17 Jun 2019 16:18:15 -
@@ -10,7 +10,7 @@ MAN=  aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
-   ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
+   ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
axe.4 axen.4 axppmic.4 azalia.4 \
Index: share/man/man4/acpi.4
===
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.57
diff -u -p -u -r1.57 acpi.4
--- share/man/man4/acpi.4   23 Apr 2019 20:23:36 -  1.57
+++ share/man/man4/acpi.4   17 Jun 2019 16:18:15 -
@@ -90,6 +90,8 @@ ACPI video
 ACPI video output
 .It Xr aibs 4
 ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
+.It Xr aplgpio 4
+Intel Apollo Lake GPIO controller
 .It Xr bytgpio 4
 Intel Bay Trail GPIO controller
 .It Xr ccp 4
Index: share/man/man4/aplgpio.4
===
RCS file: share/man/man4/aplgpio.4
diff -N share/man/man4/aplgpio.4
--- /dev/null   1 Jan 1970 00:00:00 -
+++ share/man/man4/aplgpio.417 Jun 2019 16:18:15 -
@@ -0,0 +1,50 @@
+.\"$OpenBSD$
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt APLGPIO 4
+.Os
+.Sh NAME
+.Nm aplgpio
+.Nd Intel Apollo Lake GPIO controller
+.Sh SYNOPSIS
+.Cd "aplgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controllers found on Intel's Apollo 
+Lake SoC.
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt kette...@openbsd.org .
Index: sys/arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.473
diff -u -p -u -r1.473 GENERIC
--- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -   1.473
+++ sys/arch/amd64/conf/GENERIC 17 Jun 2019 16:18:16 -
@@ -61,6 +61,7 @@ acpivideo*at acpi?
 acpivout*  at acpivideo?
 acpipwrres*at acpi?
 aibs*  at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
 sdhc*  at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.179
diff -u -p -u -r1.179 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD  4 May 2019 17:59:40 -   1.179
+++ sys/arch/amd64/conf/RAMDISK_CD  17 Jun 2019 16:18:16 -
@@ -42,6 +42,7 @@ acpiec*   at acpi?
 acpiprt*   at acpi?
 acpimadt0  at acpi?
 #acpitz*   at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 sdhc*  at acpi?
 acpihve*   at acpi?
Index: sys/dev/acpi/aplgpio.c
===
RCS file: sys/dev/acpi/aplgpio.c
diff -N sys/dev/acpi/aplgpio.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ sys/dev/acpi/aplgpio.c  17 Jun 2019 16:18:16 -
@@ -0,0 +1,304 @@
+/*     $OpenBSD$   */
+/*
+ * Copyright (c) 2016 Mark Kettenis
+ * Copyright (c) 2019 James Hastings
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permi

sdhc_pci: gpio card detect

2019-06-17 Thread James Hastings
Index: sys/dev/pci/sdhc_pci.c
===
RCS file: /cvs/src/sys/dev/pci/sdhc_pci.c,v
retrieving revision 1.20
diff -u -p -u -r1.20 sdhc_pci.c
--- sys/dev/pci/sdhc_pci.c  30 Apr 2016 11:32:23 -  1.20
+++ sys/dev/pci/sdhc_pci.c  11 Jun 2019 01:31:04 -
@@ -21,6 +21,16 @@
 #include 
 #include 
 
+#include "acpi.h"
+#if NACPI > 0
+#include 
+#include 
+#include 
+#include 
+#include 
+#undef DEVNAME
+#endif
+
 #include 
 #include 
 #include 
@@ -52,6 +62,16 @@ struct sdhc_pci_softc {
pcitag_t sc_tag;
pcireg_t sc_id;
void *sc_ih;
+#if NACPI > 0
+   struct acpi_softc *sc_acpi;
+   struct aml_node *sc_node;
+
+   struct aml_node *sc_gpio_int_node;
+   struct aml_node *sc_gpio_io_node;
+   uint16_t sc_gpio_int_pin;
+   uint16_t sc_gpio_int_flags;
+   uint16_t sc_gpio_io_pin;
+#endif
 };
 
 intsdhc_pci_match(struct device *, void *, void *);
@@ -62,6 +82,17 @@ void sdhc_pci_conf_write(pci_chipset_tag
 void   sdhc_takecontroller(struct pci_attach_args *);
 void   sdhc_ricohfix(struct sdhc_pci_softc *);
 
+#if NACPI > 0
+struct aml_node *acpi_pci_match(struct device *, struct pci_attach_args *);
+intsdhc_pci_card_detect_nonremovable(struct sdhc_softc *);
+intsdhc_pci_card_detect_gpio(struct sdhc_softc *);
+intsdhc_pci_card_detect_intr(void *);
+intsdhc_pci_acpi_parse_resources(int, union acpi_resource *, void *);
+void   sdhc_pci_acpi_get_resources(struct sdhc_pci_softc *);
+void   sdhc_pci_acpi_explore(struct sdhc_pci_softc *);
+void   sdhc_pci_acpi_power_on(struct sdhc_pci_softc *, struct aml_node *);
+#endif
+
 struct cfattach sdhc_pci_ca = {
sizeof(struct sdhc_pci_softc), sdhc_pci_match, sdhc_pci_attach,
NULL, sdhc_pci_activate
@@ -147,6 +178,14 @@ sdhc_pci_attach(struct device *parent, s
}
printf(": %s\n", intrstr);
 
+#if NACPI > 0
+   sc->sc_node = acpi_pci_match(self, pa);
+   if (sc->sc_node != NULL) {
+   sdhc_pci_acpi_get_resources(sc);
+   sdhc_pci_acpi_power_on(sc, sc->sc_node);
+   sdhc_pci_acpi_explore(sc);
+   }
+#endif
/* Enable use of DMA if supported by the interface. */
usedma = PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA;
sc->sc.sc_dmat = pa->pa_dmat;
@@ -257,3 +296,123 @@ sdhc_pci_conf_write(pci_chipset_tag_t pc
tmp |= (val << ((reg & 0x3) * 8));
pci_conf_write(pc, tag, reg & ~0x3, tmp);
 }
+#if NACPI > 0
+int
+sdhc_pci_card_detect_nonremovable(struct sdhc_softc *sc)
+{
+   return 1;
+}
+
+int
+sdhc_pci_card_detect_gpio(struct sdhc_softc *ssc)
+{
+   struct sdhc_pci_softc *sc = (struct sdhc_pci_softc *)ssc;
+   struct acpi_gpio *gpio = sc->sc_gpio_io_node->gpio;
+   uint16_t pin = sc->sc_gpio_io_pin;
+
+   /* Card detect GPIO signal is active-low. */
+   return !gpio->read_pin(gpio->cookie, pin);
+}
+
+int
+sdhc_pci_card_detect_intr(void *arg)
+{
+   struct sdhc_pci_softc *sc = arg;
+
+   sdhc_needs_discover(>sc);
+
+   return 1;
+}
+
+int
+sdhc_pci_acpi_parse_resources(int crsidx, union acpi_resource *crs, void *arg)
+{
+   struct sdhc_pci_softc *sc = arg;
+   int type = AML_CRSTYPE(crs);
+   struct aml_node *node;
+   uint16_t pin;
+
+   switch (type) {
+   case LR_GPIO:
+   node = aml_searchname(sc->sc_node, (char 
*)>pad[crs->lr_gpio.res_off]);
+   pin = *(uint16_t *)>pad[crs->lr_gpio.pin_off];
+   if (crs->lr_gpio.type == LR_GPIO_INT) {
+   sc->sc_gpio_int_node = node;
+   sc->sc_gpio_int_pin = pin;
+   sc->sc_gpio_int_flags = crs->lr_gpio.tflags;
+   } else if (crs->lr_gpio.type == LR_GPIO_IO) {
+   sc->sc_gpio_io_node = node;
+   sc->sc_gpio_io_pin = pin;
+   }
+   }
+
+   return 0;
+}
+
+void
+sdhc_pci_acpi_get_resources(struct sdhc_pci_softc *sc)
+{
+   struct aml_value res;
+
+   aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, );
+   aml_parse_resource(, sdhc_pci_acpi_parse_resources, sc);
+
+   if (sc->sc_gpio_io_node && sc->sc_gpio_io_node->gpio)
+   sc->sc.sc_card_detect = sdhc_pci_card_detect_gpio;
+
+   if (sc->sc_gpio_int_node && sc->sc_gpio_int_node->gpio) {
+   struct acpi_gpio *gpio = sc->sc_gpio_int_node->gpio;
+   gpio->intr_establish(gpio->cookie, sc->sc_gpio_int_pin,
+   sc->sc_gpio_int_flags, sdhc_pci_card_detect_intr, sc);
+   }
+}
+
+void
+sdhc_pci_acpi_power_on(struct sdhc_pci_softc *sc, struct aml_node *node)
+{
+   node = aml_searchname(node, "_PS0");
+   if (node && aml_evalnode(sc->sc_acpi, node, 0, NULL, NULL))
+   printf("%s: _PS0 failed\n", sc->sc.sc_dev.dv_xname);
+}
+
+int
+sdhc_pci_acpi_do_explore(struct aml_node *node, void *arg)
+{
+   struct 

apollo lake gpio

2019-06-17 Thread James Hastings
Index: share/man/man4/Makefile
===
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.713
diff -u -p -u -r1.713 Makefile
--- share/man/man4/Makefile 7 Jun 2019 16:06:59 -   1.713
+++ share/man/man4/Makefile 11 Jun 2019 01:31:02 -
@@ -10,7 +10,7 @@ MAN=  aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
-   ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
+   ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
axe.4 axen.4 axppmic.4 azalia.4 \
Index: share/man/man4/acpi.4
===
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.57
diff -u -p -u -r1.57 acpi.4
--- share/man/man4/acpi.4   23 Apr 2019 20:23:36 -  1.57
+++ share/man/man4/acpi.4   11 Jun 2019 01:31:02 -
@@ -90,6 +90,8 @@ ACPI video
 ACPI video output
 .It Xr aibs 4
 ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
+.It Xr aplgpio 4
+Intel Apollo Lake GPIO controller
 .It Xr bytgpio 4
 Intel Bay Trail GPIO controller
 .It Xr ccp 4
Index: share/man/man4/aplgpio.4
===
RCS file: share/man/man4/aplgpio.4
diff -N share/man/man4/aplgpio.4
--- /dev/null   1 Jan 1970 00:00:00 -
+++ share/man/man4/aplgpio.411 Jun 2019 01:31:02 -
@@ -0,0 +1,49 @@
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt APLGPIO 4
+.Os
+.Sh NAME
+.Nm aplgpio
+.Nd Intel Apollo Lake GPIO controller
+.Sh SYNOPSIS
+.Cd "aplgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controllers found on Intel's Apollo 
+Lake SoC.
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt kette...@openbsd.org .
Index: sys/arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.473
diff -u -p -u -r1.473 GENERIC
--- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -   1.473
+++ sys/arch/amd64/conf/GENERIC 11 Jun 2019 01:31:02 -
@@ -61,6 +61,7 @@ acpivideo*at acpi?
 acpivout*  at acpivideo?
 acpipwrres*at acpi?
 aibs*  at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
 sdhc*  at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.179
diff -u -p -u -r1.179 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD  4 May 2019 17:59:40 -   1.179
+++ sys/arch/amd64/conf/RAMDISK_CD  11 Jun 2019 01:31:02 -
@@ -42,6 +42,7 @@ acpiec*   at acpi?
 acpiprt*   at acpi?
 acpimadt0  at acpi?
 #acpitz*   at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 sdhc*  at acpi?
 acpihve*   at acpi?
Index: sys/dev/acpi/aplgpio.c
===
RCS file: sys/dev/acpi/aplgpio.c
diff -N sys/dev/acpi/aplgpio.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ sys/dev/acpi/aplgpio.c  11 Jun 2019 01:31:03 -
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2016 Mark Kettenis
+ * Copyright (c) 2019 James Hastings
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+

sdmmc: nonremovable card status

2019-06-10 Thread James Hastings
Print nonremovable for cards with that capability set.
Helps differentiate sdmmc buses with eMMC devices at a glance.


Index: sys/dev/sdmmc/sdmmc.c
===
RCS file: /cvs/src/sys/dev/sdmmc/sdmmc.c,v
retrieving revision 1.53
diff -u -p -u -r1.53 sdmmc.c
--- sys/dev/sdmmc/sdmmc.c   2 Apr 2019 07:08:40 -   1.53
+++ sys/dev/sdmmc/sdmmc.c   11 Jun 2019 01:31:05 -
@@ -110,6 +110,8 @@ sdmmc_attach(struct device *parent, stru
printf(", mmc high-speed");
if (ISSET(saa->caps, SMC_CAPS_DMA))
printf(", dma");
+   if (ISSET(saa->caps, SMC_CAPS_NONREMOVABLE))
+   printf(", nonremovable");
printf("\n");

sc->sct = saa->sct;



sdhc_pci: gpio card detect

2019-06-10 Thread James Hastings
I ported the GPIO card detect bits from sdhc_acpi frontend to sdhc_pci.
This feels like a lot of duplicated code, should it be pushed down to
acpi or sdmmc stack?
I tested this in conjunction with apollo lake gpio driver on an Acer
Spin 1.
Card insertion and removal is now detected but card does not enable yet.


Index: sys/dev/pci/sdhc_pci.c
===
RCS file: /cvs/src/sys/dev/pci/sdhc_pci.c,v
retrieving revision 1.20
diff -u -p -u -r1.20 sdhc_pci.c
--- sys/dev/pci/sdhc_pci.c  30 Apr 2016 11:32:23 -  1.20
+++ sys/dev/pci/sdhc_pci.c  11 Jun 2019 01:31:04 -
@@ -21,6 +21,16 @@
 #include 
 #include 

+#include "acpi.h"
+#if NACPI > 0
+#include 
+#include 
+#include 
+#include 
+#include 
+#undef DEVNAME
+#endif
+
 #include 
 #include 
 #include 
@@ -52,6 +62,16 @@ struct sdhc_pci_softc {
pcitag_t sc_tag;
pcireg_t sc_id;
void *sc_ih;
+#if NACPI > 0
+   struct acpi_softc *sc_acpi;
+   struct aml_node *sc_node;
+
+   struct aml_node *sc_gpio_int_node;
+   struct aml_node *sc_gpio_io_node;
+   uint16_t sc_gpio_int_pin;
+   uint16_t sc_gpio_int_flags;
+   uint16_t sc_gpio_io_pin;
+#endif
 };

 intsdhc_pci_match(struct device *, void *, void *);
@@ -62,6 +82,17 @@ void sdhc_pci_conf_write(pci_chipset_tag
 void   sdhc_takecontroller(struct pci_attach_args *);
 void   sdhc_ricohfix(struct sdhc_pci_softc *);

+#if NACPI > 0
+struct aml_node *acpi_pci_match(struct device *, struct pci_attach_args *);
+intsdhc_pci_card_detect_nonremovable(struct sdhc_softc *);
+intsdhc_pci_card_detect_gpio(struct sdhc_softc *);
+intsdhc_pci_card_detect_intr(void *);
+intsdhc_pci_acpi_parse_resources(int, union acpi_resource *, void *);
+void   sdhc_pci_acpi_get_resources(struct sdhc_pci_softc *);
+void   sdhc_pci_acpi_explore(struct sdhc_pci_softc *);
+void   sdhc_pci_acpi_power_on(struct sdhc_pci_softc *, struct aml_node *);
+#endif
+
 struct cfattach sdhc_pci_ca = {
sizeof(struct sdhc_pci_softc), sdhc_pci_match, sdhc_pci_attach,
NULL, sdhc_pci_activate
@@ -147,6 +178,14 @@ sdhc_pci_attach(struct device *parent, s
}
printf(": %s\n", intrstr);

+#if NACPI > 0
+   sc->sc_node = acpi_pci_match(self, pa);
+   if (sc->sc_node != NULL) {
+   sdhc_pci_acpi_get_resources(sc);
+   sdhc_pci_acpi_power_on(sc, sc->sc_node);
+   sdhc_pci_acpi_explore(sc);
+   }
+#endif
/* Enable use of DMA if supported by the interface. */
usedma = PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA;
sc->sc.sc_dmat = pa->pa_dmat;
@@ -257,3 +296,123 @@ sdhc_pci_conf_write(pci_chipset_tag_t pc
tmp |= (val << ((reg & 0x3) * 8));
pci_conf_write(pc, tag, reg & ~0x3, tmp);
 }
+#if NACPI > 0
+int
+sdhc_pci_card_detect_nonremovable(struct sdhc_softc *sc)
+{
+   return 1;
+}
+
+int
+sdhc_pci_card_detect_gpio(struct sdhc_softc *ssc)
+{
+   struct sdhc_pci_softc *sc = (struct sdhc_pci_softc *)ssc;
+   struct acpi_gpio *gpio = sc->sc_gpio_io_node->gpio;
+   uint16_t pin = sc->sc_gpio_io_pin;
+
+   /* Card detect GPIO signal is active-low. */
+   return !gpio->read_pin(gpio->cookie, pin);
+}
+
+int
+sdhc_pci_card_detect_intr(void *arg)
+{
+   struct sdhc_pci_softc *sc = arg;
+
+   sdhc_needs_discover(>sc);
+
+   return 1;
+}
+
+int
+sdhc_pci_acpi_parse_resources(int crsidx, union acpi_resource *crs,
void *arg)
+{
+   struct sdhc_pci_softc *sc = arg;
+   int type = AML_CRSTYPE(crs);
+   struct aml_node *node;
+   uint16_t pin;
+
+   switch (type) {
+   case LR_GPIO:
+   node = aml_searchname(sc->sc_node, (char
*)>pad[crs->lr_gpio.res_off]);
+   pin = *(uint16_t *)>pad[crs->lr_gpio.pin_off];
+   if (crs->lr_gpio.type == LR_GPIO_INT) {
+   sc->sc_gpio_int_node = node;
+   sc->sc_gpio_int_pin = pin;
+   sc->sc_gpio_int_flags = crs->lr_gpio.tflags;
+   } else if (crs->lr_gpio.type == LR_GPIO_IO) {
+   sc->sc_gpio_io_node = node;
+   sc->sc_gpio_io_pin = pin;
+   }
+   }
+
+   return 0;
+}
+
+void
+sdhc_pci_acpi_get_resources(struct sdhc_pci_softc *sc)
+{
+   struct aml_value res;
+
+   aml_evalname(sc->sc_acpi, sc->sc_node, "_CRS", 0, NULL, );
+   aml_parse_resource(, sdhc_pci_acpi_parse_resources, sc);
+
+   if (sc->sc_gpio_io_node && sc->sc_gpio_io_node->gpio)
+   sc->sc.sc_card_detect = sdhc_pci_card_detect_gpio;
+
+   if (sc->sc_gpio_int_node && sc->sc_gpio_int_node->gpio) {
+   struct acpi_gpio *gpio = sc->sc_gpio_int_node->gpio;
+   gpio->intr_establish(gpio->cookie, sc->sc_gpio_int_pin,
+   sc->sc_gpio_int_flags, sdhc_pci_card_detect_intr, sc);
+   }
+}
+
+void
+sdhc_pci_acpi_power_on(struct 

apollo lake gpio

2019-06-10 Thread James Hastings
New driver for Apollo Lake GPIO controller.

Based on bytgpio(4); minus the randomly ordered pads.

Specification from Intel Pentium and Celeron N- and J- Series Volume 3
Document Number: 334819-001


Index: share/man/man4/Makefile
===
RCS file: /cvs/src/share/man/man4/Makefile,v
retrieving revision 1.713
diff -u -p -u -r1.713 Makefile
--- share/man/man4/Makefile 7 Jun 2019 16:06:59 -   1.713
+++ share/man/man4/Makefile 11 Jun 2019 01:31:02 -
@@ -10,7 +10,7 @@ MAN=  aac.4 abcrtc.4 ac97.4 acphy.4 acrtc
admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \
ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \
akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \
-   ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \
+   ams.4 an.4 andl.4 aplgpio.4 aps.4 arc.4 arcofi.4 \
asbtm.4 asmc.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \
auacer.4 audio.4 aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 \
axe.4 axen.4 axppmic.4 azalia.4 \
Index: share/man/man4/acpi.4
===
RCS file: /cvs/src/share/man/man4/acpi.4,v
retrieving revision 1.57
diff -u -p -u -r1.57 acpi.4
--- share/man/man4/acpi.4   23 Apr 2019 20:23:36 -  1.57
+++ share/man/man4/acpi.4   11 Jun 2019 01:31:02 -
@@ -90,6 +90,8 @@ ACPI video
 ACPI video output
 .It Xr aibs 4
 ASUSTeK AI Booster ACPI ATK0110 temperature, voltage, and fan sensor
+.It Xr aplgpio 4
+Intel Apollo Lake GPIO controller
 .It Xr bytgpio 4
 Intel Bay Trail GPIO controller
 .It Xr ccp 4
Index: share/man/man4/aplgpio.4
===
RCS file: share/man/man4/aplgpio.4
diff -N share/man/man4/aplgpio.4
--- /dev/null   1 Jan 1970 00:00:00 -
+++ share/man/man4/aplgpio.411 Jun 2019 01:31:02 -
@@ -0,0 +1,49 @@
+.\"
+.\" Copyright (c) 2019 James Hastings
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt APLGPIO 4
+.Os
+.Sh NAME
+.Nm aplgpio
+.Nd Intel Apollo Lake GPIO controller
+.Sh SYNOPSIS
+.Cd "aplgpio* at acpi?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the GPIO controllers found on Intel's Apollo
+Lake SoC.
+It does not provide direct device driver entry points but makes its
+functions available to
+.Xr acpi 4 .
+.Sh SEE ALSO
+.Xr acpi 4 ,
+.Xr intro 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An James Hastings
+based on the
+.Xr bytgpio 4
+driver by
+.An Mark Kettenis Aq Mt kette...@openbsd.org .
Index: sys/arch/amd64/conf/GENERIC
===
RCS file: /cvs/src/sys/arch/amd64/conf/GENERIC,v
retrieving revision 1.473
diff -u -p -u -r1.473 GENERIC
--- sys/arch/amd64/conf/GENERIC 7 Jun 2019 16:06:59 -   1.473
+++ sys/arch/amd64/conf/GENERIC 11 Jun 2019 01:31:02 -
@@ -61,6 +61,7 @@ acpivideo*at acpi?
 acpivout*  at acpivideo?
 acpipwrres*at acpi?
 aibs*  at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 chvgpio*   at acpi?
 sdhc*  at acpi?
Index: sys/arch/amd64/conf/RAMDISK_CD
===
RCS file: /cvs/src/sys/arch/amd64/conf/RAMDISK_CD,v
retrieving revision 1.179
diff -u -p -u -r1.179 RAMDISK_CD
--- sys/arch/amd64/conf/RAMDISK_CD  4 May 2019 17:59:40 -   1.179
+++ sys/arch/amd64/conf/RAMDISK_CD  11 Jun 2019 01:31:02 -
@@ -42,6 +42,7 @@ acpiec*   at acpi?
 acpiprt*   at acpi?
 acpimadt0  at acpi?
 #acpitz*   at acpi?
+aplgpio*   at acpi?
 bytgpio*   at acpi?
 sdhc*  at acpi?
 acpihve*   at acpi?
Index: sys/dev/acpi/aplgpio.c
===
RCS file: sys/dev/acpi/aplgpio.c
diff -N sys/dev/acpi/aplgpio.c
--- /dev/null   1 Jan 1970 00:00:00 -
+++ sys/dev/acpi/aplgpio.c  11 Jun 2019 01:31:03 -
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2016 Mark Kettenis
+ * Copyright (c) 2019 James Hastings
+ *
+ * Permission to use, copy,

dwiic: add apollo lake support

2019-06-10 Thread James Hastings
Add support for Apollo Lake I2C at pci bus.
Include two PCIE devs while we are here.


Index: sys/dev/pci/dwiic_pci.c
===
RCS file: /cvs/src/sys/dev/pci/dwiic_pci.c,v
retrieving revision 1.5
diff -u -p -u -r1.5 dwiic_pci.c
--- sys/dev/pci/dwiic_pci.c 16 May 2019 01:14:08 -  1.5
+++ sys/dev/pci/dwiic_pci.c 11 Jun 2019 01:31:03 -
@@ -70,6 +70,14 @@ const struct pci_matchid dwiic_pci_ids[]
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_4 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_5 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_6 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_1 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_2 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_3 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_4 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_5 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7 },
+   { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8 },
 };

 int
Index: sys/dev/pci/pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1889
diff -u -p -u -r1.1889 pcidevs
--- sys/dev/pci/pcidevs 10 May 2019 15:28:45 -  1.1889
+++ sys/dev/pci/pcidevs 11 Jun 2019 01:31:03 -
@@ -4951,6 +4951,13 @@ product INTEL APOLLOLAKE_HDA 0x5a98  Apol
 product INTEL APOLLOLAKE_TXE   0x5a9a  Apollo Lake TXE
 product INTEL APOLLOLAKE_XHCI  0x5aa8  Apollo Lake xHCI
 product INTEL APOLLOLAKE_I2C_1 0x5aac  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_2 0x5aae  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_3 0x5ab0  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_4 0x5ab2  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_5 0x5ab4  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_6 0x5ab6  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_7 0x5ab8  Apollo Lake I2C
+product INTEL APOLLOLAKE_I2C_8 0x5aba  Apollo Lake I2C
 product INTEL APOLLOLAKE_UART_10x5abc  Apollo Lake HSUART
 product INTEL APOLLOLAKE_SPI_1 0x5ac2  Apollo Lake SPI
 product INTEL APOLLOLAKE_SPI_2 0x5ac4  Apollo Lake SPI
@@ -4959,9 +4966,11 @@ product INTEL APOLLOLAKE_SDMMC   0x5aca  Ap
 product INTEL APOLLOLAKE_EMMC  0x5acc  Apollo Lake eMMC
 product INTEL APOLLOLAKE_SDIO  0x5ad0  Apollo Lake SDIO
 product INTEL APOLLOLAKE_SMB   0x5ad4  Apollo Lake SMBus
-product INTEL APOLLOLAKE_PCIE_10x5ad8  Apollo Lake PCIE
-product INTEL APOLLOLAKE_PCIE_20x5ad9  Apollo Lake PCIE
-product INTEL APOLLOLAKE_PCIE_30x5ada  Apollo Lake PCIE
+product INTEL APOLLOLAKE_PCIE_10x5ad6  Apollo Lake PCIE
+product INTEL APOLLOLAKE_PCIE_20x5ad7  Apollo Lake PCIE
+product INTEL APOLLOLAKE_PCIE_30x5ad8  Apollo Lake PCIE
+product INTEL APOLLOLAKE_PCIE_40x5ad9  Apollo Lake PCIE
+product INTEL APOLLOLAKE_PCIE_50x5ada  Apollo Lake PCIE
 product INTEL APOLLOLAKE_AHCI  0x5ae3  Apollo Lake AHCI
 product INTEL APOLLOLAKE_LPC   0x5ae8  Apollo Lake LPC
 product INTEL APOLLOLAKE_HB0x5af0  Apollo Lake Host
Index: sys/dev/pci/pcidevs.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.1882
diff -u -p -u -r1.1882 pcidevs.h
--- sys/dev/pci/pcidevs.h   10 May 2019 15:29:17 -  1.1882
+++ sys/dev/pci/pcidevs.h   11 Jun 2019 01:31:04 -
@@ -4956,6 +4956,13 @@
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_TXE0x5a9a  /* 
Apollo Lake TXE */
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_XHCI   0x5aa8  /* 
Apollo Lake xHCI */
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_1  0x5aac  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_2  0x5aae  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_3  0x5ab0  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_4  0x5ab2  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_5  0x5ab4  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6  0x5ab6  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7  0x5ab8  /* 
Apollo Lake I2C */
+#definePCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8  0x5aba  /* 
Apollo Lake I2C */
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_UART_1 0x5abc  /* 
Apollo Lake
HSUART */
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_SPI_1  0x5ac2  /* 
Apollo Lake SPI */
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_SPI_2  0x5ac4  /* 
Apollo Lake SPI */
@@ -4964,9 +4971,11 @@
 #definePCI_PRODUCT_INTEL_APOLLOLAKE_EMMC   0x5acc  /* 
Apollo Lake eMMC */
 #define

Re: pci_sdhc: Intel eMMC controller fix

2019-04-09 Thread James Hastings
On 03/29/2019 05:22 AM, James Hastings wrote:
> Index: dev/pci/pcidevs
> ===
> RCS file: /cvs/src/sys/dev/pci/pcidevs,v
> retrieving revision 1.1881
> diff -u -p -r1.1881 pcidevs
> --- dev/pci/pcidevs   20 Mar 2019 10:51:25 -  1.1881
> +++ dev/pci/pcidevs   29 Mar 2019 07:57:20 -
> @@ -4467,6 +4467,7 @@ product INTEL WL_3165_1 0x3165  Dual Ban
>  product INTEL WL_3165_2  0x3166  Dual Band Wireless AC 3165
>  product INTEL GLK_UHD_6050x3184  UHD Graphics 605
>  product INTEL GLK_UHD_6000x3185  UHD Graphics 600
> +product INTEL GLK_EMMC   0x31cc  Gemini Lake eMMC
>  product INTEL 31244  0x3200  31244 SATA
>  product INTEL 82855PM_HB 0x3340  82855PM Host
>  product INTEL 82855PM_AGP0x3341  82855PM AGP
> Index: dev/pci/sdhc_pci.c
> ===
> RCS file: /cvs/src/sys/dev/pci/sdhc_pci.c,v
> retrieving revision 1.20
> diff -u -p -r1.20 sdhc_pci.c
> --- dev/pci/sdhc_pci.c30 Apr 2016 11:32:23 -  1.20
> +++ dev/pci/sdhc_pci.c29 Mar 2019 07:57:20 -
> @@ -127,6 +127,12 @@ sdhc_pci_attach(struct device *parent, s
>   PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ENE_SDCARD)
>   sc->sc.sc_flags |= SDHC_F_NOPWR0;
>
> + /* Some Intel controllers break if set to 0V bus power. */
> + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
> + (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_APOLLOLAKE_EMMC ||
> + PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GLK_EMMC))
> + sc->sc.sc_flags |= SDHC_F_NOPWR0;
> +
>   /* Some RICOH controllers need to be bumped into the right mode. */
>   if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
>   (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U822 ||
>
My apologies @tech, last dmesg was subtly mangled.

Once more with card in slot, patch and sdmmcdebug=1

I believe the SD controller depends on GPIO support; for which there is
no driver on this system. However eMMC is working well.

dmesg:
OpenBSD 6.5 (GENERIC.MP) #4: Tue Apr  9 19:56:22 EDT 2019
r...@sandisk.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 451104 (3920MB)
avail mem = 3976933376 (3792MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0x78758000 (23 entries)
bios0: vendor Insyde Corp. version "V1.07" date 04/13/2018
bios0: Acer Spin SP111-32N
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP MSDM UEFI SSDT DBG2 LPIT MCFG PRAM SSDT SSDT
SSDT SSDT DMAR BDAT TPM2 HPET NPKT SSDT SSDT FPDT UEFI DBGP WSMT SSDT
SSDT SSDT APIC WDAT BGRT NHLT
acpi0: wakeup devices PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4)
RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) RP06(S4) XHC_(S3)
XDCI(S4) HDAS(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-63
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4580.15 MHz, 06-5c-09
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 1MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 80MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2.4.2.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4585.18 MHz, 06-5c-09
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 1MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4586.01 MHz, 06-5c-09
cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,

Re: pci_sdhc: Intel eMMC controller fix

2019-03-29 Thread James Hastings
Index: dev/pci/pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1881
diff -u -p -r1.1881 pcidevs
--- dev/pci/pcidevs 20 Mar 2019 10:51:25 -  1.1881
+++ dev/pci/pcidevs 29 Mar 2019 07:57:20 -
@@ -4467,6 +4467,7 @@ product INTEL WL_3165_1   0x3165  Dual Ban
 product INTEL WL_3165_20x3166  Dual Band Wireless AC 3165
 product INTEL GLK_UHD_605  0x3184  UHD Graphics 605
 product INTEL GLK_UHD_600  0x3185  UHD Graphics 600
+product INTEL GLK_EMMC 0x31cc  Gemini Lake eMMC
 product INTEL 312440x3200  31244 SATA
 product INTEL 82855PM_HB   0x3340  82855PM Host
 product INTEL 82855PM_AGP  0x3341  82855PM AGP
Index: dev/pci/sdhc_pci.c
===
RCS file: /cvs/src/sys/dev/pci/sdhc_pci.c,v
retrieving revision 1.20
diff -u -p -r1.20 sdhc_pci.c
--- dev/pci/sdhc_pci.c  30 Apr 2016 11:32:23 -  1.20
+++ dev/pci/sdhc_pci.c  29 Mar 2019 07:57:20 -
@@ -127,6 +127,12 @@ sdhc_pci_attach(struct device *parent, s
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ENE_SDCARD)
sc->sc.sc_flags |= SDHC_F_NOPWR0;

+   /* Some Intel controllers break if set to 0V bus power. */
+   if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
+   (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_APOLLOLAKE_EMMC ||
+   PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GLK_EMMC))
+   sc->sc.sc_flags |= SDHC_F_NOPWR0;
+
/* Some RICOH controllers need to be bumped into the right mode. */
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U822 ||



Re: pci_sdhc: Intel eMMC controller fix

2019-03-29 Thread James Hastings
On 3/26/19, Mark Kettenis  wrote:
> Did you test this with SD-cards in slots as well as with eMMC?
>

Tried again with Samsung 16GB card in slot plus
NOPWR0 patch and sdmmcdebug=1

eMMC works, SD slot does not work.

Also tested with combinations of existing
sdhc flags NODDR50, NOPWR0 or none.

sdmmc0: can't send memory OCR
sdmmc0: can't enable card

I do not know how to fix SD/MMC slot right now.
Will send patch for eMMC device ids instead of
matching only intel vendor id.

In the meantime I hope this debug level helps.

dmesg:
OpenBSD 6.5-beta (GENERIC.MP) #0: Thu Mar 28 22:05:35 EDT 2019
r...@sandisk.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 451104 (3920MB)
avail mem = 3976196096 (3791MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0x78758000 (23 entries)
bios0: vendor Insyde Corp. version "V1.07" date 04/13/2018
bios0: Acer Spin SP111-32N
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP MSDM UEFI SSDT DBG2 LPIT MCFG PRAM SSDT SSDT
SSDT SSDT DMAR BDAT TPM2 HPET NPKT SSDT SSDT FPDT UEFI DBGP WSMT SSDT
SSDT SSDT APIC WDAT BGRT NHLT
acpi0: wakeup devices PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4)
RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) RP06(S4)
XHC_(S3) XDCI(S4) HDAS(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-63
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4582.18 MHz, 06-5c-09
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 1MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 80MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2.4.2.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4583.71 MHz, 06-5c-09
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 1MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4583.71 MHz, 06-5c-09
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 1MB 64b/line 16-way L2 cache
cpu2: smt 0, core 2, package 0
cpu3 at mainbus0: apid 6 (application processor)
cpu3: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4583.71 MHz, 06-5c-09
cpu3: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu3: 1MB 64b/line 16-way L2 cache
cpu3: smt 0, core 3, package 0
ioapic0 at mainbus0: apid 1 pa 0xfec0, version 20, 120 pins
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (RP01)
acpiprt2 at acpi0: bus 1 (RP02)
acpiprt3 at acpi0: bus -1 (RP03)
acpiprt4 at acpi0: bus -1 (RP04)
acpiprt5 at acpi0: bus -1 (RP05)
acpiprt6 at acpi0: bus -1 (RP06)
acpiec0 at acpi0
acpi0: GPE 0x2c already enabled
acpicpu0 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpicpu1 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpicpu2 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpicpu3 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpipwrres0 at acpi0: FN00
acpitz0 at acpi0: critical temperature is 100 degC
acpipci0 at acpi0 PCI0: 0x 0x0011 0x0001
acpiac0 at acpi0: AC unit online
acpibat0 at acpi0: BAT0 model "AP16L5J" serial type LION oem 

pci_sdhc: Intel eMMC controller fix

2019-03-20 Thread James Hastings
On Intel Apollo Lake and Gemini Lake systems with pci eMMC sdhc
controller I encounter:

sdhc1 at pci0 dev 28 function 0 "Intel Apollo Lake eMMC" rev 0x0b: apic 1 int 39
sdhc1: SDHC 3.0, 200 MHz base clock
sdmmc1 at sdhc1: 8-bit, sd high-speed, mmc high-speed, dma
...
sdmmc1: can't enable card

The following patch restores normal sdmmc access.

scsibus2 at sdmmc1: 2 targets, initiator 0
sd0 at scsibus2 targ 1 lun 0:  SCSI2 0/direct removable
sd0: 59640MB, 512 bytes/sector, 122142720 sectors

I have tested on various HP and Acer laptops with success.
Bay Trail and Braswell systems are not affected, their eMMC controller
attaches to acpi and works properly.

Index: dev/pci/sdhc_pci.c
===
RCS file: /cvs/src/sys/dev/pci/sdhc_pci.c,v
retrieving revision 1.20
diff -u -p -r1.20 sdhc_pci.c
--- dev/pci/sdhc_pci.c  30 Apr 2016 11:32:23 -  1.20
+++ dev/pci/sdhc_pci.c  20 Mar 2019 05:47:13 -
@@ -127,6 +127,10 @@ sdhc_pci_attach(struct device *parent, s
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ENE_SDCARD)
sc->sc.sc_flags |= SDHC_F_NOPWR0;

+   /* Intel eMMC controllers break if set to 0V bus power. */
+   if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL)
+   sc->sc.sc_flags |= SDHC_F_NOPWR0;
+
/* Some RICOH controllers need to be bumped into the right mode. */
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U822 ||




OpenBSD 6.5-beta (GENERIC.MP) #799: Sat Mar 16 22:33:35 MDT 2019
dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 451104 (3920MB)
avail mem = 3976237056 (3792MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0x78758000 (23 entries)
bios0: vendor Insyde Corp. version "V1.07" date 04/13/2018
bios0: Acer Spin SP111-32N
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP MSDM UEFI SSDT DBG2 LPIT MCFG PRAM SSDT SSDT
SSDT SSDT DMAR BDAT TPM2 HPET NPKT SSDT SSDT FPDT UEFI DBGP WSMT SSDT
SSDT SSDT APIC WDAT BGRT NHLT
acpi0: wakeup devices PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4)
RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) RP06(S4)
XHC_(S3) XDCI(S4) HDAS(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-63
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4590.51 MHz, 06-5c-09
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 1MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 80MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2.4.2.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4591.67 MHz, 06-5c-09
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 1MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4591.67 MHz, 06-5c-09
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 1MB 64b/line 16-way L2 cache
cpu2: smt 0, core 2, package 0
cpu3 at mainbus0: apid 6 (application processor)
cpu3: Intel(R) Pentium(R) CPU N4200 @ 1.10GHz, 4591.67 MHz, 06-5c-09
cpu3: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu3: 1MB 64b/line 16-way L2 

[PATCH] Gemini Lake SoC pcidevs and eMMC

2019-01-02 Thread James Hastings
Hello tech@

I would like to add PCI devices for latest Intel SoC (Gemini Lake).

Included a patch for sdhc(4) too that depends on this to enable eMMC.
The Intel eMMC controller does not like bus power going to 0V. There
may be other systems (Apollo Lake) that need this quirk too.

With both patches I am booting from internal eMMC on HP Stream 14.

Comments? ok?


OpenBSD 6.4-current (GENERIC.MP) #22: Wed Jan  2 13:36:31 EST 2019
ti...@sandisk.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 4102090752 (3912MB)
avail mem = 3968520192 (3784MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0x75e02000 (36 entries)
bios0: vendor Insyde version "F.02" date 05/23/2018
bios0: HP HP Stream Laptop 14-cb1XX
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP UEFI IHIS UEFI SSDT TPM2 SSDT SSDT MSDM BDAT
DBG2 DBGP HPET LPIT APIC MCFG NPKT PRAM WSMT SSDT SSDT SSDT SSDT SSDT
SSDT SSDT FPDT WDAT BGRT
acpi0: wakeup devices PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4)
RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) RP06(S4) XHC_(S4)
HDAS(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz, 1097.30 MHz, 06-7a-01
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SGX,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,UMIP,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu0: 4MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 19MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2.4.2.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz, 1096.98 MHz, 06-7a-01
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SGX,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,UMIP,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu1: 4MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
ioapic0 at mainbus0: apid 1 pa 0xfec0, version 20, 120 pins
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-63
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (RP01)
acpiprt2 at acpi0: bus -1 (RP02)
acpiprt3 at acpi0: bus -1 (RP03)
acpiprt4 at acpi0: bus -1 (RP04)
acpiprt5 at acpi0: bus 1 (RP05)
acpiprt6 at acpi0: bus -1 (RP06)
acpiec0 at acpi0
### AML PARSE ERROR (0x4cd5): Undefined name: SMA4
error evaluating: \\_SB_.PCI0.LPCB.EC0_._REG
acpiec _REG failed, broken BIOS
acpipwrres0 at acpi0: DRST
acpipwrres1 at acpi0: DRST
acpipwrres2 at acpi0: DRST
acpipwrres3 at acpi0: DRST
acpipwrres4 at acpi0: DRST
acpipwrres5 at acpi0: DRST
acpicpu0 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpicpu1 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpitz0 at acpi0: critical temperature is 210 degC
acpiac0 at acpi0: AC unit offline
acpibtn0 at acpi0: LID0
acpibtn1 at acpi0: PWRB
acpibat0 at acpi0: BAT0 model "Primary" serial   type LION oem "HP"
acpipci0 at acpi0 PCI0: 0x 0x0011 0x0001
"HPQ6001" at acpi0 not configured
"HPIC0003" at acpi0 not configured
"*ETD0742" at acpi0 not configured
acpicmos0 at acpi0
"INT3453" at acpi0 not configured
"INT33A1" at acpi0 not configured
"MSFT0101" at acpi0 not configured
"PNP0C14" at acpi0 not configured
"INT3400" at acpi0 not configured
"INT3403" at acpi0 not configured
acpivideo0 at acpi0: GFX0
acpivout0 at acpivideo0: DD1F
cpu0: Enhanced SpeedStep 1097 MHz: speeds: 1101, 1100, 1000, 900, 800 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel Gemini Lake Host" rev 0x03
"Intel Gemini Lake DPTF" rev 0x03 at pci0 dev 0 function 1 not configured
"Intel Gemini Lake GNA" rev 0x03 at pci0 dev 0 function 3 not configured
"Intel UHD Graphics 600" rev 0x03 at pci0 dev 2 function 0 not configured
azalia0 at pci0 dev 14 function 0 "Intel Gemini Lake HD Audio" rev 0x03: msi
azalia0: codecs: Realtek ALC282, Intel/0x280d, using Realtek ALC282
audio0 at azalia0
"Intel Gemini Lake MEI" rev 0x03 at pci0 dev 15 function 0 not configured
ppb0 at pci0 dev 19 function 0 "Intel Gemini Lake PCIE" rev 0xf3: msi
pci1 at ppb0 bus 1
"Realtek 8822BE" rev 0x00 at pci1 dev 0 function 0 not configured
xhci0 at pci0 dev 21 function 0 "Intel Gemini Lake xHCI" rev 0x03: msi,
xHCI 1.0

Re: [PATCH] Gemini Lake SoC pcidevs

2018-12-22 Thread James Hastings
Here is a dmesg and acpidump from another HP Stream laptop.
Running with pcidevs patch and SDMMC_DEBUG turned on.


OpenBSD 6.4-current (SDMMC_DEBUG) #280: Wed Dec 19 23:44:03 EST 2018
xxx@xxx:/usr/src/sys/arch/amd64/compile/SDMMC_DEBUG
real mem = 4102090752 (3912MB)
avail mem = 3968425984 (3784MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3 @ 0x75e05000 (36 entries)
bios0: vendor Insyde version F.01 date 05/03/2018
bios0: HP HP Stream Laptop 14-cb1XX
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP UEFI IHIS UEFI SSDT TPM2 SSDT SSDT MSDM BDAT
DBG2 DBGP HPET LPIT APIC MCFG NPKT PRAM WSMT SSDT SSDT SSDT SSDT SSDT
SSDT SSDT FPDT WDAT BGRT
acpi0: wakeup devices PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) PXSX(S4)
RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) RP06(S4) XHC_(S4)
HDAS(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 1920 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz, 1097.43 MHz, 06-7a-01
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SGX,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,UMIP,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu0: 4MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 19MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2.4.2.1.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz, 1096.97 MHz, 06-7a-01
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,SGX,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,UMIP,IBRS,IBPB,STIBP,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu1: 4MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
ioapic0 at mainbus0: apid 1 pa 0xfec0, version 20, 120 pins
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-63
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (RP01)
acpiprt2 at acpi0: bus -1 (RP02)
acpiprt3 at acpi0: bus -1 (RP03)
acpiprt4 at acpi0: bus -1 (RP04)
acpiprt5 at acpi0: bus 1 (RP05)
acpiprt6 at acpi0: bus -1 (RP06)
acpiec0 at acpi0
### AML PARSE ERROR (0x4cd5): Undefined name: SMA4
error evaluating: \\_SB_.PCI0.LPCB.EC0_._REG
acpiec _REG failed, broken BIOS
acpipwrres0 at acpi0: DRST
acpipwrres1 at acpi0: DRST
acpipwrres2 at acpi0: DRST
acpipwrres3 at acpi0: DRST
acpipwrres4 at acpi0: DRST
acpipwrres5 at acpi0: DRST
acpicpu0 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpicpu1 at acpi0: C3(10@150 mwait.1@0x60), C2(10@50 mwait.1@0x21),
C1(1000@1 mwait.1@0x1), PSS
acpitz0 at acpi0: critical temperature is 210 degC
acpiac0 at acpi0: AC unit online
acpibtn0 at acpi0: LID0
acpibtn1 at acpi0: PWRB
acpibat0 at acpi0: BAT0 model Primary serial   type LION oem HP
acpipci0 at acpi0 PCI0: 0x 0x0011 0x0001
HPQ6001 at acpi0 not configured
HPIC0003 at acpi0 not configured
*ETD0742 at acpi0 not configured
acpicmos0 at acpi0
INT3453 at acpi0 not configured
INT33A1 at acpi0 not configured
MSFT0101 at acpi0 not configured
PNP0C14 at acpi0 not configured
INT3400 at acpi0 not configured
INT3403 at acpi0 not configured
acpivideo0 at acpi0: GFX0
acpivout0 at acpivideo0: DD1F
cpu0: Enhanced SpeedStep 1097 MHz: speeds: 1101, 1100, 1000, 900, 800 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel Gemini Lake Host" rev 0x03
"Intel Gemini Lake DPTF" rev 0x03 at pci0 dev 0 function 1 not configured
"Intel Gemini Lake GNA" rev 0x03 at pci0 dev 0 function 3 not configured
"Intel UHD Graphics 600" rev 0x03 at pci0 dev 2 function 0 not configured
azalia0 at pci0 dev 14 function 0 "Intel Gemini Lake HD Audio" rev 0x03: msi
azalia0: codecs: Realtek ALC282, Intel/0x280d, using Realtek ALC282
audio0 at azalia0
"Intel Gemini Lake MEI" rev 0x03 at pci0 dev 15 function 0 not configured
ppb0 at pci0 dev 19 function 0 "Intel Gemini Lake PCIE" rev 0xf3: msi
pci1 at ppb0 bus 1
"Realtek 8822BE" rev 0x00 at pci1 dev 0 function 0 not configured
xhci0 at pci0 dev 21 function 0 "Intel Gemini Lake xHCI" rev 0x03: msi,
xHCI 1
usb0 at xhci0: USB revision 3
uhub0 at usb0 configuration 1 interface 0 "Intel xHCI root hub" rev
3.00/1.00 addr 1
sdhc0 at pci0 dev 28 function 0 "Intel Gemini Lake eMMC" rev 0x03: apic
1 int 39
sdhc0: SDHC 3.0, 200 MHz base clock
sdmmc0 at sdhc0: 8-bit, sd high-speed, mmc high-speed, dma

Re: [PATCH] Gemini Lake SoC pcidevs

2018-12-14 Thread James Hastings
On 12/13/18, Heppler, J. Scott  wrote:
> I have an HP Stream 14 with an n4000 Gemini Lake mobile processor.
> The amd64_current does not find the eMMC storage
> Would it be of value to the project to apply the patch, generate an
> install image using release(8), test and submit the dmesg?

dmesg is welcome.
I think a kernel with SDMMC_DEBUG enabled would be more helpful
to find out what is failing with the eMMC chip.



[PATCH] add Gemini Lake SoC pcidevs

2018-12-11 Thread James Hastings
Index: dev/pci/pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1870
diff -u -p -r1.1870 pcidevs
--- dev/pci/pcidevs 30 Nov 2018 19:18:31 -  1.1870
+++ dev/pci/pcidevs 12 Dec 2018 04:47:11 -
@@ -4384,6 +4384,36 @@ product INTEL RCU32  0x3092  RCU32 I2O RA
 product INTEL 3124 0x3124  3124 SATA
 product INTEL WL_3165_10x3165  Dual Band Wireless AC 3165
 product INTEL WL_3165_20x3166  Dual Band Wireless AC 3165
+product INTEL GEMINILAKE_IGD_1 0x3184  UHD Graphics 605
+product INTEL GEMINILAKE_IGD_2 0x3185  UHD Graphics 600
+product INTEL GEMINILAKE_DPTF  0x318c  Gemini Lake DPTF
+product INTEL GEMINILAKE_GNA   0x3190  Gemini Lake GNA
+product INTEL GEMINILAKE_PMC   0x3194  Gemini Lake PMC
+product INTEL GEMINILAKE_HDA   0x3198  Gemini Lake HD Audio
+product INTEL GEMINILAKE_MEI   0x319a  Gemini Lake MEI
+product INTEL GEMINILAKE_XHCI  0x31a8  Gemini Lake xHCI
+product INTEL GEMINILAKE_I2C_1 0x31ac  Gemini Lake I2C
+product INTEL GEMINILAKE_UART_10x31bc  Gemini Lake HSUART
+product INTEL GEMINILAKE_UART_20x31be  Gemini Lake HSUART
+product INTEL GEMINILAKE_UART_30x31c0  Gemini Lake HSUART
+product INTEL GEMINILAKE_SPI_1 0x31c2  Gemini Lake SPI
+product INTEL GEMINILAKE_SPI_2 0x31c4  Gemini Lake SPI
+product INTEL GEMINILAKE_SPI_3 0x31c6  Gemini Lake SPI
+product INTEL GEMINILAKE_SD0x31ca  Gemini Lake SD/MMC
+product INTEL GEMINILAKE_EMMC  0x31cc  Gemini Lake eMMC
+product INTEL GEMINILAKE_SDIO  0x31d0  Gemini Lake SDIO
+product INTEL GEMINILAKE_SMB   0x31d4  Gemini Lake SMBus
+product INTEL GEMINILAKE_PCIE_10x31d6  Gemini Lake PCIE
+product INTEL GEMINILAKE_PCIE_20x31d7  Gemini Lake PCIE
+product INTEL GEMINILAKE_PCIE_30x31d8  Gemini Lake PCIE
+product INTEL GEMINILAKE_PCIE_40x31d9  Gemini Lake PCIE
+product INTEL GEMINILAKE_PCIE_50x31da  Gemini Lake PCIE
+product INTEL GEMINILAKE_PCIE_60x31db  Gemini Lake PCIE
+product INTEL GEMINIlAKE_WL0x31dc  Gemini Lake CNVi
+product INTEL GEMINILAKE_AHCI  0x31e3  Gemini Lake AHCI
+product INTEL GEMINILAKE_LPC   0x31e8  Gemini Lake LPC
+product INTEL GEMINILAKE_UART_40x31ee  Gemini Lake HSUART
+product INTEL GEMINILAKE_HOST  0x31f0  Gemini Lake Host
 product INTEL 312440x3200  31244 SATA
 product INTEL 82855PM_HB   0x3340  82855PM Host
 product INTEL 82855PM_AGP  0x3341  82855PM AGP



ral(4): add RT3290 support

2018-09-17 Thread James Hastings



Ported from original vendor driver.
RT3290 is similar to RT5390 but integrates WLAN + Bluetooth on single chip.
Bluetooth not supported.

New 4kb firmware at /etc/firmware/ral-rt3290 for this chip only.
New routines to read efuse rom and control wlan core.
Tested on RT3090 and RT5390.


Index: share/man/man4/ral.4
===
RCS file: /cvs/src/share/man/man4/ral.4,v
retrieving revision 1.112
diff -u -p -r1.112 ral.4
--- share/man/man4/ral.415 Jul 2018 10:44:49 -  1.112
+++ share/man/man4/ral.418 Sep 2018 00:43:03 -
@@ -65,7 +65,10 @@ The RT3090 chipset is the first generati
 from Ralink.
 .Pp
 The RT3900E chipset is a single-chip 802.11n adapter from Ralink.
-The MAC/Baseband Processor can be an RT5390 or RT5392.
+The MAC/Baseband Processor can be an RT3290, RT5390 or RT5392.
+The RT3290 is a combo 802.11n and Bluetooth chip.
+It operates in the 2 Ghz spectrum and supports one transmit path and one
+receiver path (1T1R).
 The RT5390 chip operates in the 2GHz spectrum and supports one 
transmit path

 and one receiver path (1T1R).
 The RT5392 chip operates in the 2GHz spectrum and supports up to two 
transmit

@@ -139,6 +142,7 @@ files to be loaded when an interface is
 .It /etc/firmware/ral-rt2561s
 .It /etc/firmware/ral-rt2661
 .It /etc/firmware/ral-rt2860
+.It /etc/firmware/ral-rt3290
 .El
 .Pp
 The RT2500 chipset does not require a firmware file to operate.
Index: sys/dev/ic/rt2860.c
===
RCS file: /cvs/src/sys/dev/ic/rt2860.c,v
retrieving revision 1.95
diff -u -p -r1.95 rt2860.c
--- sys/dev/ic/rt2860.c 26 Oct 2017 15:00:28 -  1.95
+++ sys/dev/ic/rt2860.c 18 Sep 2018 00:43:06 -
@@ -17,7 +17,8 @@
  */

 /*-
- * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset 
driver

+ * Ralink Technology RT2860/RT3090/RT3290/RT3390/RT3562/RT5390/
+ * RT5392 chipset driver
  * http://www.ralinktech.com/
  */

@@ -97,6 +98,7 @@ void  rt2860_ampdu_rx_stop(struct ieee80
 intrt2860_newstate(struct ieee80211com *, enum ieee80211_state,
int);
 uint16_t   rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
+uint16_t   rt3290_efuse_read_2(struct rt2860_softc *, uint16_t);
 uint16_t   rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
 void   rt2860_intr_coherent(struct rt2860_softc *);
 void   rt2860_drain_stats_fifo(struct rt2860_softc *);
@@ -147,6 +149,8 @@ const char *rt2860_get_rf(uint16_t);
 intrt2860_read_eeprom(struct rt2860_softc *);
 intrt2860_bbp_init(struct rt2860_softc *);
 void   rt5390_bbp_init(struct rt2860_softc *);
+void   rt3290_mac_init(struct rt2860_softc *);
+intrt3290_wlan_enable(struct rt2860_softc *);
 intrt2860_txrx_enable(struct rt2860_softc *);
 intrt2860_init(struct ifnet *);
 void   rt2860_stop(struct ifnet *, int);
@@ -172,6 +176,8 @@ static const struct {
uint8_t val;
 } rt2860_def_bbp[] = {
RT2860_DEF_BBP
+},rt3290_def_bbp[] = {
+   RT3290_DEF_BBP
 },rt5390_def_bbp[] = {
RT5390_DEF_BBP
 };
@@ -194,6 +200,8 @@ static const struct {
uint8_t val;
 }  rt3090_def_rf[] = {
RT3070_DEF_RF
+}, rt3290_def_rf[] = {
+   RT3290_DEF_RF
 }, rt3572_def_rf[] = {
RT3572_DEF_RF
 }, rt5390_def_rf[] = {
@@ -208,14 +216,19 @@ rt2860_attach(void *xsc, int id)
struct rt2860_softc *sc = xsc;
struct ieee80211com *ic = >sc_ic;
int qid, ntries, error;
-   uint32_t tmp;
+   uint32_t tmp, reg;

sc->amrr.amrr_min_success_threshold =  1;
sc->amrr.amrr_max_success_threshold = 15;

+   if (id == PCI_PRODUCT_RALINK_RT3290)
+   reg = RT2860_PCI_CFG;
+   else
+   reg = RT2860_ASIC_VER_ID;
+
/* wait for NIC to initialize */
for (ntries = 0; ntries < 100; ntries++) {
-   tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
+   tmp = RAL_READ(sc, reg);
if (tmp != 0 && tmp != 0x)
break;
DELAY(10);
@@ -286,7 +299,11 @@ rt2860_attachhook(struct device *self)
struct ifnet *ifp = >ic_if;
int i, error;

-   error = loadfirmware("ral-rt2860", >ucode, >ucsize);
+   if (sc->mac_ver == 0x3290) {
+   error = loadfirmware("ral-rt3290", >ucode, >ucsize);
+   } else {
+   error = loadfirmware("ral-rt2860", >ucode, >ucsize);
+   }
if (error != 0) {
printf("%s: error %d, could not read firmware file %s\n",
sc->sc_dev.dv_xname, error, "ral-rt2860");
@@ -1026,6 +1043,45 @@ rt3090_efuse_read_2(struct rt2860_softc
return (addr & 2) ? tmp >> 16 : tmp & 0x;
 }

+/* Read 16 bits from eFUSE ROM (RT3290 only) */
+uint16_t
+rt3290_efuse_read_2(struct rt2860_softc *sc, uint16_t 

Re: Help with the NET_LOCK()

2017-01-31 Thread James Hastings
boot to console:
/etc/hostname.re0:
inet n.n.n.n 0xff00

/etc/hostname.ral0:
nwid xyz
wpakey ""
mode 11g
dhcp

dmesg:
OpenBSD 6.0-current (GENERIC.MP) #4: Tue Jan 31 19:42:25 EST 2017
r...@cq58-b.test:/usr/src/sys/arch/amd64/compile/GENERIC.MP
RTC BIOS diagnostic error 80
real mem = 1690714112 (1612MB)
avail mem = 1634873344 (1559MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.7 @ 0x66abc000 (45 entries)
bios0: Hewlett-Packard Compaq CQ58 Notebook PC
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP UEFI HPET APIC MCFG ASF! BOOT SPCR WDRT WDAT
FPDT MSDM SSDT SSDT VFCT BGRT
acpi0: wakeup devices PB6_(S4) SPB0(S4) XPDV(S4) SPB1(S4) SPB3(S4)
GEC_(S4) OHC1(S3) OHC2(S3) OHC3(S3) OHC4(S3) EHC1(S3) EHC2(S3)
EHC3(S3) P2P_(S5)
acpitimer0 at acpi0: 3579545 Hz, 32 bits
acpihpet0 at acpi0: 14318180 Hz
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: AMD C-60 APU with Radeon(tm) HD Graphics, 998.70 MHz
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,SSSE3,CX16,POPCNT,NXE,MMXX,FFXSR,PAGE1GB,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,IBS,SKINIT,ITSC
cpu0: 32KB 64b/line 2-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
64b/line 16-way L2 cache
cpu0: 8 4MB entries fully associative
cpu0: DTLB 40 4KB entries fully associative, 8 4MB entries fully associative
cpu0: TSC frequency 998698210 Hz
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 199MHz
cpu0: mwait min=64, max=64, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: AMD C-60 APU with Radeon(tm) HD Graphics, 997.88 MHz
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,MWAIT,SSSE3,CX16,POPCNT,NXE,MMXX,FFXSR,PAGE1GB,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,IBS,SKINIT,ITSC
cpu1: 32KB 64b/line 2-way I-cache, 32KB 64b/line 8-way D-cache, 512KB
64b/line 16-way L2 cache
cpu1: 8 4MB entries fully associative
cpu1: DTLB 40 4KB entries fully associative, 8 4MB entries fully associative
cpu1: smt 0, core 1, package 0
ioapic0 at mainbus0: apid 4 pa 0xfec0, version 21, 24 pins
acpimcfg0 at acpi0 addr 0xf800, bus 0-63
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (PB4_)
acpiprt2 at acpi0: bus -1 (PB5_)
acpiprt3 at acpi0: bus -1 (PB6_)
acpiprt4 at acpi0: bus -1 (PB7_)
acpiprt5 at acpi0: bus 2 (SPB0)
acpiprt6 at acpi0: bus 6 (SPB1)
acpiprt7 at acpi0: bus 7 (SPB2)
acpiprt8 at acpi0: bus -1 (SPB3)
acpiprt9 at acpi0: bus 1 (P2P_)
acpiec0 at acpi0
acpicpu0 at acpi0: C2(0@100 io@0xf800), C1(@1 halt!), PSS
acpicpu1 at acpi0: C2(0@100 io@0xf800), C1(@1 halt!), PSS
acpipwrres0 at acpi0: FN00, resource for FAN0
acpitz0 at acpi0: critical temperature is 125 degC
acpibtn0 at acpi0: PWRB
"HPQ8001" at acpi0 not configured
"SYN1E49" at acpi0 not configured
acpiac0 at acpi0: AC unit online
acpibtn1 at acpi0: LID_
"PNP0C14" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
acpivideo0 at acpi0: VGA_
acpivideo1 at acpi0: VGA_
cpu0: 998 MHz: speeds: 1000 800 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "AMD AMD64 14h Host" rev 0x00
radeondrm0 at pci0 dev 1 function 0 "ATI Radeon HD 6290" rev 0x00
drm0 at radeondrm0
radeondrm0: msi
ahci0 at pci0 dev 17 function 0 "ATI SBx00 SATA" rev 0x00: apic 4 int
19, AHCI 1.2
ahci0: port 0: 6.0Gb/s
ahci0: port 2: 1.5Gb/s
scsibus1 at ahci0: 32 targets
sd0 at scsibus1 targ 0 lun 0: <> SCSI3 0/direct fixed
cd0 at scsibus1 targ 2 lun 0: <> ATAPI 5/cdrom removable
ohci0 at pci0 dev 18 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
18, version 1.0, legacy support
ehci0 at pci0 dev 18 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 17
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "ATI EHCI root hub" rev
2.00/1.00 addr 1
ohci1 at pci0 dev 19 function 0 "ATI SB700 USB" rev 0x00: apic 4 int
18, version 1.0, legacy support
ehci1 at pci0 dev 19 function 2 "ATI SB700 USB2" rev 0x00: apic 4 int 17
usb1 at ehci1: USB revision 2.0
uhub1 at usb1 configuration 1 interface 0 "ATI EHCI root hub" rev
2.00/1.00 addr 1
piixpm0 at pci0 dev 20 function 0 "ATI SBx00 SMBus" rev 0x42: polling
iic0 at piixpm0
spdmem0 at iic0 addr 0x51: 2GB DDR3 SDRAM PC3-12800 SO-DIMM
azalia0 at pci0 dev 20 function 2 "ATI SBx00 HD Audio" rev 0x40: apic 4 int 16
azalia0: codecs: IDT 92HD81B1X
audio0 at azalia0
pcib0 at pci0 dev 20 function 3 "ATI SB700 ISA" rev 0x40
ppb0 at pci0 dev 20 function 4 "ATI SB600 PCI" rev 0x40
pci1 at ppb0 bus 1
ppb1 at pci0 dev 21 function 0 "ATI SB800 PCIE" rev 0x00
pci2 at ppb1 bus 2
re0 at pci2 dev 0 function 0 "Realtek 8101E" rev 0x05: RTL8105E
(0x4080), msi, address
rlphy0 at re0 phy 7: RTL8201E 10/100 PHY, rev. 2
ppb2 at pci0 dev 21 function 1 "ATI SB800 PCIE" rev 0x00
pci3 at ppb2 bus 6
ral0 at pci3 dev 0 function 0 "Ralink 

Re: usbdevs: logitech: cleanup

2017-01-29 Thread James Hastings
New scaled-back diff. cleanup whitespace, s/QUICKCAM/QKCAM/, no new ids.

Index: dev/usb/uaudio.c
===
RCS file: /cvs/src/sys/dev/usb/uaudio.c,v
retrieving revision 1.122
diff -u -p -r1.122 uaudio.c
--- dev/usb/uaudio.c3 Jan 2017 06:45:58 -   1.122
+++ dev/usb/uaudio.c29 Jan 2017 22:13:04 -
@@ -214,13 +214,13 @@ struct uaudio_devs {
UAUDIO_FLAG_DEPENDENT },
{ { USB_VENDOR_DALLAS, USB_PRODUCT_DALLAS_J6502 },
UAUDIO_FLAG_NO_XU | UAUDIO_FLAG_BAD_ADC },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMNBDLX },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMNBDLX },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMPRONB },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMPRONB },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMPRO4K },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMPRO4K },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMZOOM },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMZOOM },
UAUDIO_FLAG_BAD_AUDIO },
{ { USB_VENDOR_TELEX, USB_PRODUCT_TELEX_MIC1 },
UAUDIO_FLAG_NO_FRAC }
Index: dev/usb/usbdevs
===
RCS file: /cvs/src/sys/dev/usb/usbdevs,v
retrieving revision 1.673
diff -u -p -r1.673 usbdevs
--- dev/usb/usbdevs 15 Dec 2016 15:42:05 -  1.673
+++ dev/usb/usbdevs 29 Jan 2017 22:13:07 -
@@ -2553,37 +2553,37 @@ product LOGITEC LANW300NU2S 0x0169  LAN-W
 product LOGITECH M2452 0x0203  M2452 keyboard
 product LOGITECH M4848 0x0301  M4848 mouse
 product LOGITECH PAGESCAN  0x040f  PageScan
-product LOGITECH QUICKCAMWEB   0x0801  QuickCam Web
+product LOGITECH QKCAMWEB  0x0801  QuickCam Web
 product LOGITECH WEBCAMC2000x0802  Webcam C200
 product LOGITECH WEBCAMC5000x0807  Webcam C500
 product LOGITECH QUICKCAMPRO   0x0810  QuickCam Pro
 product LOGITECH WEBCAMC3100x081b  Webcam C310
 product LOGITECH HDPROC910 0x0821  HD Pro Webcam C910
-product LOGITECH QUICKCAMEXP   0x0840  QuickCam Express
-product LOGITECH QUICKCAM  0x0850  QuickCam
-product LOGITECH QUICKCAMNBDLX 0x08a9  QuickCam Notebook Deluxe
-product LOGITECH QUICKCAMPRO3K 0x08b0  QuickCam Pro 3000
-product LOGITECH QUICKCAMNBPRO_1 0x08b1QuickCam Notebook Pro
-product LOGITECH QUICKCAMPRO4K 0x08b2  QuickCam Pro 4000
-product LOGITECH QUICKCAMZOOM  0x08b3  QuickCam Zoom
-product LOGITECH QUICKCAMFUSION_1 0x08c1 QuickCam Fusion
-product LOGITECH QUICKCAMORBITMP_1 0x08c2 QuickCam Orbit MP
-product LOGITECH QUICKCAMNBPRO 0x08c3  QuickCam Notebook Pro
-product LOGITECH QUICKCAMPRO5K_1 0x08c5QuickCam Pro 5000
-product LOGITECH QUICKCAMOEM_1 0x08c6  QuickCam OEM
-product LOGITECH QUICKCAMOEM_2 0x08c7  QuickCam OEM
-product LOGITECH QUICKCAMULTVIS0x08c9  QuickCam Ultra Vision
-product LOGITECH QUICKCAMFUSION_2 0x08ca QuickCam Fusion
-product LOGITECH QUICKCAMNBPRO_2 0x08cbQuickCam Notebook Pro
-product LOGITECH QUICKCAMORBITMP_2 0x08cc QuickCam Orbit MP
-product LOGITECH QUICKCAMPRO5K_2 0x08ceQuickCam Pro 5000
-product LOGITECH QUICKCAMPRO9K 0x0990  QuickCam Pro 9000
-product LOGITECH QUICKCAMPRONB 0x0991  QuickCam Pro Notebook
-product LOGITECH QUICKCAMCOMMDLX 0x0992QuickCam Communicate Deluxe
-product LOGITECH QUICKCAMORBITAF 0x0994 QuickCam Orbit AF
-product LOGITECH QUICKCAMCOMMMP0x09a1  QuickCam Communicate MP
-product LOGITECH QUICKCAME3500P0x09a4  QuickCam E 3500 Plus
-product LOGITECH QUICKCAMDLXNB 0x09c1  QuickCam Deluxe Notebook
+product LOGITECH QKCAMEXP  0x0840  QuickCam Express
+product LOGITECH QKCAM 0x0850  QuickCam
+product LOGITECH QKCAMNBDLX0x08a9  QuickCam Notebook Deluxe
+product LOGITECH QKCAMPRO3K0x08b0  QuickCam Pro 3000
+product LOGITECH QKCAMNBPRO_1  0x08b1  QuickCam Notebook Pro
+product LOGITECH QKCAMPRO4K0x08b2  QuickCam Pro 4000
+product LOGITECH QKCAMZOOM 0x08b3  QuickCam Zoom
+product LOGITECH QKCAMFUSION_1 0x08c1  QuickCam Fusion
+product LOGITECH QKCAMORBMP_1  0x08c2  QuickCam Orbit MP
+product LOGITECH QKCAMNBPRO0x08c3  QuickCam Notebook Pro
+product LOGITECH QKCAMPRO5K_1  0x08c5  QuickCam Pro 5000
+product LOGITECH QKCAMOEM_10x08c6  QuickCam OEM
+product LOGITECH QKCAMOEM_20x08c7  QuickCam OEM
+product LOGITECH QKCAMULTVIS   0x08c9  QuickCam Ultra Vision
+product LOGITECH QKCAMFUSION_2 0x08ca  QuickCam Fusion
+product LOGITECH QKCAMNBPRO_2  0x08cb  QuickCam Notebook Pro
+product LOGITECH QKCAMORBMP_2  0x08cc  QuickCam Orbit MP
+product LOGITECH QKCAMPRO5K_2  0x08ce  QuickCam Pro 5000
+product LOGITECH QKCAMPRO9K0x0990  QuickCam Pro 9000
+product LOGITECH QKCAMPRONB0x0991  QuickCam Pro Notebook

Re: usbdevs: logitech: cleanup and new ids

2017-01-22 Thread James Hastings
On 1/23/17, Jonathan Gray <j...@jsg.id.au> wrote:
> On Mon, Jan 23, 2017 at 01:56:20AM -0500, James Hastings wrote:
>> Hello @tech
>>
>> Recently found a pile of old Logitech webcams to test with uvideo(4).
>> s/QUICKCAM/QKCAM.
>> shorten device strings.
>> Add many new Logitech device ids.
>>
>> dev/usb/usbdevs
>> dev/usb/uaudio.c
>> dev/usb/uvideo.c
>
> USB devices normally have their own strings.  usbdevs entries are added
> for non usb-class drivers and if there is a common device without a
> string.  Do any of the devices not have their own strings?
>

One example:

uaudio0 at uhub2 port 1 configuration 1 interface 1 "Logitech product
0x08dd" rev 1.10/1.00 addr 2
uaudio0: audio rev 1.00, 3 mixer controls
audio1 at uaudio0
ugen0 at uhub2 port 1 configuration 1 "Logitech product 0x08dd" rev
1.10/1.00 addr 2

lsusb -v:
Bus 002 Device 002: ID 046d:08dd Logitech, Inc. QuickCam for Notebooks
Device Descriptor:
  bLength18
  bDescriptorType 1
  bcdUSB   1.10
  bDeviceClass0 (Defined at Interface level)
  bDeviceSubClass 0
  bDeviceProtocol 0
  bMaxPacketSize0 8
  idVendor   0x046d Logitech, Inc.
  idProduct  0x08dd QuickCam for Notebooks
  bcdDevice1.00
  iManufacturer   0
  iProduct0
  iSerial 0
  bNumConfigurations  1
  Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength  336
bNumInterfaces  3
bConfigurationValue 1
iConfiguration  0
bmAttributes 0xa0
  (Bus Powered)
  Remote Wakeup
MaxPower  100mA
Interface Descriptor:
  bLength 9
  bDescriptorType 4
  bInterfaceNumber0
  bAlternateSetting   0
  bNumEndpoints   2
  bInterfaceClass   255 Vendor Specific Class
  bInterfaceSubClass255 Vendor Specific Subclass
  bInterfaceProtocol255 Vendor Specific Protocol
  iInterface  0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81  EP 1 IN
bmAttributes1
  Transfer TypeIsochronous
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x  1x 0 bytes
bInterval   1
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82  EP 2 IN
bmAttributes3
  Transfer TypeInterrupt
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0008  1x 8 bytes
bInterval  10
Interface Descriptor:
  bLength 9
  bDescriptorType 4
  bInterfaceNumber0
  bAlternateSetting   1
  bNumEndpoints   2
  bInterfaceClass   255 Vendor Specific Class
  bInterfaceSubClass255 Vendor Specific Subclass
  bInterfaceProtocol255 Vendor Specific Protocol
  iInterface  0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81  EP 1 IN
bmAttributes1
  Transfer TypeIsochronous
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0080  1x 128 bytes
bInterval   1
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82  EP 2 IN
bmAttributes3
  Transfer TypeInterrupt
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x0008  1x 8 bytes
bInterval  10
Interface Descriptor:
  bLength 9
  bDescriptorType 4
  bInterfaceNumber0
  bAlternateSetting   2
  bNumEndpoints   2
  bInterfaceClass   255 Vendor Specific Class
  bInterfaceSubClass255 Vendor Specific Subclass
  bInterfaceProtocol255 Vendor Specific Protocol
  iInterface  0
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81  EP 1 IN
bmAttributes1
  Transfer TypeIsochronous
  Synch Type   None
  Usage Type   Data
wMaxPacketSize 0x00c0  1x 192 bytes
bInterval   1
  Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82  EP 

usbdevs: logitech: cleanup and new ids

2017-01-22 Thread James Hastings
Hello @tech

Recently found a pile of old Logitech webcams to test with uvideo(4).
s/QUICKCAM/QKCAM.
shorten device strings.
Add many new Logitech device ids.

dev/usb/usbdevs
dev/usb/uaudio.c
dev/usb/uvideo.c


Index: dev/usb/uaudio.c
===
RCS file: /cvs/src/sys/dev/usb/uaudio.c,v
retrieving revision 1.122
diff -u -p -r1.122 uaudio.c
--- dev/usb/uaudio.c3 Jan 2017 06:45:58 -   1.122
+++ dev/usb/uaudio.c22 Jan 2017 22:35:43 -
@@ -214,13 +214,13 @@ struct uaudio_devs {
UAUDIO_FLAG_DEPENDENT },
{ { USB_VENDOR_DALLAS, USB_PRODUCT_DALLAS_J6502 },
UAUDIO_FLAG_NO_XU | UAUDIO_FLAG_BAD_ADC },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMNBDLX },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMNBDX_1 },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMPRONB },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMNBPRO_4 },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMPRO4K },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMPRO4K },
UAUDIO_FLAG_BAD_AUDIO },
-   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QUICKCAMZOOM },
+   { { USB_VENDOR_LOGITECH, USB_PRODUCT_LOGITECH_QKCAMZOOM },
UAUDIO_FLAG_BAD_AUDIO },
{ { USB_VENDOR_TELEX, USB_PRODUCT_TELEX_MIC1 },
UAUDIO_FLAG_NO_FRAC }
Index: dev/usb/usbdevs
===
RCS file: /cvs/src/sys/dev/usb/usbdevs,v
retrieving revision 1.673
diff -u -p -r1.673 usbdevs
--- dev/usb/usbdevs 15 Dec 2016 15:42:05 -  1.673
+++ dev/usb/usbdevs 22 Jan 2017 22:35:47 -
@@ -2553,37 +2553,85 @@ product LOGITEC LANW300NU2S 0x0169  LAN-W
 product LOGITECH M2452 0x0203  M2452 keyboard
 product LOGITECH M4848 0x0301  M4848 mouse
 product LOGITECH PAGESCAN  0x040f  PageScan
-product LOGITECH QUICKCAMWEB   0x0801  QuickCam Web
-product LOGITECH WEBCAMC2000x0802  Webcam C200
-product LOGITECH WEBCAMC5000x0807  Webcam C500
-product LOGITECH QUICKCAMPRO   0x0810  QuickCam Pro
-product LOGITECH WEBCAMC3100x081b  Webcam C310
+product LOGITECH QKCAMWEB_10x0801  QuickCam Web
+product LOGITECH WEBCAM200 0x0802  Webcam 200
+product LOGITECH WEBCAM250 0x0804  Webcam 250
+product LOGITECH WEBCAM300 0x0805  Webcam 300
+product LOGITECH WEBCAM500 0x0807  Webcam 500
+product LOGITECH WEBCAM600 0x0808  Webcam 600
+product LOGITECH WEBCAMPRO9K   0x0809  Webcam Pro 9000
+product LOGITECH WEBCAM905 0x080a  Webcam 905
+product LOGITECH WEBCAM120 0x080f  Webcam 120
+product LOGITECH QKCAMPRO_10x0810  QuickCam Pro
+product LOGITECH WEBCAMC1000x0817  Webcam C100
+product LOGITECH WEBCAMC2100x0819  Webcam C210
+product LOGITECH WEBCAMC2600x081a  Webcam C260
+product LOGITECH HDCAMC310 0x081b  HD Webcam C310
+product LOGITECH HDCAMC510 0x081d  HD Webcam C510
+product LOGITECH QKCAMVC   0x0820  QuickCam VC
 product LOGITECH HDPROC910 0x0821  HD Pro Webcam C910
-product LOGITECH QUICKCAMEXP   0x0840  QuickCam Express
-product LOGITECH QUICKCAM  0x0850  QuickCam
-product LOGITECH QUICKCAMNBDLX 0x08a9  QuickCam Notebook Deluxe
-product LOGITECH QUICKCAMPRO3K 0x08b0  QuickCam Pro 3000
-product LOGITECH QUICKCAMNBPRO_1 0x08b1QuickCam Notebook Pro
-product LOGITECH QUICKCAMPRO4K 0x08b2  QuickCam Pro 4000
-product LOGITECH QUICKCAMZOOM  0x08b3  QuickCam Zoom
-product LOGITECH QUICKCAMFUSION_1 0x08c1 QuickCam Fusion
-product LOGITECH QUICKCAMORBITMP_1 0x08c2 QuickCam Orbit MP
-product LOGITECH QUICKCAMNBPRO 0x08c3  QuickCam Notebook Pro
-product LOGITECH QUICKCAMPRO5K_1 0x08c5QuickCam Pro 5000
-product LOGITECH QUICKCAMOEM_1 0x08c6  QuickCam OEM
-product LOGITECH QUICKCAMOEM_2 0x08c7  QuickCam OEM
-product LOGITECH QUICKCAMULTVIS0x08c9  QuickCam Ultra Vision
-product LOGITECH QUICKCAMFUSION_2 0x08ca QuickCam Fusion
-product LOGITECH QUICKCAMNBPRO_2 0x08cbQuickCam Notebook Pro
-product LOGITECH QUICKCAMORBITMP_2 0x08cc QuickCam Orbit MP
-product LOGITECH QUICKCAMPRO5K_2 0x08ceQuickCam Pro 5000
-product LOGITECH QUICKCAMPRO9K 0x0990  QuickCam Pro 9000
-product LOGITECH QUICKCAMPRONB 0x0991  QuickCam Pro Notebook
-product LOGITECH QUICKCAMCOMMDLX 0x0992QuickCam Communicate Deluxe
-product LOGITECH QUICKCAMORBITAF 0x0994 QuickCam Orbit AF
-product LOGITECH QUICKCAMCOMMMP0x09a1  QuickCam Communicate MP
-product LOGITECH QUICKCAME3500P0x09a4  QuickCam E 3500 Plus
-product LOGITECH QUICKCAMDLXNB 0x09c1  QuickCam Deluxe Notebook
+product LOGITECH HDCAMB910 0x0823  HD Webcam B910
+product LOGITECH WEBCAMC1600x0824  Webcam C160
+product LOGITECH WEBCAMC2700x0825  Webcam C270
+product LOGITECH HDCAMC525 0x0826  HD Webcam C525
+product LOGITECH 

Re: ral(4) support RT5390 and RT5392

2016-08-16 Thread James Hastings
On 8/16/16, Stefan Sperling  wrote:
>
> Your patch can't be applied with patch(1) because directory
> components are missing on the Index: lines even though modified
> files are spread across several directories. Could you please
> send a patch which uses paths relative to /usr/src ?
>

Index: share/man/man4/ral.4
===
RCS file: /cvs/src/share/man/man4/ral.4,v
retrieving revision 1.109
diff -u -p -r1.109 ral.4
--- share/man/man4/ral.416 Jun 2016 17:25:32 -  1.109
+++ share/man/man4/ral.416 Aug 2016 20:22:26 -
@@ -27,7 +27,7 @@
 The
 .Nm
 driver supports PCI/PCIe/CardBus wireless adapters based on the Ralink RT2500,
-RT2501, RT2600, RT2700, RT2800 and RT3090 chipsets.
+RT2501, RT2600, RT2700, RT2800, RT3090 and RT3900E chipsets.
 .Pp
 The RT2500 chipset is the first generation of 802.11b/g adapters from Ralink.
 It consists of two integrated chips, an RT2560 MAC/BBP and an RT2525 radio
@@ -64,6 +64,13 @@ bandwidth.)
 The RT3090 chipset is the first generation of single-chip 802.11n adapters
 from Ralink.
 .Pp
+The RT3900E chipset is a single-chip 802.11n adapter from Ralink.
+The MAC/Baseband Processor can be an RT5390 or RT5392.
+The RT5390 chip operates in the 2GHz spectrum and supports one transmit path
+and one receiver path (1T1R).
+The RT5392 chip operates in the 2GHz spectrum and supports up to two transmit
+paths and two receiver paths (2T2R).
+.Pp
 These are the modes the
 .Nm
 driver can operate in:
Index: sys/dev/ic/rt2860.c
===
RCS file: /cvs/src/sys/dev/ic/rt2860.c,v
retrieving revision 1.90
diff -u -p -r1.90 rt2860.c
--- sys/dev/ic/rt2860.c 13 Apr 2016 10:49:26 -  1.90
+++ sys/dev/ic/rt2860.c 16 Aug 2016 20:22:34 -
@@ -17,7 +17,7 @@
  */

 /*-
- * Ralink Technology RT2860/RT3090/RT3390/RT3562 chipset driver
+ * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver
  * http://www.ralinktech.com/
  */

@@ -121,8 +121,11 @@ void   rt2860_set_basicrates(struct rt286
 void   rt2860_select_chan_group(struct rt2860_softc *, int);
 void   rt2860_set_chan(struct rt2860_softc *, u_int);
 void   rt3090_set_chan(struct rt2860_softc *, u_int);
+void   rt5390_set_chan(struct rt2860_softc *, u_int);
 intrt3090_rf_init(struct rt2860_softc *);
+void   rt5390_rf_init(struct rt2860_softc *);
 void   rt3090_rf_wakeup(struct rt2860_softc *);
+void   rt5390_rf_wakeup(struct rt2860_softc *);
 intrt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
uint8_t *);
 void   rt3090_rf_setup(struct rt2860_softc *);
@@ -140,9 +143,10 @@ void   rt2860_delete_key(struct ieee80211
 #if NBPFILTER > 0
 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
 #endif
-const char *   rt2860_get_rf(uint8_t);
+const char *   rt2860_get_rf(uint16_t);
 intrt2860_read_eeprom(struct rt2860_softc *);
 intrt2860_bbp_init(struct rt2860_softc *);
+void   rt5390_bbp_init(struct rt2860_softc *);
 intrt2860_txrx_enable(struct rt2860_softc *);
 intrt2860_init(struct ifnet *);
 void   rt2860_stop(struct ifnet *, int);
@@ -168,6 +172,8 @@ static const struct {
uint8_t val;
 } rt2860_def_bbp[] = {
RT2860_DEF_BBP
+},rt5390_def_bbp[] = {
+   RT5390_DEF_BBP
 };

 static const struct rfprog {
@@ -190,6 +196,10 @@ static const struct {
RT3070_DEF_RF
 }, rt3572_def_rf[] = {
RT3572_DEF_RF
+}, rt5390_def_rf[] = {
+   RT5390_DEF_RF
+}, rt5392_def_rf[] = {
+   RT5392_DEF_RF
 };

 int
@@ -2086,6 +2096,9 @@ rt2860_select_chan_group(struct rt2860_s
uint32_t tmp;
uint8_t agc;

+   /* Wait for BBP to settle */
+   DELAY(1000);
+
rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
@@ -2293,6 +2306,107 @@ rt3090_set_chan(struct rt2860_softc *sc,
rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
 }

+void
+rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
+{
+   uint8_t h20mhz, rf, tmp;
+   int8_t txpow1, txpow2;
+   int i;
+
+   /* RT5390 is 2GHz only */
+   KASSERT(chan >= 1 && chan <= 14);
+
+   /* find the settings for this channel (we know it exists) */
+   for (i = 0; rt2860_rf2850[i].chan != chan; i++);
+
+   /* use Tx power values from EEPROM */
+   txpow1 = sc->txpow1[i];
+   txpow2 = sc->txpow2[i];
+
+   rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
+   rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
+   rf = rt3090_rf_read(sc, 11);
+   rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
+   rt3090_rf_write(sc, 11, rf);
+
+   rf = rt3090_rf_read(sc, 49);
+   rf = (rf & ~0x3f) | 

ral(4) support RT5390 and RT5392

2016-08-08 Thread James Hastings
Hi all,

The following patch adds RT5390/RT5392 support to ral(4).

Ported from FreeBSD r278551 and r36.

Running smoothly with RT3090 and various RT5390 cards.

Requires updated ral-rt2860 firmware

Index: ral.4
===
RCS file: /cvs/src/share/man/man4/ral.4,v
retrieving revision 1.109
diff -u -p -r1.109 ral.4
--- ral.4   16 Jun 2016 17:25:32 -  1.109
+++ ral.4   9 Aug 2016 01:16:11 -
@@ -27,7 +27,7 @@
 The
 .Nm
 driver supports PCI/PCIe/CardBus wireless adapters based on the Ralink RT2500,
-RT2501, RT2600, RT2700, RT2800 and RT3090 chipsets.
+RT2501, RT2600, RT2700, RT2800, RT3090 and RT3900E chipsets.
 .Pp
 The RT2500 chipset is the first generation of 802.11b/g adapters from Ralink.
 It consists of two integrated chips, an RT2560 MAC/BBP and an RT2525 radio
@@ -64,6 +64,13 @@ bandwidth.)
 The RT3090 chipset is the first generation of single-chip 802.11n adapters
 from Ralink.
 .Pp
+The RT3900E chipset is a single-chip 802.11n adapter from Ralink.
+The MAC/Baseband Processor can be an RT5390 or RT5392.
+The RT5390 chip operates in the 2GHz spectrum and supports one transmit path
+and one receiver path (1T1R).
+The RT5392 chip operates in the 2GHz spectrum and supports up to two transmit
+paths and two receiver paths (2T2R).
+.Pp
 These are the modes the
 .Nm
 driver can operate in:
Index: pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1802
diff -u -p -r1.1802 pcidevs
--- pcidevs 31 Jul 2016 07:36:16 -  1.1802
+++ pcidevs 9 Aug 2016 02:40:33 -
@@ -6436,6 +6436,10 @@ product RALINK RT35620x3562  RT3562
 product RALINK RT3592  0x3592  RT3592
 product RALINK RT3593  0x3593  RT3593
 product RALINK RT5390  0x5390  RT5390
+product RALINK RT5392  0x5392  RT5392
+product RALINK RT5390_10x539a  RT5390
+product RALINK RT5390_20x539b  RT5390
+product RALINK RT5390_30x539f  RT5390

 /* RDC products */
 product RDC R1010_IDE  0x1010  R1010 IDE
Index: pcidevs.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.1796
diff -u -p -r1.1796 pcidevs.h
--- pcidevs.h   31 Jul 2016 07:37:04 -  1.1796
+++ pcidevs.h   9 Aug 2016 03:13:34 -
@@ -6441,6 +6441,10 @@
 #definePCI_PRODUCT_RALINK_RT3592   0x3592  /* RT3592 */
 #definePCI_PRODUCT_RALINK_RT3593   0x3593  /* RT3593 */
 #definePCI_PRODUCT_RALINK_RT5390   0x5390  /* RT5390 */
+#definePCI_PRODUCT_RALINK_RT5392   0x5392  /* RT5392 */
+#definePCI_PRODUCT_RALINK_RT5390_1 0x539a  /* RT5390 */
+#definePCI_PRODUCT_RALINK_RT5390_2 0x539b  /* RT5390 */
+#definePCI_PRODUCT_RALINK_RT5390_3 0x539f  /* RT5390 */

 /* RDC products */
 #definePCI_PRODUCT_RDC_R1010_IDE   0x1010  /* R1010 IDE */
Index: pcidevs_data.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.1791
diff -u -p -r1.1791 pcidevs_data.h
--- pcidevs_data.h  31 Jul 2016 07:37:04 -  1.1791
+++ pcidevs_data.h  9 Aug 2016 03:14:17 -
@@ -22496,6 +22496,22 @@ static const struct pci_known_product pc
"RT5390",
},
{
+   PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5392,
+   "RT5392",
+   },
+   {
+   PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_1,
+   "RT5390",
+   },
+   {
+   PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_2,
+   "RT5390",
+   },
+   {
+   PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_3,
+   "RT5390",
+   },
+   {
PCI_VENDOR_RDC, PCI_PRODUCT_RDC_R1010_IDE,
"R1010 IDE",
},
Index: if_ral_pci.c
===
RCS file: /cvs/src/sys/dev/pci/if_ral_pci.c,v
retrieving revision 1.24
diff -u -p -r1.24 if_ral_pci.c
--- if_ral_pci.c24 Nov 2015 17:11:39 -  1.24
+++ if_ral_pci.c9 Aug 2016 02:45:18 -
@@ -135,7 +135,12 @@ const struct pci_matchid ral_pci_devices
{ PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3092 },
{ PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3562 },
{ PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3592 },
-   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3593 }
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT3593 },
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390 },
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5392 },
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_1 },
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_2 },
+   { PCI_VENDOR_RALINK, PCI_PRODUCT_RALINK_RT5390_3 }
 };

 int
Index: 

Re: UEFI Boot Report: Screen corruption and kernel panic

2016-02-02 Thread James Hastings
On 2/2/16, Mark Kettenis <mark.kette...@xs4all.nl> wrote:
>> Date: Tue, 2 Feb 2016 21:32:13 +0100 (CET)
>> From: Mark Kettenis <mark.kette...@xs4all.nl>
>>
>> > Date: Tue, 2 Feb 2016 14:14:04 -0500
>> > From: James Hastings <mooset...@gmail.com>
>> >
>> > Native screen size is 1366x768
>> >
>> > Results:
>> > ei.config_acpi: 0x66bfe014
>> > ei.config_smbios: 0x66abef98
>> > ei.fb_addr: 0x8000
>> > ei.fb_size: 0x42
>> > ei.fb_width: 1024
>> > ei.fb_height: 768
>> > ei.fb_pixpsl: 1024
>>
>> Right.  Looks like the firmware is giving us bogus values.  But
>> perhaps there is something subtly wrong with our bootloader code.
>
> Does the diff below help?
>
> Index: efiboot.c
> ===
> RCS file: /cvs/src/sys/arch/amd64/stand/efiboot/efiboot.c,v
> retrieving revision 1.10
> diff -u -p -r1.10 efiboot.c
> --- efiboot.c 26 Nov 2015 20:26:20 -  1.10
> +++ efiboot.c 2 Feb 2016 21:26:49 -
> @@ -526,7 +526,7 @@ efi_makebootargs(void)
>   bestsiz = gopsiz;
>   }
>   }
> - if (bestmode >= 0 && conout->Mode->Mode != bestmode) {
> + if (bestmode >= 0) {
>   status = EFI_CALL(gop->SetMode, gop, bestmode);
>   if (EFI_ERROR(status))
>   printf("GOP setmode failed(%d)\n", status);
>

Yes! Now I can read the console. Looks great.

Thank you.