> Date: Sat, 13 Jan 2018 23:08:55 +
> From: Dimitris Papastamos
>
> > + case CPU_ID_CORTEX_A15:
> > + case CPU_ID_CORTEX_A57:
> > + case CPU_ID_CORTEX_A72:
> > + /*
> > +* Vulnerable; BPIALL is "not effective" so must use
> > +* ICIALLU
> + case CPU_ID_CORTEX_A15:
> + case CPU_ID_CORTEX_A57:
> + case CPU_ID_CORTEX_A72:
> + /*
> + * Vulnerable; BPIALL is "not effective" so must use
> + * ICIALLU and hope the firmware set the magic bit in
> + * the ACTLR that actually
The diff below improves our resiliency against "variant 2". Like on
x86 the defence is based on flushing the branch predictor cache at the
appropriate points.
It turns out we are already in pretty good shape as we are already
flushing on context switches. I believe we're forced to do that