Re: rw locks vs memory barriers and adaptive spinning

2017-10-11 Thread Mateusz Guzik
On Wed, Oct 11, 2017 at 03:15:42PM +0200, Martin Pieuchot wrote: > On 10/10/17(Tue) 20:19, Mateusz Guzik wrote: > > On Tue, Oct 10, 2017 at 10:15:48AM +0200, Martin Pieuchot wrote: > > > Hello Mateusz, > > > > > > On 09/10/17(Mon) 21:43, Mateusz Guzik wrote: > > > > I was looking at rw lock code

Re: rw locks vs memory barriers and adaptive spinning

2017-10-11 Thread Martin Pieuchot
On 10/10/17(Tue) 20:19, Mateusz Guzik wrote: > On Tue, Oct 10, 2017 at 10:15:48AM +0200, Martin Pieuchot wrote: > > Hello Mateusz, > > > > On 09/10/17(Mon) 21:43, Mateusz Guzik wrote: > > > I was looking at rw lock code out of curiosity and noticed you always do > > > membar_enter which on

Re: rw locks vs memory barriers and adaptive spinning

2017-10-10 Thread Mateusz Guzik
On Tue, Oct 10, 2017 at 10:15:48AM +0200, Martin Pieuchot wrote: > Hello Mateusz, > > On 09/10/17(Mon) 21:43, Mateusz Guzik wrote: > > I was looking at rw lock code out of curiosity and noticed you always do > > membar_enter which on MP-enabled amd64 kernel translates to mfence. > > This makes the

Re: rw locks vs memory barriers and adaptive spinning

2017-10-10 Thread Martin Pieuchot
Hello Mateusz, On 09/10/17(Mon) 21:43, Mateusz Guzik wrote: > I was looking at rw lock code out of curiosity and noticed you always do > membar_enter which on MP-enabled amd64 kernel translates to mfence. > This makes the entire business a little bit slower. > > Interestingly you already have

rw locks vs memory barriers and adaptive spinning

2017-10-09 Thread Mateusz Guzik
Hello, I was looking at rw lock code out of curiosity and noticed you always do membar_enter which on MP-enabled amd64 kernel translates to mfence. This makes the entire business a little bit slower. Interestingly you already have relevant macros for amd64: #define membar_enter_after_atomic()