Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
From: "Theo de Raadt" Date: Sun, 25 Sep 2022 18:29:12 -0600 > This is not helping. > > Please send Scott private replies regarding his diff. Oh, sorry. I will reply to Scott privately. -- ASOU Masato > Masato Asou wrote: > >> Hi, >> >> I have new AMD laptop. The dmesg is posted below: >> >> OpenBSD 7.2 (GENERIC.MP) #2: Mon Sep 26 09:09:17 JST 2022 >> a...@hp-obsd.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP >> real mem = 7844245504 (7480MB) >> avail mem = 7589105664 (7237MB) >> random: good seed from bootblocks >> mpath0 at root >> scsibus0 at mpath0: 256 targets >> mainbus0 at root >> bios0 at mainbus0: SMBIOS rev. 3.3 @ 0xbc55d000 (35 entries) >> bios0: vendor AMI version "F.05" date 06/15/2022 >> bios0: HP HP Laptop 14s-fq2xxx >> acpi0 at bios0: ACPI 6.2Undefined scope: \\_SB_.PCI0.28 >> >> acpi0: sleep states S0 S4 S5 >> acpi0: tables DSDT FACP MSDM SSDT IVRS SSDT FIDT MCFG HPET VFCT SSDT TPM2 >> SSDT CRAT CDIT SSDT SSDT SSDT SSDT SSDT SSDT SSDT WSMT APIC SSDT SSDT SSDT >> SSDT SSDT SSDT FPDT BGRT >> acpi0: wakeup devices GPP1(S4) GP17(S4) GPP0(S4) >> acpitimer0 at acpi0: 3579545 Hz, 32 bits >> acpimcfg0 at acpi0 >> acpimcfg0: addr 0xf000, bus 0-127 >> acpihpet0 at acpi0: 14318180 Hz >> acpimadt0 at acpi0 addr 0xfee0: PC-AT compat >> cpu0 at mainbus0: apid 0 (boot processor) >> cpu0: MSR C001_0064: en 1 base 2 mul 92 div 8 freq 23 Hz >> cpu0: MSR C001_0065: en 1 base 2 mul 90 div 10 freq 18 Hz >> cpu0: MSR C001_0066: en 1 base 2 mul 96 div 12 freq 16 Hz >> cpu0: MSR C001_0067: en 0 >> cpu0: MSR C001_0068: en 0 >> cpu0: MSR C001_0069: en 0 >> cpu0: MSR C001_006A: en 0 >> cpu0: MSR C001_006B: en 0 >> cpu0: AMD Ryzen 5 5625U with Radeon Graphics, 2295.73 MHz, 19-50-00 >> cpu0: >> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES >> cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB >> 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache >> tsc: calibrating with acpihpet0: 2295691309 Hz >> cpu0: smt 0, core 0, package 0 >> mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges >> cpu0: apic clock running at 99MHz >> cpu0: mwait min=64, max=64, C-substates=1.1, IBE >> cpu1 at mainbus0: apid 1 (application processor) >> cpu1: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 >> cpu1: >> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES >> cpu1: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB >> 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache >> cpu1: smt 1, core 0, package 0 >> cpu2 at mainbus0: apid 2 (application processor) >> cpu2: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 >> cpu2: >> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES >> cpu2: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB >> 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache >> cpu2: smt 0, core 1, package 0 >> cpu3 at mainbus0: apid 3 (application processor) >> cpu3: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 >> cpu3: >> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES >> cpu3: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB >> 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache >> cpu3: smt 1, core 1, package 0 >> cpu4 at mainbus0: apid
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
This is not helping. Please send Scott private replies regarding his diff. Masato Asou wrote: > Hi, > > I have new AMD laptop. The dmesg is posted below: > > OpenBSD 7.2 (GENERIC.MP) #2: Mon Sep 26 09:09:17 JST 2022 > a...@hp-obsd.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP > real mem = 7844245504 (7480MB) > avail mem = 7589105664 (7237MB) > random: good seed from bootblocks > mpath0 at root > scsibus0 at mpath0: 256 targets > mainbus0 at root > bios0 at mainbus0: SMBIOS rev. 3.3 @ 0xbc55d000 (35 entries) > bios0: vendor AMI version "F.05" date 06/15/2022 > bios0: HP HP Laptop 14s-fq2xxx > acpi0 at bios0: ACPI 6.2Undefined scope: \\_SB_.PCI0.28 > > acpi0: sleep states S0 S4 S5 > acpi0: tables DSDT FACP MSDM SSDT IVRS SSDT FIDT MCFG HPET VFCT SSDT TPM2 > SSDT CRAT CDIT SSDT SSDT SSDT SSDT SSDT SSDT SSDT WSMT APIC SSDT SSDT SSDT > SSDT SSDT SSDT FPDT BGRT > acpi0: wakeup devices GPP1(S4) GP17(S4) GPP0(S4) > acpitimer0 at acpi0: 3579545 Hz, 32 bits > acpimcfg0 at acpi0 > acpimcfg0: addr 0xf000, bus 0-127 > acpihpet0 at acpi0: 14318180 Hz > acpimadt0 at acpi0 addr 0xfee0: PC-AT compat > cpu0 at mainbus0: apid 0 (boot processor) > cpu0: MSR C001_0064: en 1 base 2 mul 92 div 8 freq 23 Hz > cpu0: MSR C001_0065: en 1 base 2 mul 90 div 10 freq 18 Hz > cpu0: MSR C001_0066: en 1 base 2 mul 96 div 12 freq 16 Hz > cpu0: MSR C001_0067: en 0 > cpu0: MSR C001_0068: en 0 > cpu0: MSR C001_0069: en 0 > cpu0: MSR C001_006A: en 0 > cpu0: MSR C001_006B: en 0 > cpu0: AMD Ryzen 5 5625U with Radeon Graphics, 2295.73 MHz, 19-50-00 > cpu0: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > tsc: calibrating with acpihpet0: 2295691309 Hz > cpu0: smt 0, core 0, package 0 > mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges > cpu0: apic clock running at 99MHz > cpu0: mwait min=64, max=64, C-substates=1.1, IBE > cpu1 at mainbus0: apid 1 (application processor) > cpu1: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu1: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu1: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu1: smt 1, core 0, package 0 > cpu2 at mainbus0: apid 2 (application processor) > cpu2: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu2: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu2: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu2: smt 0, core 1, package 0 > cpu3 at mainbus0: apid 3 (application processor) > cpu3: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu3: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu3: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB > 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache > cpu3: smt 1, core 1, package 0 > cpu4 at mainbus0: apid 4 (application processor) > cpu4: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 > cpu4: >
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
Hi, I have new AMD laptop. The dmesg is posted below: OpenBSD 7.2 (GENERIC.MP) #2: Mon Sep 26 09:09:17 JST 2022 a...@hp-obsd.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 7844245504 (7480MB) avail mem = 7589105664 (7237MB) random: good seed from bootblocks mpath0 at root scsibus0 at mpath0: 256 targets mainbus0 at root bios0 at mainbus0: SMBIOS rev. 3.3 @ 0xbc55d000 (35 entries) bios0: vendor AMI version "F.05" date 06/15/2022 bios0: HP HP Laptop 14s-fq2xxx acpi0 at bios0: ACPI 6.2Undefined scope: \\_SB_.PCI0.28 acpi0: sleep states S0 S4 S5 acpi0: tables DSDT FACP MSDM SSDT IVRS SSDT FIDT MCFG HPET VFCT SSDT TPM2 SSDT CRAT CDIT SSDT SSDT SSDT SSDT SSDT SSDT SSDT WSMT APIC SSDT SSDT SSDT SSDT SSDT SSDT FPDT BGRT acpi0: wakeup devices GPP1(S4) GP17(S4) GPP0(S4) acpitimer0 at acpi0: 3579545 Hz, 32 bits acpimcfg0 at acpi0 acpimcfg0: addr 0xf000, bus 0-127 acpihpet0 at acpi0: 14318180 Hz acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: MSR C001_0064: en 1 base 2 mul 92 div 8 freq 23 Hz cpu0: MSR C001_0065: en 1 base 2 mul 90 div 10 freq 18 Hz cpu0: MSR C001_0066: en 1 base 2 mul 96 div 12 freq 16 Hz cpu0: MSR C001_0067: en 0 cpu0: MSR C001_0068: en 0 cpu0: MSR C001_0069: en 0 cpu0: MSR C001_006A: en 0 cpu0: MSR C001_006B: en 0 cpu0: AMD Ryzen 5 5625U with Radeon Graphics, 2295.73 MHz, 19-50-00 cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache tsc: calibrating with acpihpet0: 2295691309 Hz cpu0: smt 0, core 0, package 0 mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges cpu0: apic clock running at 99MHz cpu0: mwait min=64, max=64, C-substates=1.1, IBE cpu1 at mainbus0: apid 1 (application processor) cpu1: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu1: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu1: smt 1, core 0, package 0 cpu2 at mainbus0: apid 2 (application processor) cpu2: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu2: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu2: smt 0, core 1, package 0 cpu3 at mainbus0: apid 3 (application processor) cpu3: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,ERMS,INVPCID,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,PKU,IBPB,IBRS,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu3: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu3: smt 1, core 1, package 0 cpu4 at mainbus0: apid 4 (application processor) cpu4: AMD Ryzen 5 5625U with Radeon Graphics, 2295.69 MHz, 19-50-00 cpu4:
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
Hi, The dmesg is posted below: OpenBSD 7.2 (GENERIC.MP) #2: Mon Sep 26 09:09:29 JST 2022 a...@amd-obsd.my.domain:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 34256752640 (32669MB) avail mem = 33201127424 (31663MB) random: good seed from bootblocks mpath0 at root scsibus0 at mpath0: 256 targets mainbus0 at root bios0 at mainbus0: SMBIOS rev. 2.8 @ 0xdb64 (63 entries) bios0: vendor American Megatrends Inc. version "9015" date 03/03/2020 bios0: MouseComputer Co.,Ltd. LM-AG400 acpi0 at bios0: ACPI 6.0 acpi0: sleep states S0 S3 S4 S5 acpi0: tables DSDT FACP APIC FPDT FIDT SSDT MSDM SSDT SSDT MCFG HPET UEFI BGRT TPM2 IVRS PCCT SSDT CRAT CDIT SSDT SSDT SSDT acpi0: wakeup devices GPP0(S4) GPP1(S4) GPP3(S4) GPP4(S4) GPP5(S4) GPP6(S4) GPP7(S4) GPP8(S4) X161(S4) GPP9(S4) X162(S4) GPPA(S4) GPPB(S4) GPPC(S4) GPPD(S4) GPPE(S4) [...] acpitimer0 at acpi0: 3579545 Hz, 32 bits acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: MSR C001_0064: en 1 base 2 mul 144 div 8 freq 36 Hz cpu0: MSR C001_0065: en 1 base 2 mul 140 div 10 freq 28 Hz cpu0: MSR C001_0066: en 1 base 2 mul 132 div 12 freq 22 Hz cpu0: MSR C001_0067: en 0 cpu0: MSR C001_0068: en 0 cpu0: MSR C001_0069: en 0 cpu0: MSR C001_006A: en 0 cpu0: MSR C001_006B: en 0 cpu0: AMD Ryzen 7 3700X 8-Core Processor, 3593.49 MHz, 17-71-00 cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu0: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache tsc: calibrating with acpitimer0: 3593266153 Hz cpu0: smt 0, core 0, package 0 mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges cpu0: apic clock running at 99MHz cpu0: mwait min=64, max=64, C-substates=1.1, IBE cpu1 at mainbus0: apid 2 (application processor) cpu1: AMD Ryzen 7 3700X 8-Core Processor, 3593.27 MHz, 17-71-00 cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu1: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu1: smt 0, core 1, package 0 cpu2 at mainbus0: apid 4 (application processor) cpu2: AMD Ryzen 7 3700X 8-Core Processor, 3593.27 MHz, 17-71-00 cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu2: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu2: smt 0, core 2, package 0 cpu3 at mainbus0: apid 6 (application processor) cpu3: AMD Ryzen 7 3700X 8-Core Processor, 3593.26 MHz, 17-71-00 cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu3: 32KB 64b/line 8-way D-cache, 32KB 64b/line 8-way I-cache, 512KB 64b/line 8-way L2 cache, 16MB 64b/line 16-way L3 cache cpu3: smt 0, core 3, package 0 cpu4 at mainbus0: apid 8 (application processor) cpu4: AMD Ryzen 7 3700X 8-Core Processor, 3593.27 MHz, 17-71-00 cpu4: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,IBS,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,PQM,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBPB,STIBP,SSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu4: 32KB
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
Scott Cheloha [2022-09-23, 14:51 -0500]: > On Fri, Sep 23, 2022 at 10:40:19PM +0300, Timo Myyr?? wrote: > >> Scott Cheloha [2022-09-23, 09:16 -0500]: >> >> > [...] >> > >> > Test results? Clues on reading the configuration space? >> > >> > [...] >> >> Hi, >> >> Here's a dmesg from thinkpad e485: > > Thanks for testing. > >> Does these timers affect the booting of kernel? Once I select the kernel >> to boot by pressing enter on "bsd>" line, the boot process takes about >> 18s to proceed from the "booting sr0a:/bsd". > > The patch reads a couple MSRs and prints ~10 additional lines during > boot from the primary CPU. The computed TSC frequency is not used by > the kernel, only printed so I can check whether my code is correct. > > It should have zero impact on the length of the boot. It should not > change any runtime behavior whatsoever. > > Your boot probably should not be taking that long, but I can't imagine > how my patch would cause such a dramatic change. > > If you reverse the patch, what happens? > I haven't been keeping track of boot times but I doubt it is new issue with this laptop. Current cold boot seemed to pass the "counters" part in about 5s so it varies a bit. I'll see if I find the time to dig through the code to see what boot process is actually doing at that point. >> OpenBSD 7.2 (GENERIC.MP) #20: Fri Sep 23 22:27:31 EEST 2022 >> t...@asteroid.bittivirhe.fi:/usr/src/sys/arch/amd64/compile/GENERIC.MP >> [...] >> cpu0 at mainbus0: apid 0 (boot processor) >> cpu0: MSR C001_0064: en 1 base 2 mul 100 div 10 freq 20 Hz >> cpu0: MSR C001_0065: en 1 base 2 mul 102 div 12 freq 17 Hz >> cpu0: MSR C001_0066: en 1 base 2 mul 96 div 12 freq 16 Hz >> cpu0: MSR C001_0067: en 0 >> cpu0: MSR C001_0068: en 0 >> cpu0: MSR C001_0069: en 0 >> cpu0: MSR C001_006A: en 0 >> cpu0: MSR C001_006B: en 0 >> cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.30 MHz, 17-11-00 >> cpu0: >> FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES >> cpu0: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB >> 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache >> tsc: calibrating with acpihpet0: 1996264149 Hz > > Your family 17h CPU has a computed P0 frequency of 2000MHz. The > calibrated TSC frequency is 1996264149 Hz. > > That seems right to me, thank you for testing.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
Scott Cheloha wrote: > > And it is the wrong time in the release cycle for this. > > This doesn't need to make release, I'm just gauging interest and > testing code. But you didn't say that in your email. But Worse, you didn't think that you need to say it.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
On Sat, Sep 24, 2022 at 11:06:24AM +1000, Jonathan Gray wrote:
> On Fri, Sep 23, 2022 at 09:16:25AM -0500, Scott Cheloha wrote:
> > Hi,
> >
> > TL;DR:
> >
> > I want to compute the TSC frequency on AMD CPUs using the methods laid
> > out in the AMD manuals instead of calibrating the TSC by hand.
> >
> > If you have an AMD CPU with an invariant TSC, please apply this patch,
> > recompile/boot the resulting kernel, and send me the resulting dmesg.
> >
> > Family 10h-16h CPUs are especially interesting. If you've got one,
> > don't be shy!
> >
> > Long explanation:
> >
> > On AMD CPUs we calibrate the TSC with a separate timer. This is slow
> > and introduces error. I also worry about a future where legacy timers
> > are absent or heavily gated (read: useless).
> >
> > This patch adds most of the code needed to compute the TSC frequency
> > on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an
> > invariant TSC so they are irrelevant.
> >
> > I have riddled the code with printf(9) calls so I can work out what's
> > wrong by hand if a test result makes no sense.
> >
> > The only missing piece is code to read the configuration space on
> > family 10h-16h CPUs to determine how many boosted P-states we need to
> > skip to get to the MSR describing the software P0 state. I would
> > really appreciate it if someone could explain how to do this at this
> > very early point in boot. jsg@ pointed me to pci_conf_read(9), but
> > I'm a little confused about how I get the needed pci* inputs at this
> > point in boot.
>
> I also said you shouldn't be looking at pci devices for this.
What you want to look at is section 2.1.4 of this:
https://developer.amd.com/wp-content/resources/56255_3_03.PDF
It describes what you need to do. It's for family 17 but I would guess
that there is an equivalent family 10/12/etc doc, and I'd be surprised
if any of this has changed in a long time.
If you can't figure it out, I'd suggest that we don't do this for
family 10/12/etc and use the old method for CPUs that don't have the
MSRs you need. I also sorta share jsg's opinion below, this feels
like a solution for a problem that really doesn't exist.
-ml
>
> I remain unconvinced that all of this is worth it compared to
> calibrating off a timer with a known rate. And it is the wrong time in
> the release cycle for this.
>
> Boost could be disabled for the measurement if need by.
>
> AMD64 Architecture Programmer's Manual
> Volume 2: System Programming
> Publication No. 24593
> Revision 3.38
>
> "17.2 Core Performance Boost
> ...
> CPB can be disabled using the CPBDis field of the Hardware Configuration
> Register (HWCR MSR) on the appropriate core. When CPB is disabled,
> hardware limits the frequency and voltage of the core to those defined
> by P0.
>
> Support for core performance boost is indicated by
> CPUID Fn8000_0007_EDX[CPB] = 1."
>
> "3.2.10 Hardware Configuration Register (HWCR)
> ...
> CpbDis. Bit 25. Core performance boost disable. When set to 1, core
> performance boost is disabled.
> "
>
> Processor Programming Reference (PPR)
> for AMD Family 17h Model 01h, Revision B1 Processors
> 54945 Rev 1.14 - April 15, 2017
>
> "MSRC001_0015 [Hardware Configuration] (HWCR)
>
> 25 CpbDis: core performance boost disable. Read-write.
> Reset: 0. 0=CPB is requested to be enabled. 1=CPB is disabled.
> Specifies whether core performance boost is requested to be enabled or
> disabled. If core performance boost is disabled while a core is in a
> boosted P-state, the core automatically transitions to the highest
> performance non-boosted P-state."
>
> also mentioned in
>
> BIOS and Kernel Developer's Guide (BKDG)
> For AMD Family 10h Processors
> 31116 Rev 3.48 - April 22, 2010
>
> >
> > --
> >
> > Test results? Clues on reading the configuration space?
> >
> > -Scott
> >
> > Index: tsc.c
> > ===
> > RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
> > retrieving revision 1.29
> > diff -u -p -r1.29 tsc.c
> > --- tsc.c 22 Sep 2022 04:57:08 - 1.29
> > +++ tsc.c 23 Sep 2022 14:04:22 -
> > @@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci)
> > return (0);
> > }
> >
> > +uint64_t
> > +tsc_freq_msr(struct cpu_info *ci)
> > +{
> > + uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier;
> > + uint32_t msr, off = 0;
> > +
> > + if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
> > + return 0;
> > +
> > + /*
> > +* All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit.
> > +* If TscFreqSel is not set the TSC does not advance at the P0
> > +* frequency, in which case something is wrong and we need to
> > +* calibrate by hand.
> > +*/
> > +#define HWCR_TSCFREQSEL (1 << 24)
> > + if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */
> > + return 0;
> > +#undef HWCR_TSCFREQSEL
> > +
> > + /*
> > +* For families 10h, 12h, 14h, 15h, and 16h, we need to skip
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
On Fri, Sep 23, 2022 at 07:46:55PM -0600, Theo de Raadt wrote: > > And it is the wrong time in the release cycle for this. > > No kidding. > > As this makes absolutely no difference for any existing code in 7.2, > except the strong hazard of accidentally breaking a machine. It does not need to make release.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
On Sat, Sep 24, 2022 at 11:06:24AM +1000, Jonathan Gray wrote: > On Fri, Sep 23, 2022 at 09:16:25AM -0500, Scott Cheloha wrote: > > [...] > > > > The only missing piece is code to read the configuration space on > > family 10h-16h CPUs to determine how many boosted P-states we need to > > skip to get to the MSR describing the software P0 state. I would > > really appreciate it if someone could explain how to do this at this > > very early point in boot. jsg@ pointed me to pci_conf_read(9), but > > I'm a little confused about how I get the needed pci* inputs at this > > point in boot. > > I also said you shouldn't be looking at pci devices for this. Right, but the manual says that's where the information I want is located. I might be wrong, of course. Can't know until I get a test on a CPU in one of the relevant families. > I remain unconvinced that all of this is worth it compared to > calibrating off a timer with a known rate. For Intel CPUs we use CPUID to determine the TSC frequency where the leaf is available. It seems "fair," for lack of a better word, to make an effort to do the same for AMD CPUs. The other available timers with known frequencies are not great and they might be getting worse. The ISA timer is heavily gated out of the box on many contemporary machines where it is available. You can toggle the gating in the BIOS for now.The PM Timer and the HPET have been slow to read for years. I doubt these timers will improve. At minimum, I think it's safe to say that they are not a priority. They are considered "legacy" hardware, and you know what happens to the legacy stuff. Calibrating the TSC with one of these other timers introduces error: 1. jmc@'s machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 2 mul 100 div 10 freq 20 Hz tsc: calibrating with acpihpet0: 1996260074 Hz 2. robert@'s machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 2 mul 156 div 8 freq 39 Hz tsc: calibrating with acpihpet0: 3892696616 Hz 3. Timo Myrra's machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 2 mul 100 div 10 freq 20 Hz tsc: calibrating with acpihpet0: 1996264149 Hz The calibration code can be improved, and I have a patch waiting in the wings which does so, but you can't beat just *knowing* the frequency. ... I think we need to make the TSC "just work" in as many contexts as possible, especially on newer machines. > And it is the wrong time in the release cycle for this. This doesn't need to make release, I'm just gauging interest and testing code. > Boost could be disabled for the measurement if need by. > > AMD64 Architecture Programmer's Manual > Volume 2: System Programming > Publication No. 24593 > Revision 3.38 > > "17.2 Core Performance Boost > ... > CPB can be disabled using the CPBDis field of the Hardware Configuration > Register (HWCR MSR) on the appropriate core. When CPB is disabled, > hardware limits the frequency and voltage of the core to those defined > by P0. > > Support for core performance boost is indicated by > CPUID Fn8000_0007_EDX[CPB] = 1." > > "3.2.10 Hardware Configuration Register (HWCR) > ... > CpbDis. Bit 25. Core performance boost disable. When set to 1, core > performance boost is disabled. > " > > Processor Programming Reference (PPR) > for AMD Family 17h Model 01h, Revision B1 Processors > 54945 Rev 1.14 - April 15, 2017 > > "MSRC001_0015 [Hardware Configuration] (HWCR) > > 25 CpbDis: core performance boost disable. Read-write. > Reset: 0. 0=CPB is requested to be enabled. 1=CPB is disabled. > Specifies whether core performance boost is requested to be enabled or > disabled. If core performance boost is disabled while a core is in a > boosted P-state, the core automatically transitions to the highest > performance non-boosted P-state." > > [...] (Caveat: I might be wrong.) I believe this is only a toggle for whether the CPU can enter or remain in a boosted P-state. I do not think that toggling the feature on or off rewrites the P-state voltage/frequency MSRs on the fly. Toggling on or toggled off, we will still need a way to programmatically decide whether a given MSR describes a boosted P-state or P0. I have a line on a Sempron machine (family 10h) south of Austin, TX, $100. If it works when I pick it up I will probably have it set up to test within a few days.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
> And it is the wrong time in the release cycle for this. No kidding. As this makes absolutely no difference for any existing code in 7.2, except the strong hazard of accidentally breaking a machine.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
On Fri, Sep 23, 2022 at 09:16:25AM -0500, Scott Cheloha wrote:
> Hi,
>
> TL;DR:
>
> I want to compute the TSC frequency on AMD CPUs using the methods laid
> out in the AMD manuals instead of calibrating the TSC by hand.
>
> If you have an AMD CPU with an invariant TSC, please apply this patch,
> recompile/boot the resulting kernel, and send me the resulting dmesg.
>
> Family 10h-16h CPUs are especially interesting. If you've got one,
> don't be shy!
>
> Long explanation:
>
> On AMD CPUs we calibrate the TSC with a separate timer. This is slow
> and introduces error. I also worry about a future where legacy timers
> are absent or heavily gated (read: useless).
>
> This patch adds most of the code needed to compute the TSC frequency
> on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an
> invariant TSC so they are irrelevant.
>
> I have riddled the code with printf(9) calls so I can work out what's
> wrong by hand if a test result makes no sense.
>
> The only missing piece is code to read the configuration space on
> family 10h-16h CPUs to determine how many boosted P-states we need to
> skip to get to the MSR describing the software P0 state. I would
> really appreciate it if someone could explain how to do this at this
> very early point in boot. jsg@ pointed me to pci_conf_read(9), but
> I'm a little confused about how I get the needed pci* inputs at this
> point in boot.
I also said you shouldn't be looking at pci devices for this.
I remain unconvinced that all of this is worth it compared to
calibrating off a timer with a known rate. And it is the wrong time in
the release cycle for this.
Boost could be disabled for the measurement if need by.
AMD64 Architecture Programmer's Manual
Volume 2: System Programming
Publication No. 24593
Revision 3.38
"17.2 Core Performance Boost
...
CPB can be disabled using the CPBDis field of the Hardware Configuration
Register (HWCR MSR) on the appropriate core. When CPB is disabled,
hardware limits the frequency and voltage of the core to those defined
by P0.
Support for core performance boost is indicated by
CPUID Fn8000_0007_EDX[CPB] = 1."
"3.2.10 Hardware Configuration Register (HWCR)
...
CpbDis. Bit 25. Core performance boost disable. When set to 1, core performance
boost is disabled.
"
Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors
54945 Rev 1.14 - April 15, 2017
"MSRC001_0015 [Hardware Configuration] (HWCR)
25 CpbDis: core performance boost disable. Read-write.
Reset: 0. 0=CPB is requested to be enabled. 1=CPB is disabled.
Specifies whether core performance boost is requested to be enabled or
disabled. If core performance boost is disabled while a core is in a
boosted P-state, the core automatically transitions to the highest
performance non-boosted P-state."
also mentioned in
BIOS and Kernel Developer's Guide (BKDG)
For AMD Family 10h Processors
31116 Rev 3.48 - April 22, 2010
>
> --
>
> Test results? Clues on reading the configuration space?
>
> -Scott
>
> Index: tsc.c
> ===
> RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
> retrieving revision 1.29
> diff -u -p -r1.29 tsc.c
> --- tsc.c 22 Sep 2022 04:57:08 - 1.29
> +++ tsc.c 23 Sep 2022 14:04:22 -
> @@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci)
> return (0);
> }
>
> +uint64_t
> +tsc_freq_msr(struct cpu_info *ci)
> +{
> + uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier;
> + uint32_t msr, off = 0;
> +
> + if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
> + return 0;
> +
> + /*
> + * All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit.
> + * If TscFreqSel is not set the TSC does not advance at the P0
> + * frequency, in which case something is wrong and we need to
> + * calibrate by hand.
> + */
> +#define HWCR_TSCFREQSEL (1 << 24)
> + if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */
> + return 0;
> +#undef HWCR_TSCFREQSEL
> +
> + /*
> + * For families 10h, 12h, 14h, 15h, and 16h, we need to skip past
> + * the boosted P-states (Pb0, Pb1, etc.) to find the MSR describing
> + * P0, i.e. the highest performance unboosted P-state. The number
> + * of boosted states is kept in the "Core Performance Boost Control"
> + * configuration space register.
> + */
> +#ifdef __not_yet__
> + uint32_t reg;
> + switch (ci->ci_family) {
> + case 0x10:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(F4x15C);
> + off = (reg >> 2) & 0x1;
> + break;
> + case 0x12:
> + case 0x14:
> + case 0x15:
> + case 0x16:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(D18F4x15C);
> + off = (reg >> 2) &
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
On Fri, Sep 23, 2022 at 10:40:19PM +0300, Timo Myyr?? wrote: > Scott Cheloha [2022-09-23, 09:16 -0500]: > > > [...] > > > > Test results? Clues on reading the configuration space? > > > > [...] > > Hi, > > Here's a dmesg from thinkpad e485: Thanks for testing. > Does these timers affect the booting of kernel? Once I select the kernel > to boot by pressing enter on "bsd>" line, the boot process takes about > 18s to proceed from the "booting sr0a:/bsd". The patch reads a couple MSRs and prints ~10 additional lines during boot from the primary CPU. The computed TSC frequency is not used by the kernel, only printed so I can check whether my code is correct. It should have zero impact on the length of the boot. It should not change any runtime behavior whatsoever. Your boot probably should not be taking that long, but I can't imagine how my patch would cause such a dramatic change. If you reverse the patch, what happens? > OpenBSD 7.2 (GENERIC.MP) #20: Fri Sep 23 22:27:31 EEST 2022 > t...@asteroid.bittivirhe.fi:/usr/src/sys/arch/amd64/compile/GENERIC.MP > [...] > cpu0 at mainbus0: apid 0 (boot processor) > cpu0: MSR C001_0064: en 1 base 2 mul 100 div 10 freq 20 Hz > cpu0: MSR C001_0065: en 1 base 2 mul 102 div 12 freq 17 Hz > cpu0: MSR C001_0066: en 1 base 2 mul 96 div 12 freq 16 Hz > cpu0: MSR C001_0067: en 0 > cpu0: MSR C001_0068: en 0 > cpu0: MSR C001_0069: en 0 > cpu0: MSR C001_006A: en 0 > cpu0: MSR C001_006B: en 0 > cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.30 MHz, 17-11-00 > cpu0: > FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES > cpu0: 32KB 64b/line 8-way D-cache, 64KB 64b/line 4-way I-cache, 512KB > 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache > tsc: calibrating with acpihpet0: 1996264149 Hz Your family 17h CPU has a computed P0 frequency of 2000MHz. The calibrated TSC frequency is 1996264149 Hz. That seems right to me, thank you for testing.
Re: [please test] tsc: derive frequency on AMD CPUs from MSRs
Scott Cheloha [2022-09-23, 09:16 -0500]:
> Hi,
>
> TL;DR:
>
> I want to compute the TSC frequency on AMD CPUs using the methods laid
> out in the AMD manuals instead of calibrating the TSC by hand.
>
> If you have an AMD CPU with an invariant TSC, please apply this patch,
> recompile/boot the resulting kernel, and send me the resulting dmesg.
>
> Family 10h-16h CPUs are especially interesting. If you've got one,
> don't be shy!
>
> Long explanation:
>
> On AMD CPUs we calibrate the TSC with a separate timer. This is slow
> and introduces error. I also worry about a future where legacy timers
> are absent or heavily gated (read: useless).
>
> This patch adds most of the code needed to compute the TSC frequency
> on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an
> invariant TSC so they are irrelevant.
>
> I have riddled the code with printf(9) calls so I can work out what's
> wrong by hand if a test result makes no sense.
>
> The only missing piece is code to read the configuration space on
> family 10h-16h CPUs to determine how many boosted P-states we need to
> skip to get to the MSR describing the software P0 state. I would
> really appreciate it if someone could explain how to do this at this
> very early point in boot. jsg@ pointed me to pci_conf_read(9), but
> I'm a little confused about how I get the needed pci* inputs at this
> point in boot.
>
> --
>
> Test results? Clues on reading the configuration space?
>
> -Scott
>
> Index: tsc.c
> ===
> RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
> retrieving revision 1.29
> diff -u -p -r1.29 tsc.c
> --- tsc.c 22 Sep 2022 04:57:08 - 1.29
> +++ tsc.c 23 Sep 2022 14:04:22 -
> @@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci)
> return (0);
> }
>
> +uint64_t
> +tsc_freq_msr(struct cpu_info *ci)
> +{
> + uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier;
> + uint32_t msr, off = 0;
> +
> + if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
> + return 0;
> +
> + /*
> + * All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit.
> + * If TscFreqSel is not set the TSC does not advance at the P0
> + * frequency, in which case something is wrong and we need to
> + * calibrate by hand.
> + */
> +#define HWCR_TSCFREQSEL (1 << 24)
> + if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */
> + return 0;
> +#undef HWCR_TSCFREQSEL
> +
> + /*
> + * For families 10h, 12h, 14h, 15h, and 16h, we need to skip past
> + * the boosted P-states (Pb0, Pb1, etc.) to find the MSR describing
> + * P0, i.e. the highest performance unboosted P-state. The number
> + * of boosted states is kept in the "Core Performance Boost Control"
> + * configuration space register.
> + */
> +#ifdef __not_yet__
> + uint32_t reg;
> + switch (ci->ci_family) {
> + case 0x10:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(F4x15C);
> + off = (reg >> 2) & 0x1;
> + break;
> + case 0x12:
> + case 0x14:
> + case 0x15:
> + case 0x16:
> + /* XXX How do I read config space at this point in boot? */
> + reg = read_config_space(D18F4x15C);
> + off = (reg >> 2) & 0x7;
> + break;
> + default:
> + break;
> + }
> +#endif
> +
> +/* DEBUG Let's look at all the MSRs to check my math. */
> +for (; off < 8; off++) {
> +
> + /*
> + * In family 10h+, core P-state voltage/frequency definitions
> + * are kept in MSRs C001_006[4:B] (eight registers in total).
> + * All MSRs in the range are readable, but if the EN bit isn't
> + * set the register doesn't define a valid P-state.
> + */
> + msr = 0xc0010064 + off; /* XXX specialreg.h */
> + def = rdmsr(msr);
> + printf("%s: MSR %04X_%04X: en %d",
> + ci->ci_dev->dv_xname, msr >> 16, msr & 0x,
> + !!ISSET(def, 1ULL << 63));
> + if (!ISSET(def, 1ULL << 63)) { /* XXX specialreg.h */
> + printf("\n");
> + continue;
> + }
> + switch (ci->ci_family) {
> + case 0x10:
> + /* AMD Family 10h Processor BKDG, Rev 3.62, p. 429 */
> + base = 1; /* 100.0 MHz */
> + did = (def >> 6) & 0x7;
> + divisor = 1ULL << did;
> + fid = def & 0x1f;
> + multiplier = fid + 0x10;
> + printf(" base %llu did %llu div %llu fid %llu mul %llu",
> + base, did, divisor, fid, multiplier);
> + break;
> + case 0x11:
> + /* AMD Family 11h Processor BKDG, Rev 3.62, p. 236 */
> + base = 1; /* 100.0 MHz */
> + did = (def >> 6) & 0x7;
> + divisor = 1ULL << did;
> + fid = def
[please test] tsc: derive frequency on AMD CPUs from MSRs
Hi,
TL;DR:
I want to compute the TSC frequency on AMD CPUs using the methods laid
out in the AMD manuals instead of calibrating the TSC by hand.
If you have an AMD CPU with an invariant TSC, please apply this patch,
recompile/boot the resulting kernel, and send me the resulting dmesg.
Family 10h-16h CPUs are especially interesting. If you've got one,
don't be shy!
Long explanation:
On AMD CPUs we calibrate the TSC with a separate timer. This is slow
and introduces error. I also worry about a future where legacy timers
are absent or heavily gated (read: useless).
This patch adds most of the code needed to compute the TSC frequency
on AMD family 10h+ CPUs. CPUs prior to family 10h did not support an
invariant TSC so they are irrelevant.
I have riddled the code with printf(9) calls so I can work out what's
wrong by hand if a test result makes no sense.
The only missing piece is code to read the configuration space on
family 10h-16h CPUs to determine how many boosted P-states we need to
skip to get to the MSR describing the software P0 state. I would
really appreciate it if someone could explain how to do this at this
very early point in boot. jsg@ pointed me to pci_conf_read(9), but
I'm a little confused about how I get the needed pci* inputs at this
point in boot.
--
Test results? Clues on reading the configuration space?
-Scott
Index: tsc.c
===
RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
retrieving revision 1.29
diff -u -p -r1.29 tsc.c
--- tsc.c 22 Sep 2022 04:57:08 - 1.29
+++ tsc.c 23 Sep 2022 14:04:22 -
@@ -100,6 +100,253 @@ tsc_freq_cpuid(struct cpu_info *ci)
return (0);
}
+uint64_t
+tsc_freq_msr(struct cpu_info *ci)
+{
+ uint64_t base, def, did, did_lsd, did_msd, divisor, fid, multiplier;
+ uint32_t msr, off = 0;
+
+ if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
+ return 0;
+
+ /*
+* All family 10h+ CPUs have MSR_HWCR and the TscFreqSel bit.
+* If TscFreqSel is not set the TSC does not advance at the P0
+* frequency, in which case something is wrong and we need to
+* calibrate by hand.
+*/
+#define HWCR_TSCFREQSEL (1 << 24)
+ if (!ISSET(rdmsr(MSR_HWCR), HWCR_TSCFREQSEL)) /* XXX specialreg.h */
+ return 0;
+#undef HWCR_TSCFREQSEL
+
+ /*
+* For families 10h, 12h, 14h, 15h, and 16h, we need to skip past
+* the boosted P-states (Pb0, Pb1, etc.) to find the MSR describing
+* P0, i.e. the highest performance unboosted P-state. The number
+* of boosted states is kept in the "Core Performance Boost Control"
+* configuration space register.
+*/
+#ifdef __not_yet__
+ uint32_t reg;
+ switch (ci->ci_family) {
+ case 0x10:
+ /* XXX How do I read config space at this point in boot? */
+ reg = read_config_space(F4x15C);
+ off = (reg >> 2) & 0x1;
+ break;
+ case 0x12:
+ case 0x14:
+ case 0x15:
+ case 0x16:
+ /* XXX How do I read config space at this point in boot? */
+ reg = read_config_space(D18F4x15C);
+ off = (reg >> 2) & 0x7;
+ break;
+ default:
+ break;
+ }
+#endif
+
+/* DEBUG Let's look at all the MSRs to check my math. */
+for (; off < 8; off++) {
+
+ /*
+* In family 10h+, core P-state voltage/frequency definitions
+* are kept in MSRs C001_006[4:B] (eight registers in total).
+* All MSRs in the range are readable, but if the EN bit isn't
+* set the register doesn't define a valid P-state.
+*/
+ msr = 0xc0010064 + off; /* XXX specialreg.h */
+ def = rdmsr(msr);
+ printf("%s: MSR %04X_%04X: en %d",
+ ci->ci_dev->dv_xname, msr >> 16, msr & 0x,
+ !!ISSET(def, 1ULL << 63));
+ if (!ISSET(def, 1ULL << 63)) { /* XXX specialreg.h */
+ printf("\n");
+ continue;
+ }
+ switch (ci->ci_family) {
+ case 0x10:
+ /* AMD Family 10h Processor BKDG, Rev 3.62, p. 429 */
+ base = 1; /* 100.0 MHz */
+ did = (def >> 6) & 0x7;
+ divisor = 1ULL << did;
+ fid = def & 0x1f;
+ multiplier = fid + 0x10;
+ printf(" base %llu did %llu div %llu fid %llu mul %llu",
+ base, did, divisor, fid, multiplier);
+ break;
+ case 0x11:
+ /* AMD Family 11h Processor BKDG, Rev 3.62, p. 236 */
+ base = 1; /* 100.0 MHz */
+ did = (def >> 6) & 0x7;
+ divisor = 1ULL << did;
+ fid = def & 0x1f;
+ multiplier = fid + 0x8;
+ printf(" base %llu did %llu div %llu fid %llu mul %llu",
+ base, did,
