Anyone?
On Wed, Apr 22, 2020 at 07:28:02PM +0200, Stefan Sperling wrote:
> We currently configure interrupt mitigation for Rx, but not for Tx.
>
> And there is also a global Tx/Rx interrupt limit which can be configured
> via the MIRT register. Setting this could prevent Tx/Rx interrupt storms.
>
> This change doesn't really buy us anything during regular use of the
> device, but during my testing it didn't hurt either.
>
> OK?
>
> diff 9b00dd5006bdfc0cf9d71dac4defe47f2ccfda0d
> c50b0f0215d7dd5773e0ee8623d8aa2c7d2107c6
> blob - 88784561c133b42b2b23dff2cea0075cf2ffdd27
> blob + b3532eb8263f678c80a44257fe4f55820458a18c
> --- sys/dev/ic/athn.c
> +++ sys/dev/ic/athn.c
> @@ -2428,6 +2428,12 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_
> /* Setup Rx interrupt mitigation. */
> AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
>
> + /* Setup Tx interrupt mitigation. */
> + AR_WRITE(sc, AR_TIMT, SM(AR_TIMT_FIRST, 2000) | SM(AR_TIMT_LAST, 500));
> +
> + /* Set maximum interrupt rate threshold (in micro seconds). */
> + AR_WRITE(sc, AR_MIRT, SM(AR_MIRT_RATE_THRES, 2000));
> +
> ops->init_baseband(sc);
>
> if ((error = athn_init_calib(sc, c, extc)) != 0) {
> blob - 92b937ce3b3a0977a0f8548051863c39656a4862
> blob + e14c096b90b5350712548d245a9bfd919b66f23b
> --- sys/dev/ic/athnreg.h
> +++ sys/dev/ic/athnreg.h
> @@ -280,6 +280,10 @@
> /* Bits for AR_IER. */
> #define AR_IER_ENABLE0x0001
>
> +/* Bits for AR_MIRT. */
> +#define AR_MIRT_RATE_THRES_M 0x
> +#define AR_MIRT_RATE_THRES_S 0
> +
> /* Bits for AR_TIMT. */
> #define AR_TIMT_LAST_M 0x
> #define AR_TIMT_LAST_S 0
>
>
