On 18/02/20(Tue) 22:39, Jonathan Matthew wrote:
> On Fri, Feb 14, 2020 at 06:28:20PM +0100, Martin Pieuchot wrote:
> > @@ -2597,13 +2635,6 @@ em_initialize_receive_unit(struct em_sof
> > E1000_WRITE_REG(>hw, ITR, DEFAULT_ITR);
> > }
> >
> > - /* Setup the Base and Length of the
On Fri, Feb 14, 2020 at 06:28:20PM +0100, Martin Pieuchot wrote:
> This diff introduces the concept of "queue" in the em(4) driver. The
> logic present in ix(4) has been matched for coherency.
>
> Currently the driver uses a single queue and the diff below doesn't
> change anything in that
On 14.2.2020. 18:28, Martin Pieuchot wrote:
> I'm running this on:
>
> em0 at pci1 dev 0 function 0 "Intel I210" rev 0x03: msi
> em0 at pci0 dev 20 function 0 "Intel I354 SGMII" rev 0x03: msi
>
> More tests are always welcome ;)
em0 at pci0 dev 25 function 0 "Intel 82579LM" rev
This diff introduces the concept of "queue" in the em(4) driver. The
logic present in ix(4) has been matched for coherency.
Currently the driver uses a single queue and the diff below doesn't
change anything in that regard. It can be viewed as the introduction
of an abstraction.
I'd like to
