Re: inteldrm: setup backlight pwm alternate increment on backlight enable

2017-02-20 Thread joshua stein 
On Fri, 10 Feb 2017 at 10:46:08 +0100, Peter Hessler wrote:
> On 2017 Feb 10 (Fri) at 11:52:20 +1100 (+1100), Jonathan Gray wrote:
> :On Thu, Feb 09, 2017 at 06:39:13PM -0600, joshua stein wrote:
> :> I have no idea why there are chickens involved, but this fixes the
> :> problem on at least the MacBookAir7,1 (Broadwell) where upon S3
> :> resume, the backlight value is treated as 0 or 100 despite reporting
> :> intermediate values, so if the backlight value was anything other
> :> than 100 at suspend time, the screen will stay off upon resume.
> :
> :Chicken bits are overrides for functions like clock gating, if it turns
> :out there is a hardware bug in a particular feature these bits are used
> :to disable them.
> :
> :This diff seems reasonable but it would be nice to get some tests
> :on non-apple broadwell hardware.
> :
> 
> Tested on a broadwell Thinkpad x250, seems fine.  Changed the brightness
> to 40%, then did a few suspend-resumes.

Anyone else have any reports testing this diff?

Re: inteldrm: setup backlight pwm alternate increment on backlight enable

2017-02-10 Thread Peter Hessler 
On 2017 Feb 10 (Fri) at 11:52:20 +1100 (+1100), Jonathan Gray wrote:
:On Thu, Feb 09, 2017 at 06:39:13PM -0600, joshua stein wrote:
:> I have no idea why there are chickens involved, but this fixes the
:> problem on at least the MacBookAir7,1 (Broadwell) where upon S3
:> resume, the backlight value is treated as 0 or 100 despite reporting
:> intermediate values, so if the backlight value was anything other
:> than 100 at suspend time, the screen will stay off upon resume.
:
:Chicken bits are overrides for functions like clock gating, if it turns
:out there is a hardware bug in a particular feature these bits are used
:to disable them.
:
:This diff seems reasonable but it would be nice to get some tests
:on non-apple broadwell hardware.
:

Tested on a broadwell Thinkpad x250, seems fine.  Changed the brightness
to 40%, then did a few suspend-resumes.

dmesg:

OpenBSD 6.0-current (GENERIC.MP) #21: Fri Feb 10 10:39:29 CET 2017
phess...@dante.txl.hsgate.de:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 8277168128 (7893MB)
avail mem = 8021643264 (7650MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.7 @ 0xccbfd000 (64 entries)
bios0: vendor LENOVO version "N10ET28W (1.05 )" date 01/23/2015
bios0: LENOVO 20CM001UGE
acpi0 at bios0: rev 2
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP SLIC ASF! HPET ECDT APIC MCFG SSDT SSDT SSDT SSDT SSDT 
SSDT SSDT SSDT SSDT PCCT SSDT TCPA SSDT UEFI MSDM BATB FPDT UEFI DMAR
acpi0: wakeup devices LID_(S4) SLPB(S3) IGBE(S4) EXP2(S4) XHCI(S3) EHC1(S3)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 14318179 Hz
acpiec0 at acpi0
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM) i7-5600U CPU @ 2.60GHz, 2594.33 MHz
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,RDSEED,ADX,SMAP,PT,SENSOR,ARAT
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: TSC frequency 2594330400 Hz
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 99MHz
cpu0: mwait min=64, max=64, C-substates=0.2.1.2.4.1.1.1, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: Intel(R) Core(TM) i7-5600U CPU @ 2.60GHz, 2593.99 MHz
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,RDSEED,ADX,SMAP,PT,SENSOR,ARAT
cpu1: 256KB 64b/line 8-way L2 cache
cpu1: smt 1, core 0, package 0
cpu2 at mainbus0: apid 2 (application processor)
cpu2: Intel(R) Core(TM) i7-5600U CPU @ 2.60GHz, 2593.99 MHz
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,RDSEED,ADX,SMAP,PT,SENSOR,ARAT
cpu2: 256KB 64b/line 8-way L2 cache
cpu2: smt 0, core 1, package 0
cpu3 at mainbus0: apid 3 (application processor)
cpu3: Intel(R) Core(TM) i7-5600U CPU @ 2.60GHz, 2593.99 MHz
cpu3: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,RDSEED,ADX,SMAP,PT,SENSOR,ARAT
cpu3: 256KB 64b/line 8-way L2 cache
cpu3: smt 1, core 1, package 0
ioapic0 at mainbus0: apid 2 pa 0xfec0, version 20, 40 pins
acpimcfg0 at acpi0 addr 0xf800, bus 0-63
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (PEG_)
acpiprt2 at acpi0: bus 2 (EXP1)
acpiprt3 at acpi0: bus 3 (EXP2)
acpiprt4 at acpi0: bus -1 (EXP3)
acpicpu0 at acpi0: C3(200@233 mwait.1@0x40), C2(200@148 mwait.1@0x33), 
C1(1000@1 mwait.1), PSS
acpicpu1 at acpi0: C3(200@233 mwait.1@0x40), C2(200@148 mwait.1@0x33), 
C1(1000@1 mwait.1), PSS
acpicpu2 at acpi0: C3(200@233 mwait.1@0x40), C2(200@148 mwait.1@0x33), 
C1(1000@1 mwait.1), PSS
acpicpu3 at acpi0: C3(200@233 mwait.1@0x40), C2(200@148 mwait.1@0x33), 
C1(1000@1 mwait.1), PSS
acpipwrres0 at acpi0: PUBS, resource for XHCI, EHC1
acpipwrres1 at acpi0: NVP3, resource for PEG_
acpipwrres2 at acpi0: NVP2,

Re: inteldrm: setup backlight pwm alternate increment on backlight enable

2017-02-09 Thread Jonathan Gray 
On Thu, Feb 09, 2017 at 06:39:13PM -0600, joshua stein wrote:
> I have no idea why there are chickens involved, but this fixes the
> problem on at least the MacBookAir7,1 (Broadwell) where upon S3
> resume, the backlight value is treated as 0 or 100 despite reporting
> intermediate values, so if the backlight value was anything other
> than 100 at suspend time, the screen will stay off upon resume.

Chicken bits are overrides for functions like clock gating, if it turns
out there is a hardware bug in a particular feature these bits are used
to disable them.

This diff seems reasonable but it would be nice to get some tests
on non-apple broadwell hardware.

> 
> This is backported from Linux commits
> 32b421e79e6b546da1d469f1229403ac9142d695 and
> e29aff05f239f8dd24e9ee7816fd96726e20105a which were noted in
> freedesktop.org bug 67454.
> 
> This and the previous ACPI diff get suspend and resume working on
> the MacBook Air.
> 
> 
> Index: sys/dev/pci/drm/i915/i915_reg.h
> ===
> RCS file: /cvs/src/sys/dev/pci/drm/i915/i915_reg.h,v
> retrieving revision 1.11
> diff -u -p -u -p -r1.11 i915_reg.h
> --- sys/dev/pci/drm/i915/i915_reg.h   25 Sep 2015 16:15:19 -  1.11
> +++ sys/dev/pci/drm/i915/i915_reg.h   10 Feb 2017 00:39:02 -
> @@ -4540,9 +4540,11 @@
>  #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 
> 2)))
>  #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 
> 2)))
>  #define  FDI_BC_BIFURCATION_SELECT   (1 << 12)
> +#define  SPT_PWM_GRANULARITY (1<<0)
>  #define SOUTH_CHICKEN2   0xc2004
>  #define  FDI_MPHY_IOSFSB_RESET_STATUS(1<<13)
>  #define  FDI_MPHY_IOSFSB_RESET_CTL   (1<<12)
> +#define  LPT_PWM_GRANULARITY (1<<5)
>  #define  DPLS_EDP_PPS_FIX_DIS(1<<0)
>  
>  #define _FDI_RXA_CHICKEN 0xc200c
> Index: sys/dev/pci/drm/i915/intel_drv.h
> ===
> RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_drv.h,v
> retrieving revision 1.9
> diff -u -p -u -p -r1.9 intel_drv.h
> --- sys/dev/pci/drm/i915/intel_drv.h  9 Dec 2015 05:17:44 -   1.9
> +++ sys/dev/pci/drm/i915/intel_drv.h  10 Feb 2017 00:39:02 -
> @@ -168,6 +168,7 @@ struct intel_panel {
>   bool enabled;
>   bool combination_mode;  /* gen 2/4 only */
>   bool active_low_pwm;
> + bool alternate_pwm_increment;   /* lpt+ */
>   struct backlight_device *device;
>   } backlight;
>  };
> Index: sys/dev/pci/drm/i915/intel_panel.c
> ===
> RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_panel.c,v
> retrieving revision 1.11
> diff -u -p -u -p -r1.11 intel_panel.c
> --- sys/dev/pci/drm/i915/intel_panel.c23 Sep 2015 23:12:12 -  
> 1.11
> +++ sys/dev/pci/drm/i915/intel_panel.c10 Feb 2017 00:39:02 -
> @@ -611,7 +611,7 @@ static void bdw_enable_backlight(struct 
>   struct drm_device *dev = connector->base.dev;
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_panel *panel = >panel;
> - u32 pch_ctl1, pch_ctl2;
> + u32 pch_ctl1, pch_ctl2, schicken;
>  
>   pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
>   if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
> @@ -620,6 +620,22 @@ static void bdw_enable_backlight(struct 
>   I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
>   }
>  
> + if (HAS_PCH_LPT(dev)) {
> + schicken = I915_READ(SOUTH_CHICKEN2);
> + if (panel->backlight.alternate_pwm_increment)
> + schicken |= LPT_PWM_GRANULARITY;
> + else
> + schicken &= ~LPT_PWM_GRANULARITY;
> + I915_WRITE(SOUTH_CHICKEN2, schicken);
> + } else {
> + schicken = I915_READ(SOUTH_CHICKEN1);
> + if (panel->backlight.alternate_pwm_increment)
> + schicken |= SPT_PWM_GRANULARITY;
> + else
> + schicken &= ~SPT_PWM_GRANULARITY;
> + I915_WRITE(SOUTH_CHICKEN1, schicken);
> + }
> +
>   pch_ctl2 = panel->backlight.max << 16;
>   I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
>  
> @@ -956,6 +972,13 @@ static int bdw_setup_backlight(struct in
>   struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_panel *panel = >panel;
>   u32 pch_ctl1, pch_ctl2, val;
> + bool alt;
> +
> + if (HAS_PCH_LPT(dev))
> + alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
> + else
> + alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
> + panel->backlight.alternate_pwm_increment = alt;
>  
>   pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
>   panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
>

inteldrm: setup backlight pwm alternate increment on backlight enable

2017-02-09 Thread joshua stein 
I have no idea why there are chickens involved, but this fixes the
problem on at least the MacBookAir7,1 (Broadwell) where upon S3
resume, the backlight value is treated as 0 or 100 despite reporting
intermediate values, so if the backlight value was anything other
than 100 at suspend time, the screen will stay off upon resume.

This is backported from Linux commits
32b421e79e6b546da1d469f1229403ac9142d695 and
e29aff05f239f8dd24e9ee7816fd96726e20105a which were noted in
freedesktop.org bug 67454.

This and the previous ACPI diff get suspend and resume working on
the MacBook Air.


Index: sys/dev/pci/drm/i915/i915_reg.h
===
RCS file: /cvs/src/sys/dev/pci/drm/i915/i915_reg.h,v
retrieving revision 1.11
diff -u -p -u -p -r1.11 i915_reg.h
--- sys/dev/pci/drm/i915/i915_reg.h 25 Sep 2015 16:15:19 -  1.11
+++ sys/dev/pci/drm/i915/i915_reg.h 10 Feb 2017 00:39:02 -
@@ -4540,9 +4540,11 @@
 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 
2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define  SPT_PWM_GRANULARITY   (1<<0)
 #define SOUTH_CHICKEN2 0xc2004
 #define  FDI_MPHY_IOSFSB_RESET_STATUS  (1<<13)
 #define  FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
+#define  LPT_PWM_GRANULARITY   (1<<5)
 #define  DPLS_EDP_PPS_FIX_DIS  (1<<0)
 
 #define _FDI_RXA_CHICKEN 0xc200c
Index: sys/dev/pci/drm/i915/intel_drv.h
===
RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_drv.h,v
retrieving revision 1.9
diff -u -p -u -p -r1.9 intel_drv.h
--- sys/dev/pci/drm/i915/intel_drv.h9 Dec 2015 05:17:44 -   1.9
+++ sys/dev/pci/drm/i915/intel_drv.h10 Feb 2017 00:39:02 -
@@ -168,6 +168,7 @@ struct intel_panel {
bool enabled;
bool combination_mode;  /* gen 2/4 only */
bool active_low_pwm;
+   bool alternate_pwm_increment;   /* lpt+ */
struct backlight_device *device;
} backlight;
 };
Index: sys/dev/pci/drm/i915/intel_panel.c
===
RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_panel.c,v
retrieving revision 1.11
diff -u -p -u -p -r1.11 intel_panel.c
--- sys/dev/pci/drm/i915/intel_panel.c  23 Sep 2015 23:12:12 -  1.11
+++ sys/dev/pci/drm/i915/intel_panel.c  10 Feb 2017 00:39:02 -
@@ -611,7 +611,7 @@ static void bdw_enable_backlight(struct 
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_panel *panel = >panel;
-   u32 pch_ctl1, pch_ctl2;
+   u32 pch_ctl1, pch_ctl2, schicken;
 
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
@@ -620,6 +620,22 @@ static void bdw_enable_backlight(struct 
I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
}
 
+   if (HAS_PCH_LPT(dev)) {
+   schicken = I915_READ(SOUTH_CHICKEN2);
+   if (panel->backlight.alternate_pwm_increment)
+   schicken |= LPT_PWM_GRANULARITY;
+   else
+   schicken &= ~LPT_PWM_GRANULARITY;
+   I915_WRITE(SOUTH_CHICKEN2, schicken);
+   } else {
+   schicken = I915_READ(SOUTH_CHICKEN1);
+   if (panel->backlight.alternate_pwm_increment)
+   schicken |= SPT_PWM_GRANULARITY;
+   else
+   schicken &= ~SPT_PWM_GRANULARITY;
+   I915_WRITE(SOUTH_CHICKEN1, schicken);
+   }
+
pch_ctl2 = panel->backlight.max << 16;
I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
 
@@ -956,6 +972,13 @@ static int bdw_setup_backlight(struct in
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_panel *panel = >panel;
u32 pch_ctl1, pch_ctl2, val;
+   bool alt;
+
+   if (HAS_PCH_LPT(dev))
+   alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
+   else
+   alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
+   panel->backlight.alternate_pwm_increment = alt;
 
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;