Re: landisk: invalidate the entire cache on EMODE CPUs

[Tobias Ulmer]

On Fri, Mar 04, 2016 at 10:32:01PM +, Miod Vallat wrote:
> 
> > SH4 CPUs with EMODE bit set have a cache twice as big.  Fix the obvious
> > copy&paste mistake.
> 
> There is nothing to fix in these routines.
> 
> When EMODE is enabled, the cache becomes two way, instead of one way,
> which is why it becomes twice as big.
> 
> sh4_emode_icache_sync_all() and sh4_emode_dcache_wbinv_all() wrap
> cache_sh4_emode_op_8lines_32(), which will operate on both ways.
> 

Ouch, that's a pretty mean trap :/ Sorry for the noise

Re: landisk: invalidate the entire cache on EMODE CPUs

[Miod Vallat]

> SH4 CPUs with EMODE bit set have a cache twice as big.  Fix the obvious
> copy&paste mistake.

There is nothing to fix in these routines.

When EMODE is enabled, the cache becomes two way, instead of one way,
which is why it becomes twice as big.

sh4_emode_icache_sync_all() and sh4_emode_dcache_wbinv_all() wrap
cache_sh4_emode_op_8lines_32(), which will operate on both ways.

landisk: invalidate the entire cache on EMODE CPUs

[Tobias Ulmer]

SH4 CPUs with EMODE bit set have a cache twice as big.  Fix the obvious
copy&paste mistake.

Didn't fix the problem I was looking at, but may help with general
stability (I think all landisks use the EMODE capable SH7751R)
My "good" landisk is happy with this.

diff --git a/sys/arch/sh/sh/cache_sh4.c b/sys/arch/sh/sh/cache_sh4.c
index 8c736a1..ea70312 100644
--- a/sys/arch/sh/sh/cache_sh4.c
+++ b/sys/arch/sh/sh/cache_sh4.c
@@ -403,7 +403,7 @@ void
 sh4_emode_icache_sync_all(void)
 {
vaddr_t va = 0;
-   vaddr_t eva = SH4_ICACHE_SIZE;
+   vaddr_t eva = SH4_EMODE_ICACHE_SIZE;
 
sh4_emode_dcache_wbinv_all();
 
@@ -443,7 +443,7 @@ void
 sh4_emode_dcache_wbinv_all(void)
 {
vaddr_t va = 0;
-   vaddr_t eva = SH4_DCACHE_SIZE;
+   vaddr_t eva = SH4_EMODE_DCACHE_SIZE;
 
while (va < eva) {
cache_sh4_emode_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,