Re: riscv64: trigger deferred timer interrupts from splx(9)

On Fri, Aug 05, 2022 at 12:34:59AM +0200, Jeremie Courreges-Anglas wrote: > >> [...] > >> > >> You're adding the timer reset to plic_setipl() but the latter is called > >> after softintr processing in plic_splx(). > >> > >>/* Pending software intr is handled here */ > >>if

Re: riscv64: trigger deferred timer interrupts from splx(9)

On Thu, Aug 04 2022, Scott Cheloha wrote: > On Thu, Aug 04, 2022 at 09:39:13AM +0200, Jeremie Courreges-Anglas wrote: >> On Mon, Aug 01 2022, Scott Cheloha wrote: >> > On Mon, Aug 01, 2022 at 07:15:33PM +0200, Jeremie Courreges-Anglas wrote: >> >> On Sun, Jul 31 2022, Scott Cheloha wrote: >> >>

Re: riscv64: trigger deferred timer interrupts from splx(9)

> Date: Thu, 4 Aug 2022 10:36:22 -0500 > From: Scott Cheloha > > On Thu, Aug 04, 2022 at 09:39:13AM +0200, Jeremie Courreges-Anglas wrote: > > On Mon, Aug 01 2022, Scott Cheloha wrote: > > > On Mon, Aug 01, 2022 at 07:15:33PM +0200, Jeremie Courreges-Anglas wrote: > > >> On Sun, Jul 31 2022,

Re: riscv64: trigger deferred timer interrupts from splx(9)

On Thu, Aug 04, 2022 at 09:39:13AM +0200, Jeremie Courreges-Anglas wrote: > On Mon, Aug 01 2022, Scott Cheloha wrote: > > On Mon, Aug 01, 2022 at 07:15:33PM +0200, Jeremie Courreges-Anglas wrote: > >> On Sun, Jul 31 2022, Scott Cheloha wrote: > >> > Hi, > >> > > >> > I am unsure how to properly

Re: riscv64: trigger deferred timer interrupts from splx(9)

On Mon, Aug 01 2022, Scott Cheloha wrote: > On Mon, Aug 01, 2022 at 07:15:33PM +0200, Jeremie Courreges-Anglas wrote: >> On Sun, Jul 31 2022, Scott Cheloha wrote: >> > Hi, >> > >> > I am unsure how to properly mask RISC-V timer interrupts in hardware >> > at or above IPL_CLOCK. I think that

Re: riscv64: trigger deferred timer interrupts from splx(9)

On Mon, Aug 01, 2022 at 07:15:33PM +0200, Jeremie Courreges-Anglas wrote: > On Sun, Jul 31 2022, Scott Cheloha wrote: > > Hi, > > > > I am unsure how to properly mask RISC-V timer interrupts in hardware > > at or above IPL_CLOCK. I think that would be cleaner than doing > > another timer

Re: riscv64: trigger deferred timer interrupts from splx(9)

On Sun, Jul 31 2022, Scott Cheloha wrote: > Hi, > > I am unsure how to properly mask RISC-V timer interrupts in hardware > at or above IPL_CLOCK. I think that would be cleaner than doing > another timer interrupt deferral thing. > > But, just to get the ball rolling, here a first attempt at the

riscv64: trigger deferred timer interrupts from splx(9)

Hi, I am unsure how to properly mask RISC-V timer interrupts in hardware at or above IPL_CLOCK. I think that would be cleaner than doing another timer interrupt deferral thing. But, just to get the ball rolling, here a first attempt at the timer interrupt deferral thing for riscv64. The