Here is a diff to add flow control support to vge(4).

Tested with..
vge0 at pci2 dev 4 function 0 "VIA VT612x" rev 0x11
ciphy0 at vge0 phy 1: CS8201 10/100/1000TX PHY, rev. 1

OK?


Index: if_vge.c
===================================================================
RCS file: /home/cvs/src/sys/dev/pci/if_vge.c,v
retrieving revision 1.51
diff -u -p -r1.51 if_vge.c
--- if_vge.c    22 Jun 2011 16:44:27 -0000      1.51
+++ if_vge.c    22 Oct 2012 08:22:55 -0000
@@ -812,7 +812,7 @@ vge_attach(struct device *parent, struct
        ifmedia_init(&sc->sc_mii.mii_media, 0,
            vge_ifmedia_upd, vge_ifmedia_sts);
        mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
-           MII_OFFSET_ANY, 0);
+           MII_OFFSET_ANY, MIIF_DOPAUSE);
        if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
                printf("%s: no PHY found!\n", sc->vge_dev.dv_xname);
                ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL,
@@ -1630,9 +1630,16 @@ vge_init(struct ifnet *ifp)
        /* Init the multicast filter. */
        vge_setmulti(sc);
 
-       /* Enable flow control */
-
-       CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
+       /* Initialize pause timer. */
+       CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
+       /*
+        * Initialize flow control parameters.
+        *  TX XON high threshold : 48
+        *  TX pause low threshold : 24
+        *  Disable half-duplex flow control
+        */
+       CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
+       CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
 
        /* Enable jumbo frame reception (if desired) */
 
@@ -1768,6 +1775,16 @@ vge_miibus_statchg(struct device *dev)
                    sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media));
                break;
        }
+
+       /*
+        * 802.3x flow control
+       */
+       CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
+           VGE_CR2_FDX_RXFLOWCTL_ENABLE);
+       if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
+               CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE);
+       if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
+               CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE);
 }
 
 int

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