While I was researching the FMC thing the other day, I came a couple
posts from Pavel that I'd forgotten about.
https://lists.cryptech.is/archives/tech/2015-October/002293.html
On Tue Oct 20 17:47:48 UTC 2015, Pavel Shatov wrote:
>> In the long term, I *really* want to get rid of this double
On Wed, 23 May 2018 01:34:28 -0400, Joachim Strömbergson wrote:
>
> Just to get some clarifications - what was the number of 2048 sigs/s
> before the AES updates?
Don't remember (might be in old email), but I saved the bitstream, so
we can find out what current firmware does with the older
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Aloha!
Rob Austein wrote:
>> After this the big thing I can do is the streaming interface I've
>> been talking about.
> ...
>
> Sounds cool, but not sure it helps for specific case of AES keywrap.
> You might want to look at
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Aloha!
Rob Austein wrote:
> On Wed, 23 May 2018 01:34:28 -0400, Joachim Strömbergson wrote:
>> Since you are running w parallel AES cores that way of improving
>> things is already used. The next thing should be double sys_clk to
>> 100 MHz. That
Where would I confirm the clock speed after editing these lines? I did a
grep for frequency on the build dir and came up with two files using
.CLK_OUT_MUL (20.0), // 2..64
.CLK_OUT_DIV (10.0) // 1..128
alpha_fmc_err.twr and
alpha_fmc.srp
"grep -r frequency
alpha_fmc_err.twr:
I'm not the verilog expert, but would you also need to change
alpha_fmc.ucf to match?
paul
On 05/23/2018 12:37 PM, Joachim Strömbergson wrote:
> Aloha!
>
> Rob Austein wrote:
>> On Wed, 23 May 2018 01:34:28 -0400, Joachim Strömbergson wrote:
>>> Since you are
