Re: CPUID: Check for PTM and HWP features
Thanks for noticing this!
Here's an updated diff. I also included Hardware Duty Cycling (HDC) tests.
Index: arch/amd64/include/specialreg.h
===
RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v
retrieving revision 1.48
diff -u -p -u -p -r1.48 specialreg.h
--- arch/amd64/include/specialreg.h 10 Sep 2016 17:15:44 - 1.48
+++ arch/amd64/include/specialreg.h 15 Sep 2016 12:05:46 -
@@ -220,6 +220,9 @@
*/
#defineTPM_SENSOR 0x0001 /* Digital temp sensor */
#defineTPM_ARAT0x0004 /* APIC Timer Always Running */
+#defineTPM_PTM 0x0040 /* Package Thermal Management
*/
+#defineTPM_HWP 0x0080 /* Hardware P-states */
+#defineTPM_HDC 0x2000 /* Hardware Duty Cycling */
/*
* "Architectural Performance Monitoring" bits (CPUID function 0x0a):
@@ -414,6 +417,16 @@
#define MSR_MC3_STATUS 0x411
#define MSR_MC3_ADDR 0x412
#define MSR_MC3_MISC 0x413
+
+/* Hardware P state interface */
+#define MSR_PPERF 0x64e
+#define MSR_PERF_LIMIT_REASONS 0x64f
+#define MSR_PM_ENABLE 0x770
+#define MSR_HWP_CAPABILITIES 0x771
+#define MSR_HWP_REQUEST_PKG0x772
+#define MSR_HWP_INTERRUPT 0x773
+#define MSR_HWP_REQUEST0x774
+#define MSR_HWP_STATUS 0x777
/* VIA MSR */
#define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */
Index: arch/i386/include/specialreg.h
===
RCS file: /cvs/src/sys/arch/i386/include/specialreg.h,v
retrieving revision 1.57
diff -u -p -u -p -r1.57 specialreg.h
--- arch/i386/include/specialreg.h 3 Sep 2016 13:35:03 - 1.57
+++ arch/i386/include/specialreg.h 15 Sep 2016 12:05:47 -
@@ -205,6 +205,9 @@
*/
#defineTPM_SENSOR 0x0001 /* Digital temp sensor */
#defineTPM_ARAT0x0004 /* APIC Timer Always Running */
+#defineTPM_PTM 0x0040 /* Package Thermal Management
*/
+#defineTPM_HWP 0x0080 /* Hardware P-states */
+#defineTPM_HDC 0x2000 /* Hardware Duty Cycling */
/*
* "Architectural Performance Monitoring" bits (CPUID function 0x0a):
@@ -396,6 +399,16 @@
#define MSR_MC3_STATUS 0x411
#define MSR_MC3_ADDR 0x412
#define MSR_MC3_MISC 0x413
+
+/* Hardware P state interface */
+#define MSR_PPERF 0x64e
+#define MSR_PERF_LIMIT_REASONS 0x64f
+#define MSR_PM_ENABLE 0x770
+#define MSR_HWP_CAPABILITIES 0x771
+#define MSR_HWP_REQUEST_PKG0x772
+#define MSR_HWP_INTERRUPT 0x773
+#define MSR_HWP_REQUEST0x774
+#define MSR_HWP_STATUS 0x777
/* VIA MSRs */
#define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */
Index: arch/amd64/amd64/identcpu.c
===
RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v
retrieving revision 1.74
diff -u -p -u -p -r1.74 identcpu.c
--- arch/amd64/amd64/identcpu.c 3 Sep 2016 12:12:43 - 1.74
+++ arch/amd64/amd64/identcpu.c 15 Sep 2016 12:05:47 -
@@ -199,6 +199,9 @@ const struct {
}, cpu_tpm_eaxfeatures[] = {
{ TPM_SENSOR, "SENSOR" },
{ TPM_ARAT, "ARAT" },
+ { TPM_PTM, "PTM" },
+ { TPM_HWP, "HWP" },
+ { TPM_HDC, "HDC" },
}, cpu_cpuid_perf_eax[] = {
{ CPUIDEAX_VERID, "PERF" },
}, cpu_cpuid_apmi_edx[] = {
Index: arch/i386/i386/machdep.c
===
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.589
diff -u -p -u -p -r1.589 machdep.c
--- arch/i386/i386/machdep.c3 Sep 2016 12:12:43 - 1.589
+++ arch/i386/i386/machdep.c15 Sep 2016 12:05:47 -
@@ -1089,6 +1089,9 @@ const struct cpu_cpuid_feature cpu_seff0
const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = {
{ TPM_SENSOR, "SENSOR" },
{ TPM_ARAT, "ARAT" },
+ { TPM_PTM, "PTM" },
+ { TPM_HWP, "HWP" },
+ { TPM_HDC, "HDC" },
};
const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = {
Re: CPUID: Check for PTM and HWP features
On Thu, Sep 15, 2016 at 01:42:33PM +0300, Paul Irofti wrote:
> Hi,
>
> The following diff adds checks for Package Thermal Management and
> Hardware P-states in the Thermal and Power Management CPUID Leaf.
>
> I also added the the Hardware P-States MSRs for a Skylake firmware fix
> that I will send later toady. I don't mind if that should go in a separate
> commit.
>
> Tested only on amd64, i386 tests welcomed! Ok?
>
>
> Index: arch/amd64/include/specialreg.h
> ===
> RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v
> retrieving revision 1.48
> diff -u -p -u -p -r1.48 specialreg.h
> --- arch/amd64/include/specialreg.h 10 Sep 2016 17:15:44 - 1.48
> +++ arch/amd64/include/specialreg.h 15 Sep 2016 10:36:48 -
> @@ -220,6 +220,8 @@
> */
> #define TPM_SENSOR 0x0001 /* Digital temp sensor */
> #define TPM_ARAT0x0004 /* APIC Timer Always Running */
> +#define TPM_PTM 0x0006 /* Package Thermal Management
> */
> +#define TPM_HWP 0x0007 /* Hardware P-states */
Those are not single bits.
The Thermal and Power Management Leaf has eax documented as:
Bit 00: Digital temperature sensor is supported if set.
Bit 01: Intel Turbo Boost Technology Available (see description of
IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,
IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is
supported if set.
Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
IA32_THREAD_STALL MSRs are
supported if set.
Bits 31 - 15: Reserved.
So they should be (1 << 6) 0x40, and (1 << 7) 0x80 instead.
>
> /*
>* "Architectural Performance Monitoring" bits (CPUID function 0x0a):
> @@ -414,6 +416,16 @@
> #define MSR_MC3_STATUS 0x411
> #define MSR_MC3_ADDR 0x412
> #define MSR_MC3_MISC 0x413
> +
> +/* Hardware P state interface */
> +#define MSR_PPERF0x64e
> +#define MSR_PERF_LIMIT_REASONS 0x64f
> +#define MSR_PM_ENABLE0x770
> +#define MSR_HWP_CAPABILITIES 0x771
> +#define MSR_HWP_REQUEST_PKG 0x772
> +#define MSR_HWP_INTERRUPT0x773
> +#define MSR_HWP_REQUEST 0x774
> +#define MSR_HWP_STATUS 0x777
>
> /* VIA MSR */
> #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature
> */
> Index: arch/i386/include/specialreg.h
> ===
> RCS file: /cvs/src/sys/arch/i386/include/specialreg.h,v
> retrieving revision 1.57
> diff -u -p -u -p -r1.57 specialreg.h
> --- arch/i386/include/specialreg.h3 Sep 2016 13:35:03 - 1.57
> +++ arch/i386/include/specialreg.h15 Sep 2016 10:36:48 -
> @@ -205,6 +205,8 @@
> */
> #define TPM_SENSOR 0x0001 /* Digital temp sensor */
> #define TPM_ARAT0x0004 /* APIC Timer Always Running */
> +#define TPM_PTM 0x0006 /* Package Thermal Management
> */
> +#define TPM_HWP 0x0007 /* Hardware P-states */
>
> /*
> * "Architectural Performance Monitoring" bits (CPUID function 0x0a):
> @@ -396,6 +398,16 @@
> #define MSR_MC3_STATUS 0x411
> #define MSR_MC3_ADDR 0x412
> #define MSR_MC3_MISC 0x413
> +
> +/* Hardware P state interface */
> +#define MSR_PPERF0x64e
> +#define MSR_PERF_LIMIT_REASONS 0x64f
> +#define MSR_PM_ENABLE0x770
> +#define MSR_HWP_CAPABILITIES 0x771
> +#define MSR_HWP_REQUEST_PKG 0x772
> +#define MSR_HWP_INTERRUPT0x773
> +#define MSR_HWP_REQUEST 0x774
> +#define MSR_HWP_STATUS 0x777
>
> /* VIA MSRs */
> #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature
> */
> Index: arch/amd64/amd64/identcpu.c
> ===
> RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v
> retrieving revision 1.74
> diff -u -p -u -p -r1.74 identcpu.c
> --- arch/amd64/amd64/identcpu.c 3 Sep 2016 12:12:43 - 1.74
> +++ arch/amd64/amd64/identcpu.c 15 Sep 2016 10:36:48 -
> @@ -199,6 +199,8 @@ const struct {
> }, cpu_tpm_eaxfeatures[] = {
> { TPM_SENSOR, "SENSOR" },
> { TPM_ARAT,
