On 23.8.2020. 16:50, Claudio Jeker wrote:
> On Sun, Aug 23, 2020 at 04:06:01PM +0200, Christian Weisgerber wrote:
>> Scott Cheloha:
>>
>>> This "it might slow down the network stack" thing keeps coming up, and
>>> yet nobody can point to (a) who expressed this concern or (b) what the
>>> penalty
On Sun, Aug 23, 2020 at 04:06:01PM +0200, Christian Weisgerber wrote:
> Scott Cheloha:
>
> > This "it might slow down the network stack" thing keeps coming up, and
> > yet nobody can point to (a) who expressed this concern or (b) what the
> > penalty is in practice.
>
> It was kettenis@ who
Scott Cheloha:
> This "it might slow down the network stack" thing keeps coming up, and
> yet nobody can point to (a) who expressed this concern or (b) what the
> penalty is in practice.
It was kettenis@ who simply raised the question and asked for
comments from the network people.
I think we
> Date: Sat, 22 Aug 2020 22:05:44 -0500
> From: Scott Cheloha
>
> On Tue, Jul 28, 2020 at 10:02:07AM +0300, Paul Irofti wrote:
> >
> > [...]
> >
> > Is the issue with LFENCE slowing down the network stack settled? That was
> > the argument against it last time.
>
> ... a month passes. Nobody
Hi,
As I see this is addressed to me I will reply. I am in the mountains until the
end of the month with poor internet connection.
First, it was not me that stated that the network stack is blocking the change.
Somebody said that during the initial development of the user timeclock when I
On Tue, Jul 28, 2020 at 10:02:07AM +0300, Paul Irofti wrote:
>
> [...]
>
> Is the issue with LFENCE slowing down the network stack settled? That was
> the argument against it last time.
... a month passes. Nobody says anything.
This "it might slow down the network stack" thing keeps coming
On 2020-07-27 18:24, Mark Kettenis wrote:
Date: Mon, 27 Jul 2020 17:14:21 +0200
From: Christian Weisgerber
Scott Cheloha:
--- lib/libc/arch/amd64/gen/usertc.c8 Jul 2020 09:17:48 - 1.2
+++ lib/libc/arch/amd64/gen/usertc.c25 Jul 2020 17:50:38 -
@@ -21,9 +21,12 @@
static
> Date: Mon, 27 Jul 2020 17:14:21 +0200
> From: Christian Weisgerber
>
> Scott Cheloha:
>
> > --- lib/libc/arch/amd64/gen/usertc.c8 Jul 2020 09:17:48 -
> > 1.2
> > +++ lib/libc/arch/amd64/gen/usertc.c25 Jul 2020 17:50:38 -
> > @@ -21,9 +21,12 @@
> > static inline
Scott Cheloha:
> --- lib/libc/arch/amd64/gen/usertc.c 8 Jul 2020 09:17:48 - 1.2
> +++ lib/libc/arch/amd64/gen/usertc.c 25 Jul 2020 17:50:38 -
> @@ -21,9 +21,12 @@
> static inline u_int
> rdtsc(void)
> {
> - uint32_t hi, lo;
> - asm volatile("rdtsc" : "=a"(lo),
On Fri, Jul 17, 2020 at 10:47:50AM -0900, Philip Guenther wrote:
> On Thu, Jul 16, 2020 at 4:55 PM Scott Cheloha
> wrote:
>
> > > On Jul 16, 2020, at 19:36, Theo de Raadt wrote:
> > >
> > >> Note the third sentence.
> > >>
> > >> Given that, I reason that a serializing instruction before *and*
On Thu, Jul 16, 2020 at 4:55 PM Scott Cheloha
wrote:
> > On Jul 16, 2020, at 19:36, Theo de Raadt wrote:
> >
> >> Note the third sentence.
> >>
> >> Given that, I reason that a serializing instruction before *and* after
> >> the RDTSC should freeze it in place.
> >
> > I haven't seen anyone
> On Jul 16, 2020, at 19:36, Theo de Raadt wrote:
>
>> Note the third sentence.
>>
>> Given that, I reason that a serializing instruction before *and* after
>> the RDTSC should freeze it in place.
>
> I haven't seen anyone read it that way.
They say that instructions after RDTSC can run
> Note the third sentence.
>
> Given that, I reason that a serializing instruction before *and* after
> the RDTSC should freeze it in place.
I haven't seen anyone read it that way.
On Thu, Jul 16, 2020 at 02:14:45PM +0200, Christian Weisgerber wrote:
> Scott Cheloha:
>
> > Can we add the missing LFENCE instructions to userspace and the
> > kernel? And can we excise the upper 32 bits?
>
> > + uint32_t lo;
> > +
> > + asm volatile("lfence");
> > + asm volatile("rdtsc"
> Date: Wed, 15 Jul 2020 20:36:04 -0500
> From: Scott Cheloha
>
> On Sat, Jul 11, 2020 at 01:16:43PM +0200, Mark Kettenis wrote:
> > > From: Paul Irofti
> > > Date: Sat, 11 Jul 2020 13:50:37 +0300
> > >
> > > On 2020-07-11 13:46, Mark Kettenis wrote:
> > > >> From: Paul Irofti
> > > >> Date:
Scott Cheloha:
> Can we add the missing LFENCE instructions to userspace and the
> kernel? And can we excise the upper 32 bits?
> + uint32_t lo;
> +
> + asm volatile("lfence");
> + asm volatile("rdtsc" : "=a"(lo));
That's wrong. rtdsc will clobber %rdx, whether you use that value
On Sat, Jul 11, 2020 at 01:16:43PM +0200, Mark Kettenis wrote:
> > From: Paul Irofti
> > Date: Sat, 11 Jul 2020 13:50:37 +0300
> >
> > On 2020-07-11 13:46, Mark Kettenis wrote:
> > >> From: Paul Irofti
> > >> Date: Sat, 11 Jul 2020 13:32:22 +0300
> > >>
> > >> Hi,
> > >>
> > >> Getting lots of
> From: Paul Irofti
> Date: Sat, 11 Jul 2020 13:50:37 +0300
>
> On 2020-07-11 13:46, Mark Kettenis wrote:
> >> From: Paul Irofti
> >> Date: Sat, 11 Jul 2020 13:32:22 +0300
> >>
> >> Hi,
> >>
> >> Getting lots of messages about people loving the new timekeep
> >> functionality, which I am very
On 2020-07-11 13:46, Mark Kettenis wrote:
From: Paul Irofti
Date: Sat, 11 Jul 2020 13:32:22 +0300
Hi,
Getting lots of messages about people loving the new timekeep
functionality, which I am very happy about, but also some that have the
skew too large for it to be enabled.
I plan on sending a
> From: Paul Irofti
> Date: Sat, 11 Jul 2020 13:32:22 +0300
>
> Hi,
>
> Getting lots of messages about people loving the new timekeep
> functionality, which I am very happy about, but also some that have the
> skew too large for it to be enabled.
>
> I plan on sending a diff next week to
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