Hi Bruce,
that would work too. We get 330fs jitter rms with this circuit using the
Fairchild UHS LVC family, that's pretty much the noise floor of the OCXO :)
If you use a bias network, you won't get 50% symmetry since it will never
perfectly match the inverter's inflection point (which
Hello Bruce,
I believe a driver for an FPGA running at 350MHz was the initial query, 6GHz
BW and crystal filters are probably overkill.
bye,
Said
In a message dated 7/31/2008 01:59:34 Pacific Daylight Time,
[EMAIL PROTECTED] writes:
Yes, however it is quieter and adding duty cycle
Two things NOT to do:
1. Do NOT use ECL. CMOS is much lower jitter.
2. Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based comparator.
---
Some things that you should do:
Make all circuitry differential if
Rick,
Can you explain #2?
I understand ECL has more jitter, so I understand excluding ECL based
comparators, but why excluding ALL comparators? It seems to me the
comparators allow tighter control of the threshold, so it sounds as if it
would help at very low frequencies, unless the higher 1/f
Comparators have very wideband, high gain inputs with typically
high noise figures. The effective input noise is determined by
the noise figure and the comparator bandwidth and the fact
the the comparator only utilizes a few mV of the input signal. If you are
trying to square up a 10 MHz signal,
I do agree with Richard, comparators are quite bad...
Having played with interfacing signals to FPGA 'ad nausea'
I found that the only simple scheme that works
better than biased (or feedback) cmos gates and of
course much better than ECL line receivers or comparators
(even cmos gates biased
The JPL paper is here: http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf
Pete Rawson
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In any event, if you actually test real comparators, you will
find them to be universally lousy. I will be happy to be proven
wrong if someone is aware of a good comparator. It's just that
I have never met I comparator I liked :-)
I think you're right about that. About the best thing you
I do agree with Richard, comparators are quite bad...
Having played with interfacing signals to FPGA 'ad nausea'
I found that the only simple scheme that works
better than biased (or feedback) cmos gates and of
course much better than ECL line receivers or comparators
(even cmos gates
Pete wrote:
The JPL paper is here: http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf
Pete Rawson
Pete
You can usually do much better than that.
The Collins paper indicates how.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=10665arnumber=494304type=ref
John Miles wrote:
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers has
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers has been faster
John Miles wrote:
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers
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