I have this (very smart) semi-retired design engineer friend named Craig who I
first queried about this clock issue.
We always enjoy getting together in his lab or sitting outside enjoying the
weather and good cigars.
As usual I bug him with my crazy ideas as a way to educate myself or
Interesting, I would have thought that the +12V input would be extremely
well regulated since its shared with the oven heater, I*R drops are going
to show up every where, if your looking for uV levels of stability.
Just a connector has milliohms of contact resistance, let alone routing and
If you are detecting events at 100Khz I think the best way is not to try
and time stamp each event. Even if only 32 bit time stamps are used you'd
have a 3.2 mega bit per second data rate for just the stamps. And the
possible error in the stamp approaches the time between samples
I think a
Hi
> On Oct 21, 2016, at 7:44 PM, Scott Stobbe wrote:
>
> A little more data on the 7912.
>
> The first plot shows the tempCo of the 7912 measured with ambient
> temperature swings "7912_TempCo.png". Which is -150 ppm/degC.
>
> The second plot is off a 7912 logged
If the heart of your clock is a micro, you may be able to reset the
processor and set the time once a second fastest enough not to have any
visual artifacts. Even if you have a perfect 32.768 kHz clock you still
have to set the phase (time) manually and deal with DST, leap seconds,
and power
Yo Chris!
On Thu, 20 Oct 2016 23:37:23 -0700
Chris Albertson wrote:
> I think your graph only shows 1/2 of the problem. It is the easy part
> because all that code is written and likely already installed on the
> OP's computer.
Yup, of course. But my actual results
Hi Jim,
I'm glad you mentioned the DS3231 aging trick. Many PIC's also have the ability
to digitally tune their internal low power oscillator. Attached is a plot
showing the 32 steps of the OSCTUNE register in a $1 8-pin PIC12F683.
Notice in the plot that the frequency adjustment range (and
Yo Chris!
On Thu, 20 Oct 2016 23:31:46 -0700
Chris Albertson wrote:
> You should expect the system time to have error on the order of about
> 10 microseconds
Check out the graaphs I sent earlier. On a RasPi I can get oue
standard deviation under 1 µs.
> The PPS
Yo David!
On Fri, 21 Oct 2016 09:00:33 +0100
"David J Taylor" wrote:
> I set up and configured a brand new xenial box using ntp, and let it
> run for a day (approx 7 hours).
NTPsec, or NTp Classic?
> remote refid st t when poll reach delay
I'm kind of late to the party on this one, but I think the simplest
approach with the least disturbance to the operation of the original
system would be to form a VCXO and PLL.
Good old 4000 series CMOS stuff should be plenty fast enough. Two pieces
should be sufficient. For example, a CMOS
On Thu, Oct 20, 2016 at 7:08 AM, Bob Camp wrote:
> One problem with a PLL and a 1 Hz input are the values of components
> you get in the loop.
> The other issue is the cost of the VCXO that will get
> you to 32,768 KHz.
>
As I mentioned earlier, the DS3231 chip (about $6.50 qty 1
On Fri, 21 Oct 2016 10:59:59 +0200, you wrote:
>On Fri, 21 Oct 2016 00:20:43 -0400
>Scott Stobbe wrote:
>
>> The bad side of a 7912 is in long-term stability and tempCo, the sample I
>> tested had at least a 150 ppm/degC tempCo, which is going to put a serious
>>
On Fri, 21 Oct 2016 06:14:03 -0700
Nick Sayer via time-nuts wrote:
> Well, because it's easily an order of magnitude more expensive than a 7912.
> $5 instead of 50¢ (Q:1).
>
> If it *matters*, then fine, but I am sensitive to cost efficiency in addition
> to efficacy.
Hi
At least in terms of voltage regulation (as opposed to noise), the -12V input
on the TBolt is
the *least* sensitive input on the TBolt. It’s issue is only in terms of PSRR.
The internals of
the unit take care of any drift or really low frequency stuff on the -12 input.
Bob
> On Oct 21,
Well, because it's easily an order of magnitude more expensive than a 7912. $5
instead of 50¢ (Q:1).
If it *matters*, then fine, but I am sensitive to cost efficiency in addition
to efficacy.
If you put the board in a box in a stable temperature environment (which I'd
kind of assume you'd do
Hi
> On Oct 21, 2016, at 12:20 AM, Scott Stobbe wrote:
>
> Nick had mention that the -12V rail on the thunderbolt has the poorest PSRR
> with respect to frequency output, so I first took a look at the venerable
> 7912.
>
> The first data-set was taken with a -13.5 VDC
> Le 20 oct. 2016 à 22:06, Hal Murray a écrit :
>
>
>> full disclosure: there were a couple of outlier external clocks I threw out,
>> one with a 38 ms offset and the other with a 112 ms offset).
>
> That's not uncommon. It happens more often when the server is
it's a BC546, 10k collector resistor... I thought it was fast enough,
but also think the signal is inverted, since there's passive quenching
in this circuit, so the breakdown voltage of the APD is lowering too
slowly before next photon, causing this kind of positive edge.. if you
see well
What is the circuit driving that signal ? It appears to have too little
positive drive to overcome the capacitance. Perhaps it's an open collector
with too large a pull-up ?
On 21 Oct 2016 12:23 a.m., "Ilia Platone" wrote:
> sorry, no attachment, this mail contains two
I really think that a wired correlator would be the best choice... using
an FPGA :)
Best Regards,
Ilia.
On 10/21/16 06:45, Bruce Griffiths wrote:
Another issue is that the finer the timestamp quantisation step size the larger
the signal of interest (Intensity correlation). The signal doesn't
On Fri, 21 Oct 2016 10:59:59 +0200
Attila Kinali wrote:
> And while you are at it, use three LT3090 for the positive supplies :-)
Ermm... LT3045
Attila Kinali
--
Malek's Law:
Any simple idea will be worded in the most complicated way.
On Fri, 21 Oct 2016 00:20:43 -0400
Scott Stobbe wrote:
> The bad side of a 7912 is in long-term stability and tempCo, the sample I
> tested had at least a 150 ppm/degC tempCo, which is going to put a serious
> lump/bump in the 10s tau to gps crossover point on an allan
On Thu, 20 Oct 2016 21:45:42 +
Ilia Platone wrote:
> >> I will be interested to see what is recommended for a 100 kHz event rate.
> > This is actually a very tough question. 100kHz means that for each event
> > there is only 10µs available for detection, processing and
Wow .. 24kW for a clock display !
On Fri, Oct 21, 2016 at 6:56 AM, Todd Caldwell wrote:
> Hi All,
>
> I've been lurking and assembling gear for the most part, so this is my
> first post I think.
>
> I was at KSC in May of 2010 for the launch of STS-132. Attached is a
More followup:
I set up and configured a brand new xenial box using ntp, and let it run
for a day (approx 7 hours). Here are the ntpq -p from that:
$ ntpq -p
remote refid st t when poll reach delay offset
jitter
Another issue is that the finer the timestamp quantisation step size the larger
the signal of interest (Intensity correlation). The signal doesn't vanish as
the timestamp quantisation step size increases however the signal decreases
requiring a longer observation time to achieve a given SNR.
On Thu, Oct 20, 2016 at 12:02 AM, Gary E. Miller wrote:
I think your graph only shows 1/2 of the problem. It is the easy part
because all that code is written and likely already installed on the OP's
computer.
The other half of the problem is responding to events and getting
On Wed, Oct 19, 2016 at 11:15 PM, Ilia Platone wrote:
> I need to know how much precise this system can be. How much resolution
> can I obtain with a cheap receiver (maximum quantization frequency)?
> Formulas are well accepted.
Even a cheap receiver will have error that
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