The clock-correction seemed a bit crude. I expected to find a PI-filter
and a phase-accumulator to steer the 300 MHz to 37 MHz synthesis.
Actually I do use a phase accumulator, in Fig. 26 it's inside the binary
search block. The phase is accumulated during several seconds (longer for
a noisy
to hear your feedback.
--Daniel Engeler
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Hi Attila
Thanks for the feedback.
* you have a lot of simulation and measurments on BER vs SNR. For time-nutty
needs that's not so relevant. An ADEV plot would be much more informative
on the stability.
* Also some data on the absolute timing variations vs time would be
nice to have.
Yes
