In message 4ab6b76d.1010...@rubidium.dyndns.org, Magnus Danielson writes:
Seems less likely. I was pondering if the power line frequency was doing
some nice beat frequency with the system...
1250 seconds at 50Hz = 62500 periods.
Assume one extra period over 1250 seconds: 62500 + 1 = 62501
Poul-Henning Kamp wrote:
In message 4ab6b76d.1010...@rubidium.dyndns.org, Magnus Danielson writes:
Seems less likely. I was pondering if the power line frequency was doing
some nice beat frequency with the system...
1250 seconds at 50Hz = 62500 periods.
Assume one extra period over 1250
And a FYI - it was 60 hertz power here
Magnus Danielson wrote:
Poul-Henning Kamp wrote:
In message 4ab6b76d.1010...@rubidium.dyndns.org, Magnus Danielson
writes:
Seems less likely. I was pondering if the power line frequency was
doing some nice beat frequency with the system...
1250
Brian Kirby wrote:
And a FYI - it was 60 hertz power here
Never let flimsy details like facts derail a perfectly good theory.
(That's about 13,33 ppm BTW)
Cheers,
Magnus
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-nuts] Jitter Test on Dividers
I ran a 24 hour test on the async dividers (74HC390s) that Tom Clark
designed and they basically have a triangular peak to peak jitter of 500
picoseconds over 22 minutes. The baseline drift started at reference
0 ns and made a negative parabola that dipped
John Miles wrote:
Interesting! 500 picoseconds is a lot of drift. Can you try 74AC390s as
well?
While that may be interesting, I think we should stop here and think a
little... where would a seemingly stable oscillation/beat frequency with
a period of about 1250 seconds (4 cycles in 5000
...@febo.com [mailto:time-nuts-boun...@febo.com]on
Behalf Of Brian Kirby
Sent: Sunday, September 20, 2009 2:19 PM
To: precise time
Subject: [time-nuts] Jitter Test on Dividers
I ran a 24 hour test on the async dividers (74HC390s) that Tom Clark
designed and they basically have a triangular peak
Magnus Danielson wrote:
John Miles wrote:
Interesting! 500 picoseconds is a lot of drift. Can you try 74AC390s as
well?
While that may be interesting, I think we should stop here and think a
little... where would a seemingly stable oscillation/beat frequency
with a period of about 1250
Bruce Griffiths wrote:
Not surprising, given that there is typically about 30ns clock to output
delay per HC390 (divide by 2 and divide by 5 asynchronously cascaded)
with 7 asynchronously cascaded 390's between the 10MHz clock input and a
1PPS output having a typical total clock to output delay
Bruce Griffiths wrote:
Magnus Danielson wrote:
John Miles wrote:
Interesting! 500 picoseconds is a lot of drift. Can you try 74AC390s as
well?
While that may be interesting, I think we should stop here and think a
little... where would a seemingly stable oscillation/beat frequency
with a
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