So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
CMOS is actually among the cleanest logic families for digital PLLs these
days. ECL has always been among the worst. It was used
So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
- The logic supplies should be well regulated, distributed
and decoupled.
- Make the PRF to the P/F detector as high as
