Jitter specs assume a logic
waveform input, not a sine wave input. Many jitter specs refer to
pattern jitter of data, which does not apply to clocks. Also, jitter
increases at low frequencies in practice, even though in theory it
should not. Like I said, this topic is very tricky.
How
Bob Paddock wrote:
Jitter specs assume a logic
waveform input, not a sine wave input. Many jitter specs refer to
pattern jitter of data, which does not apply to clocks. Also, jitter
increases at low frequencies in practice, even though in theory it
should not. Like I said, this topic is
Hi Bruce,
that would work too. We get 330fs jitter rms with this circuit using the
Fairchild UHS LVC family, that's pretty much the noise floor of the OCXO :)
If you use a bias network, you won't get 50% symmetry since it will never
perfectly match the inverter's inflection point (which
Hello Bruce,
I believe a driver for an FPGA running at 350MHz was the initial query, 6GHz
BW and crystal filters are probably overkill.
bye,
Said
In a message dated 7/31/2008 01:59:34 Pacific Daylight Time,
[EMAIL PROTECTED] writes:
Yes, however it is quieter and adding duty cycle
Two things NOT to do:
1. Do NOT use ECL. CMOS is much lower jitter.
2. Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based comparator.
---
Some things that you should do:
Make all circuitry differential if
of precise time and frequency measurement
Subject: Re: [time-nuts] What is a Time-Nut grade Zero
Crossing Circuit?
Two things NOT to do:
1. Do NOT use ECL. CMOS is much lower jitter.
2. Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based
-nuts] What is a Time-Nut grade Zero
Crossing Circuit?
Two things NOT to do:
1. Do NOT use ECL. CMOS is much lower jitter.
2. Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based comparator.
___
time
Subject: Re: [time-nuts] What is a Time-Nut grade Zero
Crossing Circuit?
Two things NOT to do:
1. Do NOT use ECL. CMOS is much lower jitter.
2. Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based comparator
The JPL paper is here: http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf
Pete Rawson
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and follow the instructions there.
In any event, if you actually test real comparators, you will
find them to be universally lousy. I will be happy to be proven
wrong if someone is aware of a good comparator. It's just that
I have never met I comparator I liked :-)
I think you're right about that. About the best thing you
I do agree with Richard, comparators are quite bad...
Having played with interfacing signals to FPGA 'ad nausea'
I found that the only simple scheme that works
better than biased (or feedback) cmos gates and of
course much better than ECL line receivers or comparators
(even cmos gates
Pete wrote:
The JPL paper is here: http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf
Pete Rawson
Pete
You can usually do much better than that.
The Collins paper indicates how.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=10665arnumber=494304type=ref
John Miles wrote:
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers has
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers has been faster
John Miles wrote:
Modern ECL parts aren't necessarily that bad compared to the old MECL
stuff.
My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago. I designed many synthesizers around them
for Zeta Labs. Every newer family of ECL line receivers
Can you point me to a Time-Nut grade Zero Crossing
circuit that I can feed a Actel Igloo FPGA (It doesn't
like sine waves)?
For the sake of discussion the source signal
is a ThunderBolt at 10 MHz.
The FPGA is rated to 350 MHz, so no need to have
a 5. GHz Zero Crossing circuit.
Hi Bob,
since the sine wave is symmetric, you can use a simple LVC type CMOS
inverter with 1M Ohm resistor from input to output, and a 100nF cap (or the
largest
COG cap you can find) from the input of the inverter to the sine wave output.
You may also want to load the sine wave output
[EMAIL PROTECTED] wrote:
Hi Bob,
since the sine wave is symmetric, you can use a simple LVC type CMOS
inverter with 1M Ohm resistor from input to output, and a 100nF cap (or the
largest
COG cap you can find) from the input of the inverter to the sine wave output.
You may also
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